DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 01/03/24 & 06/13/25 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 13-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 13 recites “providing a circuit substrate and a chip;… forming an auxiliary structure between the circuit substrate and the chip;…” (emphasis added). The underlined portion covers a scenario where the auxiliary is structure is formed either on the chip or the circuit substrate so as to be present between the chip and the circuit substrate when later bonded, but also covers a scenario wherein the chip and substrate are pre-positioned with an empty gap therebetween and then the auxiliary structure is formed or inserted so as to fill the said empty gap. There is no description and supporting drawings for the second scenario and therefore Applicants cannot claim it with the claim language pointed out above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15 and 16-18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites “the thickness” and claim 16 recites “the materials”. There are insufficient antecedent basis for those limitations in the claims.
Claim 16 recites “solid-solved”. This expression does not exist in the conventional English language and it is unclear what that means. Even if viewed as a composite expression, “solve” means “finding a solution, explanation or answer for” according to the Webster online dictionary, so “solved” would implicitly means “solution or explanation or answer found”, so “solid-solved” would mean a solid to which an answer or explanation or solution was found and this does not make any sense in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 7-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fang (US 2021/0134711).
a. Re claim 1, Fang discloses a semiconductor package device 2a (see figs. 1-3&6 and related text; see remaining of disclosure for more details), comprising: a circuit substrate 3&18&19 ([0047], [0044]) having a first terminal end (leftmost unlabeled pad 191; [0044]); a chip 12b ([0039]) disposed on the circuit substrate and having a conductive pad (leftmost unlabeled connecting member 128; ([0039]); an auxiliary structure (leftmost unlabeled layer 17; [0045]) disposed between the first terminal end and the conductive pad, wherein the chip is electrically connected to the circuit substrate through the auxiliary structure; and a protective layer 16 ([0042]) disposed on the circuit substrate and surrounding the chip, wherein in a direction (horizontal direction in a landscape view of fig. 6) perpendicular to a normal direction (vertical direction) of the semiconductor package device, the first terminal end has a first width (explicit on fig. 6), the auxiliary structure has a second width (width at the interface with 191 or width at the interface with 128), and the first width is greater than or equal to the second width (explicit on fig. 6).
b. Re claim 2, in the direction perpendicular to the normal direction of the semiconductor package device, the conductive pad has a third width (explicit on fig. 6), and the third width is smaller than the first width (explicit on fig. 6).
c. Re claim 3, the semiconductor package device as claimed in claim 1, further comprises an intermediate layer 14 ([0041]) disposed between the circuit substrate and the chip.
d. Re claim 4, the circuit substrate has a second terminal end 39 ([0048]), the second terminal end is opposite to the first terminal end, wherein the second terminal end and one side (left side) of the chip are misaligned with each other (explicit on fig. 6).
e. Re claim 7, a projection of the conductive pad onto a plane (horizontal plane perpendicular to the plane of fig. 6) perpendicular to the normal direction of the semiconductor package device is smaller than a projection of the auxiliary structure onto the plane perpendicular to the normal direction of the semiconductor package device (this is implicit in view of fig. 6 noting that a width of 128 is smaller than a width of 19 at the interface with 17).
f. Re claim 8, the protective layer comprises first filler particles 164 (see fig. 2, [0042]).
g. Re claim 9, the semiconductor package device as claimed in claim 8, further comprises an intermediate layer 14 disposed between the circuit substrate and the chip, and the intermediate layer comprises second filler particles 144 (fig. 2, [0042]).
h. Re claim 10, a particle size of the second filler particles is smaller than a particle size of the first filler particles (fig. 2, [0042-[0043]).
i. Re claim 11, the semiconductor package device as claimed in claim 1, further comprises an electronic component 12a ([0039]) disposed on the circuit substrate.
Claim(s) 1, 4 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. (US 2011/0297425).
a. Re claim 1, Nakamura et al. disclose a semiconductor package device 70 (see fig. 24 and related text; see [0140] and remaining of disclosure for more details), comprising: a circuit substrate 10 ([0140]) having a first terminal end 11 ([0043]); a chip 71 ([0140]) disposed on the circuit substrate and having a conductive pad 73 ([0141]); an auxiliary structure 74 ([0142]) disposed between the first terminal end and the conductive pad, wherein the chip is electrically connected to the circuit substrate through the auxiliary structure; and a protective layer 75 ([0140]) disposed on the circuit substrate and surrounding the chip, wherein in a direction (horizontal direction in a landscape view of fig. 24) perpendicular to a normal direction (vertical direction) of the semiconductor package device, the first terminal end has a first width (explicit on fig. 24), the auxiliary structure has a second width (width at the interface with 11), and the first width is greater than or equal to the second width (explicit on fig. 24).
b. Re claim 4, the circuit substrate has a second terminal end 15 ([0143]), the second terminal end is opposite to the first terminal end, wherein the second terminal end and one side (left side) of the chip are misaligned with each other (explicit on fig. 24).
c. Re claim 5, the second terminal end has a concave surface 15x ([0052]).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 2019/0252306).
a. Re claim 13, Park discloses a method for forming a semiconductor package device, comprising: providing a circuit substrate 10 and a chip 120 (see (figs. 3-17&35A and related text; see also [0041] and [0098] as well as remaining of disclosure for more details); forming an auxiliary material pattern 20ap (fig. 12, [0055]) on the circuit substrate, the chip, or a combination thereof; forming an auxiliary structure 124 (fig. 35A, [0098]) between the circuit substrate and the chip (see fig. 35A); and forming a protective layer 140 (fig. 35A, [0098]) on the circuit substrate and surrounding the chip.
b. Re claim 14, the step of forming the auxiliary material pattern comprises a step of forming an auxiliary material layer 20a (fig. 11, [0054]) comprising an auxiliary material (copper as per [0054]) on the circuit substrate, the chip, or a combination thereof and a step of patterning the auxiliary material layer to form the auxiliary material pattern (fig. 12, [0055]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 2007/0030628).
a. Re claim 1, Yamamoto et al. disclose a semiconductor package device, comprising: a circuit substrate 11&31&32 (see fig. 9 and related text; see remaining of disclosure for more details) having a first terminal end 44 ([0193]); a chip 21 ([0193]) disposed on the circuit substrate and having a conductive pad 22; an auxiliary structure 45 ([0193]) disposed between the first terminal end and the conductive pad, wherein the chip is electrically connected to the circuit substrate through the auxiliary structure; wherein in a direction (horizontal direction in a landscape view of fig. 9) perpendicular to a normal direction (vertical direction) of the semiconductor package device, the first terminal end has a first width (explicit on fig. 9), the auxiliary structure has a second width (explicit on fig. 9), and the first width is greater than or equal to the second width (explicit on fig. 9). But Yamamoto et al. do not appear to explicitly disclose a protective layer disposed on the circuit substrate and surrounding the chip.
However, it is conventionally known in the art to provided encapsulant surrounding chips in order to seal and protect them from environmental contaminants and mechanical damage. As such, it would have been obvious to one skilled in the art before the effective filing of the invention to have provided an encapsulant (protective layer) disposed on the circuit substrate and surrounding the chip in order to seal and protect them from environmental contaminants and mechanical damage (see MPEP 2144.I&II).
b. Re claim 12, the semiconductor package device as claimed in claim 1, further comprises an electronic component 101 ([0193]) disposed in the circuit substrate.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2019/0252306).
Re claim 15, Park discloses all the limitations of claim 13 as stated above except explicitly that the thickness of the auxiliary material layer is 20 nm-1000 nm. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the thickness of the auxiliary material layer to be 20 nm-1000 nm in order to obtain a thinner and lighter wiring substrate (thus lighter weight) for the package 200 on fig. 35A (see MPEP 2144.I&II).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lu (US 2019/0053373), Kim (US 2023/0134201) and Nishimura et al. (US 2023/0319992) disclose structures similar to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899