DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Group III, in the reply filed on July 30, 2026 is acknowledged.
Amendment filed July 30, 2026 is acknowledged. New claims 21-36 have been added. Claims 1-16 have been cancelled. Claim have been amended. Claims are pending.
Action on merits of claims follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 22, 2025 has been considered by the examiner.
Specification
Amendment to the Specification is acknowledged.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
METHOD FOR FORMING TRANSISTORS HAVING SOURCE/DRAIN REGIONS INCLUDING ANTIMONY (Sb) OHMIC CONTACT LAYER BETWEEN PLATINUM ELECTRODE AND TWO-DIMENSIONAL (2D) SEMICONDUCTOR CHANNEL LAYER
Drawings
The drawings were received on July 30, 2026. These drawings are acceptable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over LIN et al. (US. Pub. No. 2020/0006541) of record.
With respect to claim 1, LIN teaches a method substantially as claimed including:
forming a dielectric layer (212) over a substrate (210);
forming a first 2D semiconductor layer (222) and a second 2D semiconductor layer (222, not shown but similar to the first 2D semiconductor layer (222)) over the dielectric layer (212);
forming a first antimony layer (230(1)) and a second antimony layer (230(2)) in contact with opposite sides of the first 2D semiconductor layer (222);
forming a third antimony layer (230(3), not shown) and a fourth antimony layer (230(4), not shown) in contact with opposite sides of the second 2D semiconductor layer (222, not shown), wherein the first antimony layer (230(1)) has a thickness and the third antimony layer (230(3), not shown) has a thickness; and
forming a first platinum layer (240(1)), a second platinum layer (240(2)), over opposite sides of the first 2D semiconductor layer (222), and a third platinum layer (240(3), not shown), and a fourth platinum layer (240(4), not shown) over opposite sides of the second 2D semiconductor layer (222, not shown), respectively. (See FIG. 2G).
Note that, although LIN does not show a second device having the same elements as that of the first device, i.e., 2D semiconductor layer, antimony layers in contact with opposite sides of the 2D semiconductor layer and platinum layers over the antimony layers.
However, LIN explicitly discloses a method for forming semiconductor devices, e.g., transistors. Thus, forming a second semiconductor device or second transistor, is just repeat the same method as that of the first semiconductor device (250). Hence, indicated as “not shown”, as above.
Thus, LIN is shown to teach all the features of the claim with the exception of explicitly disclosing the third antimony layer has a thickness greater than a thickness of the first antimony layer.
Note that, the claimed thickness of one antimony layer being greater than another antimony layer is not critical.
However, the “antimony layer” in contact with the 2D semiconductor layer has formed an ohmic contact of close to zero Schottky barrier height, thus, the thickness of the one antimony layer being greater than or less than, the other antimony layer would not alter, i.e., enhance or reduce, the functionality of the contact as a whole.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor devices of LIN having the ohmic contact, between the antimony layer and the 2D semiconductor layer, wherein one antimony layer having the thickness that is greater or less than the other antimony layer, is an obvious design choice, since the ohmic contact has been formed.
Note that the specification contains no disclosure of either the critical nature of the claimed “a thickness of one antimony layer being greater or less than the other antimony layer” of any unexpected results arising therefrom. Where patentability is aid to based upon particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
With respect to claim 18, forming the first 2D semiconductor layer (222) and the second 2D semiconductor layer (not shown) of LIN comprises: forming a first transition metal layer (222, TMD) and a second transition metal layer (TMD, not shown) over the dielectric layer (212); and
selenizing the first transition metal layer (222) and the second transition metal layer (222) into the first 2D semiconductor layer (222) and the second 2D semiconductor layer (222).
With respect to claim 20, the fourth antimony layer (230(4)) has a thickness greater than a thickness of the second antimony layer (230(2)). See claim 17 above.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over LIN ‘541 as applied to claim 17 above, and further in view of LAJOIE et al. (US. Pub. No. 2020/0411520).
LIN teaches the method as described in claim 17 above including: forming the dielectric layer over the substrate.
Thus, LIN is shown to teach all the features of the claim with the exception of explicitly disclosing forming a back gate structure.
However, LAJOIE teaches a method including:
forming a dielectric layer (245) over a substrate (251); and
forming a back gate structure (236) over the substrate (251), wherein the dielectric layer (235) is formed over the back gate structure (236). (See FIG. 2).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of LIN including forming the back gate as taught by LAJOIE for the same intended purpose of controlling the transistors.
Forming a transistor with a front gate or back gate is within the ability of one having ordinary skill in the art.
Allowable Subject Matter
Claims 21-36 are allowed.
The following is an examiner’s statement of reasons for allowance: prior art of record particularly LIN’541 or LAJOIE ‘520 fails to teach a method in the combination of the limitations as claimed including:
forming a patterned mask layer covering the second portion of the first semimetal layer while leaving the first portion exposed;
etching back the exposed first portion of the first semimetal layer by using the patterned mask layer as an etch mask, to form a thinned semimetal layer having a thickness less than a thickness of the second portion of the first semimetal layer;
removing the patterned mask layer; and after removing the patterned mask layer, forming second semimetal layers over the thinned semimetal layer and over the second portion of the first semimetal layer, the second semimetal layers having a material different than a material of the first semimetal layer. (As recited in claim 21).
Or
forming a patterned mask layer covering the first 2D semiconductor layer and the second 2D semiconductor layer;
etching the interlayer dielectric layer by using the patterned mask layer as an etch mask to form source/drain contact openings exposing opposite side surfaces of the first 2D semiconductor layer and opposite side surfaces of the second 2D semiconductor layer;
forming first semimetal layers in the source/drain contact openings and on the opposite side surfaces of the first 2D semiconductor layer, and second semimetal layers in the source/drain contact openings and on the opposite side surfaces of the second 2D semiconductor layer, the second semimetal layers having a thickness greater than a thickness of the first semimetal layers;
forming third semimetal layers respectively over the first semimetal layers and the second semimetal layers, the third semimetal layers having a same thickness; and
lifting off the patterned mask layer to remove portions of the third semimetal layers overlying the patterned mask layer. (As recited in claim 29).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (See PTO-892).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANH D MAI/Primary Examiner, Art Unit 2893
