Attorney’s Docket Number: TSMP20231203US02
Filing Date: 1/3/2024
Claimed Domestic Priority Date: 9/22/2023 (PRO 63/584,561)
Applicant(s): Ting et al.
Examiner: Rianna B. Greer
DETAILED ACTION
This Office action responds to the application filed on 1/3/2024.
Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/402,944 filed on 1/3/2024 has been entered. Pending in this Office action are claims 1-20.
Drawings
2. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the specification: S1 in Fig. 3.
3. The drawings are additionally objected to because of misspellings in Fig. 36. In process 206, “Deposititng a metal seed layer” should read --Depositi222, “Forming a via opning” should read --Forming a via opening--.
4. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
5. The disclosure is objected to because of the following informalities:
- In Par. [0008], “Figure 5 illustrates a top view of transition region with gradient pattern densities in accordance with some embodiments.” should read --Figure 5 illustrates a top view of a transition region with gradient pattern densities in accordance with some embodiments.--
- In Par. [0043], “The pattern density of PD54F may be calculated based a ring-shaped chip area with a width W3 greater than 1.5 µm, or the entire area of the functional circuit zone 58F.” should read --The pattern density of PD54F may be calculated based on a ring-shaped chip area with a width W3 greater than 1.5 µm, or the entire area of the functional circuit zone 58F.--
- In Par. [0066], “Dielectric layers 50A, 50B, and 50C are collective referred to as dielectric layer 50.” should read --Dielectric layers 50A, 50B, and 50C are collectively referred to as dielectric layer 50.--
- In Par. [0073], “One or more, or all of SoC package SoC-1, SoC-2, and SoC-3 may adopt the structure of device die 20' in any combination.” should read --One or more, or all of SoC packages SoC-1, SoC-2, and SoC-3 may adopt the structure of device die 20' in any combination.--
- In Par. [0082], “In an embodiment, the forming the passive device comprises forming an inductor, and wherein the forming the inductor comprises forming and interconnecting a plurality of redistribution lines. In an embodiment, the method further comprises bonding the device die to a package component, wherein the first plurality of bond pads and the second plurality of bond pads are physically bonded to additional bond pads of the package component. In an embodiment, the forming the first plurality of bond pads and the forming the second plurality of bond pads comprise forming a dielectric layer; etching the dielectric layer to form a plurality of openings; filling a conductive material in the plurality of openings; and performing a planarization process to level top surfaces of the dielectric layer and the conductive material, wherein remaining portions of the conductive material comprise the first plurality of bond pads and the second plurality of bond pads.” should read --In an embodiment, the forming of the passive device comprises forming an inductor, and wherein the forming of the inductor comprises forming and interconnecting a plurality of redistribution lines. In an embodiment, the method further comprises bonding the device die to a package component, wherein the first plurality of bond pads and the second plurality of bond pads are physically bonded to additional bond pads of the package component. In an embodiment, the forming of the first plurality of bond pads and the forming of the second plurality of bond pads comprises forming a dielectric layer; etching the dielectric layer to form a plurality of openings; filling a conductive material in the plurality of openings; and performing a planarization process to level top surfaces of the dielectric layer and the conductive material, wherein remaining portions of the conductive material comprise the first plurality of bond pads and the second plurality of bond pads.--
Appropriate corrections are required.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1, 7, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US2021/0066192, hereinafter Chen-192).
9. Regarding Claim 1, Chen-192 (see, e.g., Figs. 1A-1K, 2A-2B, and 3) shows all aspects of the instant invention including a method comprising:
- forming a function circuit (e.g., device 120 including active components) on a semiconductor substrate (e.g., semiconductor substrate 110) of a device die (e.g., wafer substrate WS, where Par. [0053]: wafer substrate WS is divided into a plurality of dies 100), wherein the function circuit is in a functional circuit zone (e.g., first region R1) of the device die (e.g., Fig. 1A and Par. [0012]: semiconductor substrate 110 has a device 120 formed therein)
- forming a passive device (e.g., inductor 600) over the semiconductor substrate, wherein the passive device is in a passive device zone (e.g., second region R2) of the device die (e.g., Fig. 1I)
- forming a first plurality of bond pads (e.g., bonding pads 174) in the functional circuit zone and at a surface (e.g., active surface AS1) of the device die, wherein the first plurality of bond pads have a first pattern density (e.g., Fig. 1C)
- forming a second plurality of bond pads (e.g., dummy bonding pads 176) in the passive device zone and at the surface (e.g., active surface AS1) of the device die, wherein the second plurality of bond pads have a second pattern density lower than the first pattern density (e.g., Fig. 2A and Par. [0022]: a pattern density of the bonding pads 174 is greater than a pattern density of the dummy bonding pads 176) (e.g., Fig. 1C)
10. Regarding Claim 7, Chen-192 (see, e.g., Figs. 1I and 3) shows that forming the passive device comprises forming an inductor (e.g., inductor 600), and wherein the forming the inductor comprises forming and interconnecting a plurality of redistribution lines (e.g., Par. [0047]: inductor 600 is embedded in the redistribution structure 500; inductor 600 and bottommost conductive patterns 504 may be simultaneously formed through the same process).
11. Regarding Claim 10, Chen-192 (see, e.g., Fig. 2A) shows that a ratio of the second pattern density to the first pattern density is smaller than about 0.3 (e.g., Par. [0022]: a ratio of the pattern density of the dummy bonding pads 176 to the pattern density of the bonding pads 174 ranges from 1:2.7 to 1:27).
Claim Rejections - 35 USC § 103
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. Claims 2-3, 5-6, 8, 11-12, 14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US2021/0066192, hereinafter Chen-192) in view of Chen et al. (US2019/0123006, hereinafter Chen-006).
14. Regarding Claim 2, Chen-192 is silent about forming a third plurality of bond pads in a transition zone and at the surface of the device die, wherein the transition zone is between the passive device zone and the functional circuit zone, and wherein the third plurality of bond pads have a third pattern density lower than the first pattern density. Chen-006 (see, e.g., Figs. 6A-6B and Pars. [0025], [0049], and [0073]) on the other hand and in the same field of endeavor, teaches a semiconductor package featuring a gradual decrease in pattern density for bonding pads (e.g., first, fifth, and second bonding pads 110, 130, and 120) from a central zone (e.g., central region 150) to an outer zone encircling it (e.g., edge region 152) using a plurality of transition zones (e.g., middle region 154, see Par. [0048]: middle region 154 can further include a first middle region 1541 to an (n)th middle region 154n, and the (n)th middle region 154n surrounds the (n−1) middle region 154(n−1)) to mitigate the effects of misalignment of bonding pads in the outer zone that can arise when stacking dies by enabling partial contact between the bonding pads of both dies through a gradual increase in bonding pad size, ensuring electrical connection and improving the performance and reliability of the semiconductor package.
15. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form a third plurality of bond pads in a transition zone and at the surface of the device die, wherein the transition zone is between the passive device zone and the functional circuit zone, and wherein the third plurality of bond pads have a third pattern density lower than the first pattern density, in the structure of Chen-192, as taught by Chen-006, to mitigate the effects of bonding pad misalignment and improve the performance and reliability of the semiconductor package.
16. Regarding Claim 3, Chen-006 (see, e.g., Figs. 6A-6B) teaches that the third pattern density (e.g., fifth bonding pads 130 in middle region 154) is greater than the second pattern density (e.g., first bonding pads 110 in central region 150).
17. Regarding Claim 5, Chen-006 (see, e.g., Figs. 6A-6B) teaches that the transition zone (e.g., middle region 154) has a ring shape encircling the passive device zone (e.g., central region 150).
18. Regarding Claim 6, Chen-006 (see, e.g., Figs. 6A-6B) teaches that the third pattern density is gradient, with pattern densities in portions of the transition zone (e.g., middle region 154) closer to the passive device zone (e.g., central region 150) being lower than pattern densities in portions of the transition zone closer to the functional circuit zone (e.g., edge region 152) (e.g., Par. [0048]: bonding pads in the (n)th middle region 154n include a width greater than the bonding pads in the (n−1)th middle region 154(n−1)).
19. Regarding Claim 8, while Chen-192 (see, e.g., Fig. 1D) shows that the method further comprises bonding the device die (e.g., wafer substrate WS, where Par. [0053]: wafer substrate WS is divided into a plurality of dies 100) to a package component (e.g., die 200), wherein the first plurality of bond pads (e.g., bonding pads 174) is physically bonded to additional bond pads (e.g., bonding pads 274) of the package component, they are silent about the second plurality of bond pads being physically bonded to additional bond pads of the package component. Chen-006 (see, e.g., Fig. 5 and Pars. [0025] and [0044]), on the other hand and in the same field of endeavor, teaches a semiconductor package (e.g., semiconductor structure 320) wherein a device die (e.g., semiconductor structure 200a) is bonded to a package component (e.g., semiconductor structure 100a), wherein the first plurality of bond pads (e.g., fourth bonding pads 220) and the second plurality of bond pads (e.g., third bonding pads 210) are physically bonded to additional bond pads (e.g., first bonding pads 110 and second bonding pads 120a) of the package component, to better enable electrical connection between package components.
20. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the second plurality of bond pads physically bonded to additional bond pads of the package component in the structure of Chen-192, because additional bonding pads are known in the semiconductor art for providing additional electrical contacts, as suggested by Chen-006, and implementing a known electrical connection arrangement for its conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
21. Regarding Claim 11, Chen-192 (see, e.g., 2A-2B, 3, and 4) shows most aspects of the instant invention including a structure comprising:
- a device die (e.g., die 100) comprising:
- a functional circuit zone (e.g., first region R1)
- a first plurality of bond pads (e.g., bonding pads 174) in the functional circuit zone, wherein the functional circuit zone has a first pattern density of bond pads
- a functional circuit (e.g., device 120 including active components) in the functional circuit zone and underlying the first plurality of bond pads
- a passive device zone (e.g., second region R2)
- a passive device (e.g., inductor 600) in the passive device zone
- a second plurality of bond pads (e.g., dummy bonding pads 176) in the passive device zone and over the passive device (see, e.g., Fig. 4 and Par. [0055]: inductor 600 is located directly below the dummy bonding pads 176), wherein the passive device zone has a second pattern density of bond pads, and the second pattern density is lower than the first pattern density (e.g., Fig. 2A and Par. [0022]: a pattern density of the bonding pads 174 is greater than a pattern density of the dummy bonding pads 176)
22. However, Chen-192 is silent about both a transition zone between the functional circuit zone and the passive device zone and a third plurality of bond pads in the transition zone, wherein the transition zone has a third pattern density of bond pads, and the third pattern density is lower than the first pattern density and greater than the second pattern density. Chen-006 (see, e.g., Figs. 6A-6B and Pars. [0025], [0049], and [0073]) on the other hand and in the same field of endeavor, teaches a semiconductor package featuring a gradual decrease in pattern density for bonding pads (e.g., first, fifth, and second bonding pads 110, 130, and 120) from a central zone to an outer zone encircling it using a transition zone (e.g., middle region 154) to mitigate the effects of misalignment of bonding pads in the outer zone that can arise when stacking dies by enabling partial contact between the bonding pads of both dies through a gradual increase in bonding pad size, ensuring electrical connection and improving the performance and reliability of the semiconductor package.
23. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have both a transition zone between the functional circuit zone and the passive device zone and a third plurality of bond pads in a transition zone and at the surface of the device die, wherein the transition zone is between the passive device zone and the functional circuit zone, and wherein the third plurality of bond pads have a third pattern density lower than the first pattern density, in the structure of Chen-192, as taught by Chen-006, to mitigate the effects of bonding pad misalignment and improve the performance and reliability of the semiconductor package.
24. Regarding Claim 12, Chen-192 shows that the second plurality of bond pads (e.g., dummy bonding pads 176) comprises electrically floating bond pads (see, e.g., Fig. 4 and Par. [0017]: the dummy bonding pads 176 are not connected to the interconnection structure 130 and are electrically floating).
25. Regarding Claim 14, Chen-006 (see, e.g., Figs. 6A-6B) teaches that the transition zone (e.g., middle region 154) comprises a plurality of sub zones (e.g., see Par. [0048]: middle region 154 can further include a first middle region 1541 to an (n)th middle region 154n, and the (n)th middle region 154n surrounds the (n−1) middle region 154(n−1)), and wherein first ones of the plurality of sub zones that are closer to the passive device zone (e.g., central region 150) have lower pattern densities than respective second ones of the plurality of sub zones that are closer to the functional circuit zone (e.g., edge region 152) (e.g., Par. [0048]: bonding pads in the (n)th middle region 154n include a width greater than the bonding pads in the (n−1)th middle region 154(n−1)).
26. Regarding Claim 16, Chen-192 (see, e.g., Figs. 3-4) shows that the passive device comprises an inductor (e.g., inductor 600).
27. Regarding Claim 17, Chen-006 (see, e.g., Fig. 5 and Pars. [0025] and [0044]) teaches that the structure further comprises a package component (e.g., semiconductor structure 100a) bonding to the device die (e.g., semiconductor structure 200a), wherein the first plurality of bond pads, the second plurality of bond pads, and the third plurality of bond pads (e.g., fourth bonding pads 220 and third bonding pads 210) are in physical contact with, and are joined to, the package component.
28. Regarding Claim 18, Chen-192 (see, e.g., Figs. 1A-1K, 2A-2B, and 3) shows most aspects of the instant invention including a structure comprising:
- a semiconductor substrate (e.g., semiconductor substrate 110)
- a plurality of metal layers (e.g., conductive patterns 134) over the semiconductor substrate
- an inductor (e.g., inductor 600) over the plurality of metal layers
- a first plurality of bond pads (e.g., dummy bonding pads 176), wherein a first chip area (e.g., second region R2) occupied by the first plurality of bond pads overlaps the inductor (e.g., Fig. 3), and the first plurality of bond pads have a first pitch (P176)
- a second plurality of bond pads (e.g., bonding pads 174) in a second chip area (e.g., first region R1) encircling the first plurality of bond pads, wherein the second plurality of bond pads have a second pitch (P174) smaller than the first pitch (see, e.g., Fig. 2A and Par. [0023]: the pitch P176 between two adjacent dummy bonding pads 176 is greater than the pitch P174 between two adjacent bonding pads 174)
29. However, Chen-192 is silent about a third plurality of bond pads in a third chip area encircling the second plurality of bond pads, wherein the third plurality of bond pads have a third pitch smaller than the second pitch. Chen-006 (see, e.g., Figs. 6A-6B and Pars. [0025], [0049], and [0073]) on the other hand and in the same field of endeavor, teaches a semiconductor package featuring a gradual decrease in pattern density for bonding pads (e.g., first, fifth, and second bonding pads 110, 130, and 120) from a central zone to an outer zone encircling it using a transition zone (e.g., middle region 154) to mitigate the effects of misalignment of bonding pads in the outer zone that can arise when stacking dies by enabling partial contact between the bonding pads of both dies through a gradual increase in bonding pad size, ensuring electrical connection and improving the performance and reliability of the semiconductor package.
30. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a third plurality of bond pads in a third chip area encircling the second plurality of bond pads, wherein the third plurality of bond pads have a third pitch smaller than the second pitch, in the structure of Chen-192, as taught by Chen-006, to mitigate the effects of bonding pad misalignment and improve the performance and reliability of the semiconductor package.
31. Regarding Claim 19, Chen-006 (see, e.g., Figs. 6A-6B) teaches that the first plurality of bond pads (e.g., first bonding pads 110) have a first pattern density, and wherein the second plurality of bond pads (e.g., fifth bonding pads 130) have a second pattern density greater than the first pattern density, and the third plurality of bond pads (e.g., second bonding pads 120) have a third pattern density greater than the second pattern density.
32. Regarding Claim 20, Chen-006 (see, e.g., Figs. 6A-6B) teaches that the first plurality of bond pads (e.g., diameter of first bonding pads 110) have a first lateral dimension, and wherein the second plurality of bond pads (e.g., diameter of fifth bonding pads 130) have a second lateral dimension greater than the first lateral dimension, and the third plurality of bond pads (e.g., diameter of second bonding pads 120) have a third lateral dimension greater than the second lateral dimension.
33. Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US2021/0066192, hereinafter Chen-192) in view of Chen et al. (US2019/0123006, hereinafter Chen-006) and in further view of Park et al. (US2022/0077116).
34. Regarding Claim 4, Chen-192 in view of Chen-006 is silent about the third plurality of bond pads being dummy pads. Park (see, e.g., Figs. 3 and 7-8 and Pars. [0057]-[0058]), on the other hand and in the same field of endeavor, teaches a semiconductor package featuring variable pattern density for bonding pads using a plurality of transition zones where the third plurality of bond pads are dummy pads (e.g., semiconductor lower dummy pads 255D) installed to assist subsequent planarization processes by mitigating unequal removal rates of different materials and improve bonding operations.
35. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the third plurality of bond pads be dummy pads in the structure of Chen-192 in view of Chen-006, as taught by Park, to assist subsequent planarization processes by mitigating unequal removal rates of different materials and improve bonding operations.
36. Regarding Claim 13, Chen-192 in view of Chen-006 is silent about the third plurality of bond pads being electrically floating. Park (see, e.g., Figs. 3 and 7-8 and Pars. [0057]-[0058]), on the other hand and in the same field of endeavor, teaches a semiconductor package featuring variable pattern density for bonding pads using a plurality of transition zones where the third plurality of bond pads are dummy pads (e.g., semiconductor lower dummy pads 255D) installed to assist subsequent planarization processes by mitigating unequal removal rates of different materials and improve bonding operations.
37. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the third plurality of bond pads being electrically floating in the structure of Chen-192 in view of Chen-006, as taught by Park, to assist subsequent planarization procedures by mitigating unequal removal rates of different materials and improve bonding operations.
38. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US2021/0066192, hereinafter Chen-192) in view of Chen et al. (US2019/0123006, hereinafter Chen-006) and in further view of Basavanhally et al. (Optoelectronic Packaging: Solder Assembly, Encyclopedia of Materials: Science and Technology, 2001, Elsevier, pg. 6482-6485).
39. Regarding Claim 9, Chen-192 (see, e.g., Fig. 1C and Pars. [0017]-[0018]) teaches that the forming the first plurality of bond pads and the forming the second plurality of bond pads (e.g., bonding pads 174 and dummy bonding pads 176) comprise: forming a dielectric layer (e.g., dielectric layer 172); removing portions of the dielectric layer to form a plurality of openings (Par. [0018]: trenches are formed in the dielectric layer 172 by removing portions of these layers); and filling a conductive material in the plurality of openings (Par. [0018]: conductive material fills into the trenches to form the bonding pads 174 and the dummy bonding pads 176). However, Chen-192 is silent about both the use of etching in the step removing portions of the dielectric layer to form a plurality of openings and the step of performing a planarization process to level top surfaces of the dielectric layer and the conductive material, wherein remaining portions of the conductive material comprise the first plurality of bond pads and the second plurality of bond pads. Chen-006 (see, e.g., Fig. 18 and Par. [0072]), on the other hand and in the same field of endeavor, teaches that bonding pads are formed through a similar process followed by a planarization operation to remove superfluous conductive material, a well-known procedure in semiconductor fabrication, and to prepare the die for stacking. Additionally, Basavanhally (see, e.g., pg. 6482), on the other hand and in the same field of endeavor, teaches that etching is a common fabrication technique for constructing bonding pads with high precision.
40. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to etch in the step removing portions of the dielectric layer to form a plurality of openings and to perform a planarization process to level top surfaces of the dielectric layer and the conductive material, wherein remaining portions of the conductive material comprise the first plurality of bond pads and the second plurality of bond pads, in the structure of Chen-192, as taught by Chen-006 and Basavanhally, to precisely fabricate bonding pads ready for die stacking.
Allowable Subject Matter
41. Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
42. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. The additional references cited disclose semiconductor structures having arrangements of bonding pads similar to the instant inventions.
43. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rianna B. Greer whose telephone number is (571) 272-7985. The examiner can normally be reached Monday - Friday, 8 AM - 6 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.B.G./Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814