Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Group I and Species IB in the reply filed on 1 June 2026 is acknowledged.
Claims 3, 17 and 21-25 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention or Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1 June 2026.
Drawing Objections
The drawings are objected to because in Fig. 5 circuit unit 30a does not show the N+ marking adjacent to the DL. Additionally, neither 300a nor 300b are marked with an N+ near the storage circuit 212. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 6 objected to because of the following informalities:
Claim 6 recites “The device of claim 4, wherein: each of the circuit layers includes a maximum number of circuit units; and the device includes half the maximum number of vertical body contacts.”
The term maximum is undefined. Paragraph 84 specification shows that the WL structure can extend laterally across a row of n number of semiconductor bodies that represent an n number of storage circuits that together store a data word.
Because there is one storage circuit per circuit unit (see paras. 84-86 of the application), claim 6 is interpreted to read “The device of claim 4, wherein: each of the circuit layers includes a maximum number n of circuit units; and the device includes half the maximum number n of vertical body contacts.”
Appropriate correction is required.
Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 10 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US 20210183862), hereinafter referred to as Son, and Lee et al. (US Pub. 20190164985), hereinafter referred to as Lee.
Regarding claim 1, Son teaches A three-dimensionally integrated semiconductor memory device, comprising: vertically stacked circuit layers (Son, L1-L3, Fig. 4, para. 36) that each include at least one circuit unit, wherein each circuit unit includes (1) a storage circuit configured to store one or more bits of data (Son, DS, Fig. 4, para. 40) and (2) an access circuit (Son, SP, Fig. 4, para. 37) configured to provide access to and/or from the storage circuit, the access circuit having a semiconductor body (Son, CH, Fig. 4, Fig. 38), and wherein the access circuit across the layers are aligned along a vertical direction (Son, D3, Fig. 4).
Son does not teach a vertical body contact extending vertically and connected to the semiconductor body of the at least one access circuit aligned across the two or more layers,
wherein the vertical body contact is configured to provide a transistor body contact for multiple access circuits located on different layers.
However, Lee teaches a common source line (Lee, CLS, Fig. 2, para. 42) which extends both laterally (Lee, D1, Fig. 2) and vertically (Lee, D3, Fig. 2) and connects to all the semiconductor patterns of the device (Lee, SP, Fig. 2, para. 35).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the semiconductor device of Son with the common source line of Lee to avoid the memory cells from having floating bodies (Lee, para. 56).
Regarding claim 2, modified Son teaches the device of claim 1, wherein the access circuit includes: the semiconductor body (Son, SP, Fig. 4, para. 37) having a length and coupled to the storage circuit (Son, DS, Fig. 4, para. 33) at one end of the length; a word-line (Son, WL, Fig. 4, para. 32) structure facing and coupled to at least one side of the semiconductor body; a digit-line (Son, BL Fig. 4, para. 31) connected to the semiconductor body at a first location across the WL structure from the storage circuit; and the vertical body contact (Lee, CLS, Fig. 2, para. 42) connected to the semiconductor body at a second location across the WL structure from the storage circuit.
Regarding claim 10, modified Son teaches the device of claim 2, wherein: each layer (Son, L1-L3, Fig. 4, paras. 36, 41)includes a set of circuit units arranged along a lateral direction, the set of circuit units including an n number of storage circuits configured to store a set of bits that correspond to a stored data word (Son, paras. 36, 41); the WL structure extends across the set of circuit units along the lateral direction and is configured to simultaneously control an n number of access circuits in the set of circuit units (Son, paras 33-41); and the DL (CL, Fig. 4, paras 30-33) comprises an n number of DLs that (1) extend vertically across the layers and (2) each couples to an instance of the storage circuit corresponding to a unique bit position in the set of bits on each of the layers.
Regarding claim 16, Son teaches a three-dimensionally integrated semiconductor device, comprising: vertically stacked circuit layers (Son, L1-L3, Fig. 4, paras. 36-38) that each includes at least one transistor, wherein each of the at least one transistor includes a first terminal (Son, SD2, Fig. 4, para. 38), a second terminal (Son, SD1, Fig. 4, para. 38) and a gate terminal (Son, GE, par. 51) connected to or integral with a semiconductor body (Son, CJ, Fig. 4, para. 38), the first and second terminals functioning as endpoints of a current channel (Son, para. 38), and wherein the at least one transistor on each of the layers are aligned along a vertical direction (Son, D3, Fig. 4).
Son does not teach a vertical body contact extending vertically across the layers and connected to the semiconductor body of the at least one transistor on each of the layers, wherein the vertical body contact is configured to provide a transistor body contact for the transistors located on different layers.
However, Lee teaches a common source line (Lee, CLS, Fig. 2, para. 42) which extends both laterally (Lee, D1, Fig. 2) and vertically (Lee, D3, Fig. 2) and connects to all the semiconductor patterns of the device (Lee, SP, Fig. 2, para. 35).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to one having ordinary skill in the art to combine the semiconductor device of Son with the common source line of Lee to avoid the memory cells from having floating bodies (Lee, para. 56).
Claims 4, 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Son and Lee as applied to claim 2 above, and further in view of Sung (US Pub. 20120153365), hereinafter referred to as Sung
Regarding claim 4, modified Son teaches the device of claim 2 wherein: the first location for the DL (Son, Son, BL Fig. 4, para. 31) contact is at an opposite end of the length, but does not teach and the second location for the vertical body contact is on a portion of a sidewall of the semiconductor body and between the first location and the WL structure.
However, Sung teaches a semiconductor device wherein the vertical body contact (Sung, 160a, para. 20) is coupled to the semiconductor body (Sung, 105a, 105b, Fig. 1) through the upper substrate (Sung, 1000a1, 100a2, Fig. 1, para. 20 ). The upper substrate provides this connection between the word lines (Sung, 240a, 240b, para. 22) and the bit line (Sung, 120a, 120b, Fig. 1, para. 18)
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Son and Lee with the connection placement of Sung in order to provide a fixed voltage level via the body contact (Sung, para. 20).
Regarding claim 7, modified Son teaches the device of claim 2, wherein: the access circuit comprises a transistor formed on or integral with the semiconductor body (Son, paras. 30, 33, 38), the storage circuit (Son, DS, Fig. 4, paras. 33, 38) is a capacitor connected to a first end terminal of the transistor (Son, SD2, Fig. 4, paras. 33, 38); the WL structure corresponds to a gate terminal of the transistor (Son, para. 51); the DL (Son, BL, Fig. 4, para. 43) corresponds to a second end terminal (Son, SD1, Fig. 4, para. 43) of the transistor.
Modified Son does not teach and the vertical body contact corresponds to the transistor body contact configured to route leakage current away from the capacitor when the transistor is off.
However, Sung teaches that the body contact may be grounded or fixed at any voltage level (Son, para. 20).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Son and Lee with the connection placement of Sung in order to provide a fixed voltage level or grounding path via the body contact (Sung, para. 20).
Regarding claim 8, modified Son teaches the device of claim 7, wherein the WL (Son, WL, Fig. 4, para. 51) structure encircles the semiconductor body along a portion of the length for a gate-all-around (GAA) transistor structure.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Son and Lee as applied to claim 6 above, and further in view of Sung.
Regarding claim 18, modified Son teaches the device of claim 16, wherein: the first terminal includes a first end portion of the semiconductor body (Son, SD2, Fig. 4, para. 38);
the second terminal includes a second end portion of the semiconductor body opposite the first end portion (Son, SD1, Fig. 4, para. 38);
the gate terminal (Son, GE, Fig. 4, para. 51) includes a structure facing a section of at least one surface of the semiconductor body between the first and second end portions.
Neither Son nor Lee teach the vertical body contact is connected to a portion of the semiconductor body between the gate terminal and the second terminal.
However, Sung teaches a semiconductor device wherein the vertical body contact (Sung, 160a, para. 20) is coupled to the semiconductor body (Sung, 105a, 105b, Fig. 1) through the upper substrate (Sung, 1000a1, 100a2, Fig. 1, para. 20 ). The upper substrate provides this connection between the word lines (Sung, 240a, 240b, para. 22) and the bit line (Sung, 120a, 120b, Fig. 1, para. 18)
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Son and Lee with the connection placement of Sung in order to provide a fixed voltage level via the body contact (Sung, para. 20).
Claim(s) 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Son, Lee, and Sung as applied to claim 4 above, and further in view of Cheng et. al. (US Pub. 20070045698), hereinafter referred to as Cheng.
Regarding claim 5, modified Son teaches the device of claim 4, but does not teach wherein: the at least one circuit unit on each of the layers includes at least two circuit units positioned adjacent to each other; and the vertical body contact is a shared body contact that is (1) located between the two circuit units and (2) connected to mirroring portions of sidewalls on semiconductor bodies of the at least two circuit units.
However, Cheng teaches a memory device wherein the body contact (Cheng, 54, Fig. 13, para. 37) is connected to the gate structure (Cheng, 40, Fig. 13, para. 32) of two memory cells (Cheng, 12, Fig, 13, para. 32, see diagram below), through mirrored SOI bodies (Cheng, 16 18, Fig. 12, para. 24, 26).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the device of Son, Lee and Sung with the shared body contact of Cheng in order to prevent the floating body effect caused by leakage in a parasitic bipolar transistor thereby preventing the discharge of the storage capacitor (Cheng, para. 10, 69).
Regarding claim 6, modified Son teaches the device of claim 4, wherein: each of the circuit layers includes a maximum number n of circuit units; and the device includes half the maximum number n of vertical body contacts.
Cheng teaches (Cheng, Fig. 13) that each body contact (Cheng, 54, Fig. 13) is shared between two memory cells (Cheng, 12, Fig. 13, see diagram below). Combining that shared configuration with the vertically extending vertical body contact of Lee (Lee, CSL, Fig. 2), and the placement of Sung (Sung 160a, 160b, Fig. 1) teaches a plurality of body contact, extending vertically and where they are shared between two memory cells per level.
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Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Son and Lee as applied to claim 1 above, and further in view of Cheng.
Regarding claim 12, modified Son teaches the device of claim 1, further comprising: a semiconductor substrate (Son, SUB, Fig. 4, para. 35), wherein the vertically stacked circuit layers are stacked over the semiconductor substrate (Son, Fig. 4).
Modified Son does not teach the substrate includes a conductive top surface and wherein the conductive top surface is electrically coupled to the vertical body contact and is configured to laterally route electrical signals to or from the vertical body contact.
However, Cheng teaches a semiconductor substrate (Cheng, 14, Fig. 13, para. 24) including a conductive top surface (Cheng, 25, Fig. 13, para. 24), and wherein the conductive top surface is electrically coupled to the vertical body contact and is configured to laterally route electrical signals to or from the vertical body contact (Cheng, para. 40).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the device of Son, and Lee with the doped substrate of Cheng in order to provide a leaky current path thereby reducing parasitic capacitance and thereby preventing the discharge of the storage capacitor (Cheng, para. 10, 40, 69).
Regarding claim 14, modified Son teaches the device of claim 12, wherein the conductive top surface includes a P+ doped P-well on a top portion of the semiconductor substrate (Cheng, 25, para. 24).
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Son and Lee as applied to claim 16 above, and further in view of Cheng.
Regarding claim 19, modified Son teaches the device of claim 16, wherein: at least one of the layers (Son, L1-L3, Fig. 4) includes two or more transistors arranged laterally adjacent to each other (Son, para. 36).
Modified Son does not teach the vertical body contact is located between and connected to the two laterally adjacent transistors for providing a shared body contact for the two adjacent transistors in addition to the transistors aligned along the vertical direction.
However, Cheng teaches a memory device wherein the body contact (Cheng, 54, Fig. 13, para. 37) is connected to the gate structure (Cheng, 40, Fig. 13, para. 32) of two memory cells (Cheng, 12, Fig, 12, para. 32, see diagram below), through mirrored SOI bodies (Cheng, 16, 18, Fig. 12, para.24, 26).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the device of Son, Lee and Sung with the shared body contact of Cheng in order to prevent the floating body effect caused by leakage in a parasitic bipolar transistor thereby preventing the discharge of the storage capacitor (Cheng, para. 10, 69).
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Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Son, Lee and Cheng as applied to claim 12 above, and further in view of Paul (US Pub 20200027908), hereinafter referred to as Paul.
Regarding claim 13, modified Son teaches the device of claim 12, but does not teach further comprising: vertical metal connection electrically coupled to the conductive top surface at a location laterally displaced from the vertical body contact, herein the vertical metal connection is configured to electrically couple the vertical body contact to an external electrical connection.
However, Paul teaches connecting a body contact to a body through an extension of the semiconductor to a bias node, and states that connecting the body contact to a circuit ground or a source is a known technique (Paul, para. 8)
Therefore it would have been obvious to one having ordinary skill in the art to have connected the device of modified Son to an external connection (Paul, para. 8) to provide a ground or external power supply.
Claim 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son and Lee as applied to claim 1 above, and further in view of Cheng.
Regarding claim 15, modified Son teaches the device of claim 1, further comprising: a dielectric film (Lee, OM, Fig. 16A, para. 75) disposed between the semiconductor body and the vertical body contact, wherein the dielectric film has a thickness configured to (1) enable conduction of electrical charges or holes.
Lee is silent regarding the film inhibiting dopant diffusion between the semiconductor body and the vertical body contact.
However, Cheng teaches a buried oxide layer (Cheng, 18, Fig. 12, para. 24) which is placed in the current path between the semiconductor body (Cheng, 16, Fig. 12, para. 24) and the body contact (Cheng, 54, Fig. 12, para. 24) which significantly reduces the leakage current arising from diffusion of charge carriers.
Therefore it would have been obvious to one of ordinary skill in the art before the time of the invention to use the oxide material of Lee to provide the diffusion reduction of Cheng to minimize junction length and increase data retention times (Cheng para. 7).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Son and Lee as applied to claim 2 above, and further in view of Pulugurtha et al. (US Patent 11164872) hereinafter known as Pulugurtha.
Regarding claim 9, modified Son teaches the device of claim 2, wherein the semiconductor body is doped n+ type at the first location for the DL and at the one end of the length for the storage circuit (Son, para. 39).
Son does not teach that the semiconductor body is doped p+ type at the second location for the vertical body contact.
However, Pulugurtha teaches a memory array, with a vertical body contact (Pulugurtha, 295, Fig. 2, Col. 6, lines 52-63), wherein the portions of the access device (Pulugurtha, 221, 223 , Fig. 2, Col. 4, lines 58-62) are n+ doped. Pulugurtha also teaches that the region (Pulugurtha 989, Fig. 9, Col 27, lines 49-60) in contact with the vertical body contact is P+ doped.
Therefore it would have been obvious to one having ordinary skill in the art to have combined the teachings of Son and Lee with the doping of Pulugurtha to lower digit line contact resistance and lower source/drain doping requirements (Pulugurtha, Col. 2, lines 48-56)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Son and Lee as applied to claim 2 above, and further in view of Pulugurtha.
Regarding claim 11, modified Son teaches the device of claim 1, but does not teach wherein portions of the semiconductor body connected to the storage circuit and the vertical body contact are doped with complementary dopant types.
However, Son does teach wherein the semiconductor body is doped n+ type at the first location for the DL and at the one end of the length for the storage circuit (Son, para. 39).
Additionally, Pulugurtha teaches a memory array, with a vertical body contact (Pulugurtha, 295, Fig. 2, Col. 6, lines 52-63), wherein the portions of the access device (Pulugurtha, 221, 223 , Fig. 2, Col. 4, lines 58-62) are n+ doped. Pulugurtha also teaches that the region (Pulugurtha 989, Fig. 9, Col 27, lines 49-60) in contact with the vertical body contact is P+ doped.
Therefore it would have been obvious to one having ordinary skill in the art to have combined the teachings of Son and Lee with the doping of Pulugurtha to lower digit line contact resistance and lower source/drain doping requirements (Pulugurtha, Col. 2, lines 48-56)
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Son and Lee as applied to claim 2 above, and further in view of Cheng.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Son and Lee as applied to claim 16 above, and further in view of Pulugurtha.
Regarding claim 20, modified Son teaches the device of claim 2, wherein the semiconductor body is doped with (1) a first dopant type at the first and second terminals and (Son, para. 39).
Son does not teach that the semiconductor body is doped with a second dopant type at a location contacting the vertical body contact.
However, Pulugurtha teaches a memory array, with a vertical body contact (Pulugurtha, 295, Fig. 2, Col. 6, lines 52-63), wherein the portions of the access device (Pulugurtha, 221, 223 , Fig. 2, Col. 4, lines 58-62) are n+ doped. Pulugurtha also teaches that the region (Pulugurtha 989, Fig. 9, Col 27, lines 49-60) in contact with the vertical body contact is P+ doped.
Therefore it would have been obvious to one having ordinary skill in the art to have combined the teachings of Son and Lee with the doping of Pulugurtha to lower digit line contact resistance and lower source/drain doping requirements (Pulugurtha, Col. 2, lines 48-56)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choe et al. (US Pub 20230107911) teaches a memory device using a gate all around FET.
Yang et al. (US Pub 20230134556) teaches a memory device with a body contact that is connected to an external ground.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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