Prosecution Insights
Last updated: July 17, 2026
Application No. 18/403,162

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Jan 03, 2024
Priority
Jan 31, 2023 — JP 2023-013048 +2 more
Examiner
ZHU, SHENG-BAI
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
3m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
444 granted / 714 resolved
-5.8% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
64 currently pending
Career history
780
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
95.1%
+55.1% vs TC avg
§102
3.0%
-37.0% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 714 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Detailed Action Restriction/Election Applicant’s election, without traverse, of Claims 1-11 is acknowledged. Specification Objection The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections – 35 U.S.C. 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim 1 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shue (U.S. Patent Pub. No. 2013/0320459). Regarding Claim 1 FIG. 7 of Shue discloses a semiconductor device comprising: a semiconductor chip that has a first principal surface and a second principal surface; and an element isolation portion that is formed on the side of the first principal surface of the semiconductor chip and that demarcates an active region (28), the element isolation portion comprising: a trench (148) formed on the side of the first principal surface of the semiconductor chip; a first insulating film (150) formed on a side surface of the trench; a second insulating film (138/238) formed inside the trench such that an air gap (154) is sandwiched between the first insulating film and the second insulating film; and a buried conductor (136/236) that is covered by the second insulating film and that is connected to the semiconductor chip at a bottom portion of the trench. Claim Rejections – 35 U.S.C. 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 6, 8 and 10 rejected under 35 U.S.C. 103 as being unpatentable over Otsubo (U.S. Patent Pub. No. 2020/0403072), in view of Lee (U.S. Patent Pub. No. 2018/0166553) Regarding Claim 1 FIG. 2 of Otsubo discloses a semiconductor device comprising: a semiconductor chip that has a first principal surface and a second principal surface; and an element isolation portion (8) that is formed on the side of the first principal surface of the semiconductor chip and that demarcates an active region (2), the element isolation portion comprising: a trench formed on the side of the first principal surface of the semiconductor chip; a first insulating film (53, FIG. 3) formed on a side surface of the trench; a second insulating film (55) formed inside the trench; and a buried conductor (59) that is covered by the second insulating film and that is connected to the semiconductor chip at a bottom portion of the trench. Otsubo is silent with respect to “an air gap is sandwiched between the first insulating film and the second insulating film”. FIG. 9 of Lee discloses a similar trench formed on the side of the first principal surface of the semiconductor chip; a first insulating film (214) formed on a side surface of the trench; a second insulating film (220) formed inside the trench such that an air gap (350) is sandwiched between the first insulating film and the second insulating film; and a buried conductor (232) that is covered by the second insulating film and that is connected to the semiconductor chip at a bottom portion of the trench. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Otsubo, as taught by Lee. The ordinary artisan would have been motivated to modify Otsubo in the above manner for purpose of reducing stray capacitance ([0028] of Lee). Regarding Claim 6 FIG. 2 of Otsubo discloses the semiconductor chip includes a first-conductivity-type (p) first impurity region that is formed on the side of the second principal surface and to which the buried conductor is connected at the bottom portion of the trench, a second-conductivity-type (n) second impurity region formed on the side of the first principal surface, and a second-conductivity-type buried region (41) that is buried between the first impurity region and the second impurity region [0057]. FIG. 9 of Lee discloses the air gap is sandwiched between the buried region and the buried conductor in a lateral direction along the first principal surface. Regarding Claim 8 FIG. 9 of Lee discloses the first insulating film (214) is formed on both the side surface on one side of the trench and the side surface on one other side of the trench, and the air gap (250) is formed both between the buried conductor (232) and the side surface on the one side of the trench and between the buried conductor and the side surface on the one other side of the trench. Regarding Claim 10 FIG. 9 of Lee discloses the buried conductor (232) includes a protruding portion that protrudes toward the side of the second principal surface than the second insulating film (214), and the air gap (250) is located closer to the side of the first principal surface than a bottom wall of the protruding portion with regard to a depth direction of the trench. Claims 2-4 rejected under 35 U.S.C. 103 as being unpatentable over Otsubo and Lee in view of Shinohara (U.S. Patent Pub. No. 2017/0301669) Regarding Claim 2 Otsubo as modified by Lee discloses Claim 1. Otsubo as modified by Lee is silent with respect to “the side surface of the trench is formed in a shape in which a halfway portion in a depth direction of the trench is convex more outwardly from the trench than an open end of the trench in a cross-sectional view”. FIG. 11 of Shinohara discloses a similar trench, wherein the side surface of the trench (TP) is formed in a shape in which a halfway portion in a depth direction of the trench is convex more outwardly from the trench than an open end of the trench in a cross-sectional view. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Otsubo, as taught by Shinohara. The ordinary artisan would have been motivated to modify Otsubo in the above manner for purpose of improving performance ([0015] of Shinohara). Regarding Claim 3 FIG. 11 of Shinohara discloses the side surface of the trench is formed in a tapered shape whose width becomes smaller from the bottom portion of the trench toward the first principal surface in a cross-sectional view. Regarding Claim 4 FIG. 11 of Shinohara discloses the side surface of the trench is formed in an arched shape that is convex outwardly from the trench in a cross-sectional view. Claims 1, 5 and 11 rejected under 35 U.S.C. 103 as being unpatentable over Otsubo (U.S. Patent Pub. No. 2020/0403072), in view of Harame (U.S. Patent Pub. No. 2014/0284758) Regarding Claim 1 FIG. 2 of Otsubo discloses a semiconductor device comprising: a semiconductor chip that has a first principal surface and a second principal surface; and an element isolation portion (8) that is formed on the side of the first principal surface of the semiconductor chip and that demarcates an active region (2), the element isolation portion comprising: a trench formed on the side of the first principal surface of the semiconductor chip; a first insulating film (53) formed on a side surface of the trench; a second insulating film (55) formed inside the trench; and a buried conductor (59) that is covered by the second insulating film and that is connected to the semiconductor chip at a bottom portion of the trench. Otsubo is silent with respect to “an air gap is sandwiched between the first insulating film and the second insulating film”. FIG. 5 of Harame discloses a similar element isolation portion (48/50) comprising a first insulating film (outer portion of the filler [0033]) formed on a side surface of the trench; a second insulating film (inner portion of the filler) formed inside the trench such that an air gap (49/51) is sandwiched between the first insulating film and the second insulating film; and a buried conductor (23) that is covered by the second insulating film and that is connected to the semiconductor chip at a bottom portion of the trench. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Otsubo, as taught by Harame. The ordinary artisan would have been motivated to modify Otsubo in the above manner for purpose of enhancing the device performance ([0004] of Harame). Regarding Claim 5 FIG. 5 of Harame discloses the buried conductor (23) has a tapered sidewall whose width becomes larger from a bottom wall of the buried conductor toward the first principal surface in a cross-sectional view, and the second insulating film is contiguous to the sidewall of the buried conductor. Regarding Claim 11 FIG. 5 of Harame discloses the bottom wall of the buried conductor (23) is located closer to the side of the first principal surface than a lower end of the second insulating film and than a lower end of the air gap with regard to a depth direction of the trench. Claim 5 rejected under 35 U.S.C. 103 as being unpatentable over Otsubo and Lee in view of Schurz (CN 103578927, machine-translation provided). Regarding Claim 5 Otsubo as modified by Lee discloses Claim 1. Otsubo as modified by Lee is silent with respect to “the buried conductor has a tapered sidewall whose width becomes larger from a bottom wall of the buried conductor toward the first principal surface in a cross-sectional view, and the second insulating film is contiguous to the sidewall of the buried conductor”. FIG. 4 of Schurz discloses a similar trench, wherein the buried conductor (190) has a tapered sidewall whose width becomes larger from a bottom wall of the buried conductor toward the first principal surface in a cross-sectional view, and the second insulating film is contiguous to the sidewall of the buried conductor. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Otsubo, as taught by Schurz. The ordinary artisan would have been motivated to modify Otsubo in the above manner for purpose of improving performance ([0015] of Schurz). Claim 7 rejected under 35 U.S.C. 103 as being unpatentable over Otsubo and Lee in view of Yeh (U.S. Patent Pub. No. 2021/0028054). Regarding Claim 7 Otsubo as modified by Lee discloses Claim 6. Otsubo as modified by Lee is silent with respect to “the side surface of the trench is formed in an arched shape that is convex outwardly from the trench in a cross-sectional view, and a top portion of the side surface having the arched shape is sandwiched between the buried region and the buried conductor”. FIG. 8 of Yeh discloses a similar trench, wherein the side surface of the trench is formed in an arched shape that is convex outwardly from the trench in a cross-sectional view, thus, Otsubo as modified by Lee and Yeh discloses a top portion of the side surface having the arched shape is sandwiched between the buried region and the buried conductor. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Otsubo, as taught by Yeh. The ordinary artisan would have been motivated to modify Otsubo in the above manner for purpose of improving manufacturing process ([0003] of Yeh). Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Otsubo and Lee in view of Tokumitsu (U.S. Patent Pub. No. 2017/0287912). Regarding Claim 9 Otsubo as modified by Lee discloses Claim 1. Otsubo as modified by Lee is silent with respect to “the first insulating film and the second insulating film are connected in an upper portion of the trench, and are not connected in a halfway portion in a depth direction of the trench”. FIG. 3 of Tokumitsu discloses a similar trench, wherein the first insulating film (ILF) and the second insulating film (SSF) are connected in an upper portion of the trench, and are not connected in a halfway portion in a depth direction of the trench. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Otsubo, as taught by Tokumitsu. The ordinary artisan would have been motivated to modify Otsubo in the above manner for purpose of suppressing leak current ([0009] of Tokumitsu). Pertinent Art U.S. Patent Pub. No. 2018/0151410, 20140231877, 20130032871, 20150340273, 20160064475, 20230369462, 20160204143, 20180083128, 20240304682, 20240297071, 20070037341, 9368608, WO 2024171905, DE 102016119799. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jan 03, 2024
Application Filed
May 21, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
68%
With Interview (+6.0%)
2y 9m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 714 resolved cases by this examiner. Grant probability derived from career allowance rate.

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