DETAILED ACTION
This Notice is responsive to communication filed on 05/04/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 05/04/2026 has been acknowledged and entered into the record. Claims 4, 7, 8, 14, 17, and 18 have been cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claims 1-3, 6, 9-13, 16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Le et al. (US 20240313069), and further in view of Bisi et al. (US 20230299190) and Torabi et al. (US 20210202729).
Regarding claim 1, Le teaches a dual gate high electron mobility transistor (HEMT), comprising:
a substrate Fig. 12: 20;
a channel layer Fig. 12: 30 above the substrate Fig. 12: 20;
a source electrode Fig. 12: S electrically coupled to the channel layer Fig. 12: 30 and above the channel layer Fig. 12: 30;
a drain electrode Fig. 12: D electrically coupled to the channel layer Fig. 12: 30 and above the channel layer Fig. 12: 30;
a first gate electrode Fig. 12: G1 electrically coupled to the channel layer Fig. 12: 30 and above the channel layer Fig. 12: 30; and
a second gate electrode Fig. 12: G2 electrically coupled to the channel layer Fig. 12: 30 and above the channel layer Fig. 12: 30 wherein the first gate electrode Fig. 12: G1 is located between the source electrode Fig. 12: S and the drain electrode Fig. 12: D,
wherein the second gate electrode Fig. 12: G2 is located between the source electrode Fig. 12: S and the first gate electrode Fig. 12: G1,
wherein the second gate electrode Fig. 12: G2 is biased with a DC voltage (para. 0146, “fixed voltage signal”);
wherein a linearity of the dual gate HEMT Fig. 12 is related to a voltage value that the DC voltage has (para. 0146, “output characteristic curve”);
wherein a distance between the first gate electrode Fig. 12: G1 and the second gate electrode Fig. 12: G2 is in a range of about 0.25 micrometers (para. 0014, i.e. 0.5µm-2.7µm; a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985)) See MPEP 2144.05;
wherein the channel layer comprises: a doped GaN layer doped with iron or carbon; and
a unintentionally doped (UID) GaN layer disposed directly on the doped GaN layer and having a two-dimensional electron gas (2DEG) channel therein.
Bisi discloses the following claim limitations not disclosed by Le:
wherein the channel layer comprises a doped GaN layer Fig. 2: 11 doped with iron or carbon (para. 0033-para. 0034 “impurities such as carbon dopants ”); and
a unintentionally doped (UID) GaN layer Fig. 2: 15 (para. 0033, “UID”) disposed on the doped GaN layer Fig. 2: 11 and having a two-dimensional electron gas (2DEG) Fig. 2: 19 channel therein (para. 0033).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Le with the teachings of Bisi in order to add impurities such as carbon dopants to reduce mobile carriers/electrons, and to pin/stabilize Fermi-level within the band-gap sufficiently distant from both valence-band and conduction-band (para. 0034).
Torabi discloses the following claim limitations not disclosed by Le:
a unintentionally doped (UID) layer Fig. 2: UID GaN Channel disposed directly on the doped GaN layer Fig. 2: Be&C Doped GaN and having a 2DEG channel therein (shown in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Le’s teachings with Torabi’s teachings in order to have a UID GaN layer disposed directly on the doped GaN layer as is normal practice in the art, to overcome the electrically active carriers without allowing the dopants in the buffer to act as high levels of active long lived traps, thus reducing the current collapse and keeping the off state leakages at low and manageable levels (para. 0023).
Regarding claim 2, Le teaches the dual gate HEMT of claim 1, wherein the DC voltage is fixed and positive (para. 0146 teaches fixed voltage of 2V).
Regarding claim 3, Le teaches the dual gate HEMT of claim 1, wherein the first gate electrode Fig. 12: G1 is a radio frequency (RF) gate for receiving a radio frequency (RF) signal (para. 0146 teaches radio frequency signal RF).
Regarding claim 6, Le teaches the dual gate HEMT of claim 1, wherein a linearity of the dual gate HEMT is related to a distance between the first gate electrode Fig. 12: G1 and the second gate electrode Fig. 12: G2 (para. 0014 teaches a relation to the distance between G1 and G2).
Regarding claim 9, Le teaches the dual gate HEMT of claim 1, further comprising: a barrier layer Fig. 12: 40 above the channel layer Fig. 12: 30 and below the first gate electrode Fig. 12: G1 and the second gate electrode Fig. 12: G2.
Regarding claim 10, Le teaches the dual gate HEMT of claim 9, further comprising: a passivation layer (annotated below) above the barrier layer Fig. 12: 40 and in contact with the barrier layer Fig. 12: 40, wherein the passivation layer has a first opening and a second opening (annotated below) to expose the barrier layer Fig. 12: 40, wherein the first opening and the second opening respectively accommodate the first gate electrode Fig. 12: G1 and the second gate electrode Fig. 12: G2.
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Regarding claim 11, Le teaches a method of manufacturing a dual gate high electron mobility transistor (HEMT), comprising:
providing a substrate Fig. 12: 20;
providing a channel layer Fig. 12: 30 above the substrate Fig. 12: 20;
providing a source electrode Fig. 12: S and a drain electrode Fig. 12: D respectively electrically coupled to the channel layer Fig. 12: 30 and respectively above the channel layer Fig. 12: 30; and
providing a first gate electrode Fig. 12: G1 and a second gate electrode Fig. 12: G2 respectively electrically coupled to the channel layer Fig. 12: 30 and respectively above the channel layer Fig. 12: 30;
wherein the first gate electrode Fig. 12: G1 is located between the source electrode Fig. 12: S and the drain electrode Fig. 12: D, wherein the second gate electrode Fig. 12: G2 is located between the source electrode Fig. 12: S and the first gate electrode Fig. 12: G1, wherein the second gate electrode Fig. 12: G2 is biased with a DC voltage (para. 0146, “fixed voltage signal”);
wherein a linearity of the dual gate HEMT Fig. 12 is related to a voltage value that the DC voltage has (para. 0146, “output characteristic curve”);
wherein a distance between the first gate electrode Fig. 12: G1 and the second gate electrode Fig. 12: G2 is in a range of about 0.25 micrometers (para. 0014, i.e. 0.5µm-2.7µm; a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985)) See MPEP 2144.05;
wherein the channel layer comprises: a doped GaN layer doped with iron or carbon; and
a unintentionally doped (UID) GaN layer disposed directly on the doped GaN layer and having a two-dimensional electron gas (2DEG) channel therein.
Bisi discloses the following claim limitations not disclosed by Le:
a doped GaN layer Fig. 2: 11 doped with iron or carbon (para. 0033-0034); and
an unintentionally doped (UID) GaN layer Fig. 2: 15 (para. 0033, “UID”) disposed on the doped GaN layer Fig. 2: 14 and having a two-dimensional electron gas (2DEG) Fig. 2: 19 channel therein (para. 0033).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Le with the teachings of Bisi in order to add impurities such as carbon dopants to reduce mobile carriers/electrons, and to pin/stabilize Fermi-level within the band-gap sufficiently distant from both valence-band and conduction-band (para. 0034).
Torabi discloses the following claim limitations not disclosed by Le:
a unintentionally doped (UID) layer Fig. 2: UID GaN Channel disposed directly on the doped GaN layer Fig. 2: Be&C Doped GaN and having a 2DEG channel therein (shown in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Le’s teachings with Torabi’s teachings in order to have a UID GaN layer disposed directly on the doped GaN layer as is normal practice in the art, to overcome the electrically active carriers without allowing the dopants in the buffer to act as high levels of active long lived traps, thus reducing the current collapse and keeping the off state leakages at low and manageable levels (para. 0023).
Regarding claim 12, Le teaches the method of manufacturing the dual gate HEMT of claim 11, wherein the DC voltage is fixed and positive (para. 0146 teaches fixed voltage of 2V).
Regarding claim 13, Le teaches the method of manufacturing the dual gate HEMT of claim 11, wherein the first gate electrode Fig. 12: G1 is a radio frequency (RF) gate for receiving a radio frequency (RF) signal (para. 0146 teaches radio frequency signal RF).
Regarding claim 16, Le teaches the method of manufacturing the dual gate HEMT of claim 11, wherein a linearity of the dual gate HEMT is related to a distance between the first gate electrode Fig. 12: G1 and the second gate electrode Fig. 12: G2 (para. 0014 teaches a relation to the distance between G1 and G2).
Regarding claim 19, Le teaches the method of manufacturing the dual gate HEMT of claim 11, further comprising: providing a barrier layer Fig. 12: 40 above the channel layer Fig. 12: 30 and below the first gate electrode Fig. 12: G1 and the second gate electrode Fig. 12: G2.
Regarding claim 20, Le teaches the method of manufacturing the dual gate HEMT of claim 19, further comprising: providing a passivation layer (annotated above) above the barrier layer Fig. 12: 40 and in contact with the barrier layer Fig. 12: 40, wherein the passivation layer has a first opening and a second opening (annotated above) to expose the barrier layer Fig. 12: 40, wherein the first opening and the second opening respectively accommodate the first gate electrode Fig. 12: G1 and the second gate electrode Fig. 12: G2.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Le et al. (US 20240313069), Bisi et al. (US 20230299190), and Torabi et al. (US 20210202729) as applied to claims 1 and 11 above, and further in view of Arnold et al. (US 20250386537).
Regarding claim 5, Arnold discloses the following claim limitations not disclosed by Le and Bisi:
the dual gate HEMT of claim 1,
wherein the DC voltage has a voltage value greater than 3 volts (para. 0009 teaches 8V and a range from 2V-8V, which includes the >3V range of claim 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Le and Arnold for the purpose of minimizing the on-state resistance of the device while ensuring a low leakage through the gate (para. 0009).
Regarding claim 15, Arnold discloses the following claim limitations not disclosed by Le and Bisi:
the method of manufacturing the dual gate HEMT of claim 11,
wherein the DC voltage has a voltage value greater than 3 volts (para. 0009 teaches 8V and a range from 2V-8V, which includes the >3V range of claim 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Le and Arnold for the purpose of minimizing the on-state resistance of the device while ensuring a low leakage through the gate (para. 0009).
Response to Arguments
Applicant's arguments filed 05/04/2026 have been fully considered but they are not persuasive.
Applicant argu Le contains no data, description, or suggestion regarding how the device behavior would change if the second gate voltage were varied. This argument is not persuasive. Le discloses the same physical structure as claimed where the second gate electrode Fig. 12: G2 is biased with a fixed DC voltage signal. A property or functional relationship that is not separately measured in the claim limitations is not required to be taught by the prior art of reference.
Applicant argues that the claimed distance, in the amended claim 1, of about 0.25 micrometers is significantly smaller than and does not fall within the range disclosed in Le. This argument is not persuasive. The claim language “of about” is being interpreted using the broadest reasonable interpretation, and 0.25 micrometers is about a quarter micrometer less than Le’s range. Further, case law (See MPEP 2144.05 Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985)) has been included in the claim rejection above.
Applicant argument regarding Bisi’s layer III-N GaN doped layer is not in direct contact with the III-N channel layer, based on the amended claim 1 including the included claim limitation “disposed directly on”, has been addressed in the claim rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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