Prosecution Insights
Last updated: October 02, 2026
Application No. 18/403,266

Memory Circuitry And Method Used In Forming Memory Circuitry

Non-Final OA §103§112
Filed
Jan 03, 2024
Priority
Feb 02, 2023 — provisional 63/442,852
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
3 (Non-Final)
62%
Grant Probability
Moderate
3-4
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
517 granted / 827 resolved
-5.5% vs TC avg
Strong +24% interview lift
Without
With
+24.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
48 currently pending
Career history
874
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
52.8%
+12.8% vs TC avg
§102
16.3%
-23.7% vs TC avg
§112
24.7%
-15.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 827 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112(b) Examiner withdraws the 35 USC § 112(b) based upon Applicant’s amendments to claim 13. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-10, 13, 21-28, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al. (US 2017/0278859 A1) (“Sharangpani”), with teaching reference Nakajima et al., "forming gate regions within the first tiers, the forming the gate regions comprising a forming high-k liner material and a conducive material, the high- k liner material being formed in direct physical contact with an insulative material of the second tiers", Applied Physics Letters, vol. 80, No. 7, Feb. 18, 2022 ("Nakajima") (see MPEP 2131.01), in view of Xie et al. (US 2019/0378761 A1) ("Xie"). Regarding claim 1, Sharangpani teaches at least in figure 1-7E: forming a stack comprising vertically-alternating first tiers (42/46) and second tiers (32), the first tiers being conductive (46) and the second tiers being insulative at least in a finished-circuitry construction (32); forming channel openings (49) through the first and second tiers (42/46); forming charge-storage material (54) in the channel openings (49) through the first and second tiers (32 and 42/46), the charge-storage material (54) comprising a first charge-trap density (¶ 0053, where 54 comprises SiON); increasing the first charge-trap density of the charge-storage material that is in the first tiers as compared to the charge-storage material that is in the second tiers to a second charge-trap density (figure 7C; ¶¶ 0079-80, where SiON 54 is converted to SiN 354; where according to Applicant’s ¶ 0021 increasing is removing oxygen. This is what happens to 354 per the paragraphs above); and forming channel material (60) in the channel openings (49) through the first and second tiers (32 and 42/46) and that is laterally-inward of the charge-storage material (54/354); and forming gate regions (detailed below) within the first tiers (detailed below), the forming the gate regions comprising (detailed below) a forming high-k liner material (154, ¶ 0079, where 154 can be SiN; Nakajimia teaches in at least the abstract that SiN is a high-k dielectric) and a conducive material (46), the high- k liner (154) material being formed in direct physical contact with an insulative material of the second tiers (32). Sharangpani does not teach: The high-k liner material comprises Al2O3. This is because Sharangpani with teaching reference Nakajima teach the high-k liner material comprises SiN. Xie teaches at least in figure 4: That high-k liners for transistor gates can comprise either SiN, Al2O3, among other materials. ¶ 0043. Based upon the teachings of Xie it would have been obvious to one of ordinary skill in the art to use an art recognized equivalent material for the same purpose of being a gate liner as taught by Sharangpani. MPEP 2144.06. Further, based upon the art recognized equivalence it would have been obvious to make said substitution as both materials are known to be used for the same purpose. MPEP 2144.07. Regarding claim 2, Sharangpani teaches at least in figure 1-7D: comprising forming the channel material after forming the charge-storage material (See figures 3A-3B, where 60 is formed after 54/354). Regarding claim 3, Sharangpani teaches at least in figure 1-7D: comprising forming the channel material before the increasing (figure 7B shows that 60 is formed before 354 in figure 7C). Regarding claims 4-6, 9, 23, and 26, Sharangpani teaches at least in figure 1-7D: It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the second and arrive at the claim limitation. This is because the charge density of the charge storage material is a result dependent variable. This because one of ordinary skill in the art understands the charge density of the charge storage material, and know how to vary the material in order to change the charge density of said charge storage materials. ¶¶ 0053, 81, 0101. Further, all the necessary materials to form the claimed device are well-known in the art. Therefore, with respect to these claims, because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). Thus optimization of the claim would be obvious to one of ordinary skill in the art. Regarding claims 7-8, 13, and 24-25, Sharangpani teaches at least in figure 1-7D: wherein the charge-storage material comprises SixNyOz, where the x and the y are greater than 0, and where the z is 0 or greater than 0 (¶0053). Regarding claims 10, and 27, Sharangpani teaches at least in figure 1-7E: wherein the increasing comprises adding nitrogen to the charge-storage material (¶ 0079, where a thermal nitridation process and a plasma nitridation process can be used to convert 54 to SiN). Regarding claim 21, Sharangpani teaches at least in figure 1-7D: forming a stack comprising vertically-alternating first tiers (42/46) and second tiers (32), the first tiers comprising sacrificial material (42) and the second tiers comprising non-sacrificial material (32) that is of different composition from that of the sacrificial material (¶ 0036), the stack comprising memory-block regions (area of 50 with 354) ; forming channel openings (49) through the first and second tiers in the memory-block regions (32 and 42/46); forming insulator material (53) in the channel openings (49) through the first and second tiers (32 and 42/46), the insulator material (53) being of different composition from that of the sacrificial material (42) and from that of the non-sacrificial material (32) (¶ 0037, where 42 “can be spacer material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium”. Compared with ¶ 0036, where 32 can be “silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials”. Compared with ¶ 0052, where 53 can be silicon oxide. Therefore, 42 can be silicon and germanium, 36 can be different than silicon germanium, and 53 can be different from silicon germanium and the plurality of material of 32. Thus, the prior art teaches this limitation); forming charge-storage material (54) in the channel openings (49) through the first and second tiers (32 and 42/46) laterally-inward of the insulator material (53), the charge-storage material comprising a first charge-trap density (based upon the material of 54 it will inherently have a first charge-trap density); forming channel material (60) in the channel openings (49) through the first and second tiers (32 and 42/46) laterally-inward of the charge-storage material (54); through horizontally-elongated trenches that individually extend through the first tiers and the second tiers between immediately-adjacent of the memory-block regions, removing the sacrificial material and the insulator material from the first tiers to expose the charge-storage material in the first tiers (figures 6-7B show this); increasing the first charge-trap density of the exposed charge-storage material that is in the first tiers as compared to the charge-storage material that is in the second tiers to a second charge-trap density (figure 7C; ¶¶ 0079-80, where SiON 54 is converted to SiN 354; where according to Applicant’s ¶ 0021 increasing is removing oxygen. This is what happens to 354 per the paragraphs above); and through the horizontally-elongated trenches, forming conducting material in the first tiers and that comprises control-gate lines in the memory-block regions (46; shown in figure 7E). Regarding claim 22, Sharangpani teaches at least in figure 1-7D: wherein the sacrificial material (42) comprises silicon nitride (¶ 0036, where 42 can be SiN, or SiON), the non-sacrificial material comprises (32) silicon dioxide, and the insulator material comprises at least one of hafnium oxide, aluminum oxide, yttrium oxide, zirconium oxide, and SiCN (¶ 0036). Regarding claim 28, Claim 28 is rejected for the same reasons as claim 1 and 11 above. Regarding claim 30, Claim 30 is rejected for the same reasons as claims 1, 11-12, and 24 above. Allowable Subject Matter Claims 11-12, and 29 are allowed. The following is an examiner’s statement of reasons for allowance: see below. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Regarding claim 11, The prior art does not teach: wherein the increasing comprises removing silicon. This is because the prior art only teaches removing oxygen. Not removing silicon with the oxygen. Regarding claim 29, Claim 29 is allowable for the same reason as claim 12 above. Response to Arguments Applicant’s arguments filed August 24, 2026, have been fully considered. Regarding claim 1, Applicant’s amendments have overcome the art of record. However, Examiner has introduced new grounds of rejection based upon Applicant’s amendments. Regarding claim 21, Applicant asserts Examiner did not explain the limitation: insulator material being of different composition from that of the sacrificial material and from that of the non-sacrificial material. This is incorrect as shown above in the analysis of the claim. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jan 03, 2024
Application Filed
Mar 26, 2026
Non-Final Rejection mailed — §103, §112
Jun 08, 2026
Response Filed
Jul 31, 2026
Final Rejection mailed — §103, §112
Aug 24, 2026
Request for Continued Examination
Aug 26, 2026
Response after Non-Final Action
Sep 02, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
62%
Grant Probability
87%
With Interview (+24.4%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 827 resolved cases by this examiner. Grant probability derived from career allowance rate.

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