DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1 and 1a in the reply filed on May 1, 2026 is acknowledged. The traversal is on the ground(s) that “it should be no undue burden on the Examiner to consider all claims in the single application”. This is not found persuasive because as outlined in the previous Office Action, the species are independent or distinct because they each require a different arrangement of the first and second insulating structures, the mesa portions, second semiconductor layer and the passivation layer and the species would require different search strategies, the searching of different terms and keywords, and the species would require different determination of allowability.
The requirement is still deemed proper and is therefore made FINAL.
Claims 5, 10-12, and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on May 1, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US 20130306997 A1) herein after “Lim”.
Regarding claim 1, Fig. 6G of Lime discloses a optoelectronic semiconductor device (Fig. 6G, “semiconductor light emitting device”, ¶ [0035]), comprising:
a stack structure having a top surface and comprising a first semiconductor layer (Fig. 6G, first conductive semiconductor layer 12a, ¶ [0038]), a second semiconductor layer (Fig. 6G, second conductive semiconductor layer 12b, ¶ [0038]) and an active region (Fig. 6G, active layer 12c, ¶ [0038]) between the first semiconductor layer (12a) and the second semiconductor layer (12b);
a first insulating structure (Fig. 6G, first insulation layer 15a, ¶ [0047]) covering the stack structure and having a first upper surface (see Annotation 1, Fig. 6G of Lim, US1) and a sidewall, wherein the first upper surface (US1) is coplanar with or lower than the top surface of the stack structure; and
a second insulating structure (Fig. 6C, second insulation layer 15b, ¶ [0047]) covering the first upper surface (US1), the sidewall of the first insulating structure (15a) and the top surface of the stack structure, wherein the first insulating structure (15a) directly contacts the second insulating structure (15b).
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Annotation 1, Fig. 6G of Lim
Regarding claim 3, Fig. 6G of Lim discloses the optoelectronic semiconductor device of claim 1 as applied above, and Figs. 6D and 6G of Lim further disclose wherein the stack structure comprises a mesa portion (see Annotation 1, Fig. 6G of Lim, MP) and a recess (Fig. 6D, isolation region IE, ¶ [0065]), wherein the mesa portion (MP) comprises an inner sidewall (see Annotation 1, Fig. 6G of Lim, IS1) and an outer sidewall (see Annotation 1, Fig. 6G of Lim, OS1), wherein the outer sidewall (OS1) surrounds the inner sidewall (IS1), and the inner sidewall (IS1) defines the recess (IE).
Regarding claim 4, Figs. 6D and 6G of Lim disclose the optoelectronic semiconductor device of claim 3 as applied above, and Fig. 6G of Lim further discloses wherein the first insulating structure (15a) covers the outer sidewall (OS1) and/or the inner sidewall (IS1) of the mesa portion (MP).
Regarding claim 7, Fig. 6G of Lim discloses the optoelectronic semiconductor device of claim 1 as applied above, and Fig. 6G of Lim further discloses comprising a first conductive layer (Fig. 6G, first electrode 14a, ¶ [0069]) on the first semiconductor layer (12a).
Regarding claim 8, Fig. 6G of Lim discloses the optoelectronic semiconductor device of claim 1 as applied above, and Fig. 6G of Lim further discloses comprising a second conductive layer (Fig. 6G, second electrode 14b, ¶ [0069]) on the second semiconductor layer (12b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lim (US 20130306997 A1) in view of Huang et al. (CN 111564537 A) herein after “Huang”.
Regarding claim 2, Fig. 6G of Lim discloses the optoelectronic semiconductor device of claim 1 as applied above, but Lim fails to disclose wherein the active region has a second upper surface, wherein the first upper surface of the first insulating structure is higher than the second upper surface of the active region.
In the similar field of endeavor light emitting elements, Fig. 1 of Huang discloses wherein the active region (Fig. 1, active region 2-2, ¶ [0059]) has a second upper surface, wherein the first upper surface of the first insulating structure (Fig. 1, first insulating protective layer 5, ¶ [0061]) is higher than the second upper surface of the active region (2-2).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the first insulating structure of Lim with the arrangement as disclosed by Huang, to improve light extraction from the horizontal surface (see Huang, ¶ [0097]).
Regarding claim 6, Figs. 6D and 6G of Lim disclose the optoelectronic semiconductor device of claim 3 as applied above, but Lim fails to disclose wherein the second insulating structure comprises:
a first opening on the first semiconductor layer, wherein the first opening overlaps the recess in a vertical direction; and
a second opening on the second semiconductor layer, wherein the second opening overlaps the mesa portion in the vertical direction, and the second opening and the first opening are separated from each other.
In the similar field of endeavor light emitting elements, Figs. 1 and 8.8 of Huang disclose wherein the second insulating structure (Fig. 1, second insulating protective layer 7, ¶ [0064]) comprises:
a first opening (Fig. 8.8, opening for electrode 8) on the first semiconductor layer (2-1), wherein the first opening (opening for electrode 8) overlaps the recess (2-4) in a vertical direction; and
a second opening (Fig. 8.8, opening for electrode 9) on the second semiconductor layer (2-3), wherein the second opening (opening for electrode 9) overlaps the mesa portion (2-5) in the vertical direction, and the second opening (opening for electrode 9) and the first opening (opening for electrode 8) are separated from each other.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the first insulating structure of Lim with the openings as disclosed by Huang, to allow for subsequent interconnection (see Huang, ¶ [0093]).
Regarding claim 9, Fig. 6G of Lim discloses the optoelectronic semiconductor device of claim 1 as applied above, but Lim fails to disclose comprising:
a first electrode on the first semiconductor layer and comprising a third upper surface; and
a second electrode on the second semiconductor layer;
wherein the second insulating structure comprises a fourth upper surface and the second electrode comprises a fifth upper surface, wherein the third upper surface of the first electrode is higher than the fourth upper surface of the second insulating structure, and the fifth upper surface of the second electrode is higher than the fourth upper surface of the second insulating structure.
In the similar field of endeavor light emitting elements, Fig. 1 of Huang discloses comprising:
a first electrode (Fig. 8.9, first electrode 8, ¶ [0066]) on the first semiconductor layer (2-1) and comprising a third upper surface; and
a second electrode (Fig. 8.9, second electrode 9, ¶ [0067]) on the second semiconductor layer (2-3);
wherein the second insulating structure (7) comprises a fourth upper surface and the second electrode (9) comprises a fifth upper surface, wherein the third upper surface of the first electrode (8) is higher than the fourth upper surface of the second insulating structure (7), and the fifth upper surface of the second electrode (9) is higher than the fourth upper surface of the second insulating structure (7).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the first insulating structure of Lim with the electrodes as disclosed by Huang, to allow for subsequent interconnection (see Huang, ¶ [0093]).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lim (US 20130306997 A1) in view of Chen et al. (US 20200020739 A1) herein after “Chen”.
Regarding claim 13, Fig. 6G of Lim discloses the optoelectronic semiconductor device of claim 1 as applied above, but Lim fails to disclose wherein the first insulating structure comprises a first thickness and the second insulating structure comprises a second thickness larger than the first thickness.
In the similar field of endeavor light emitting devices, Fig. 13 of Chen discloses wherein the first insulating structure (Fig. 13, second insulating layer 60, ¶ [0091]) comprises a first thickness and the second insulating structure (Fig. 13, third insulating layer 80, ¶ [0143]) comprises a second thickness larger than the first thickness (“the second insulating layer 60 comprises a thickness between 1000 angstrom and 20,000 angstrom”, (“the third insulating layer 80 comprises a thickness ranged between 2000 angstrom and 60,000 angstrom”, ¶ [0102] and [0151]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the insulating structures of Lim with the thicknesses as disclosed by Chen, to obtain the desired layer coverage and etch selectivity (see Chen, ¶ [0103]).
Regarding claim 14, Lim and Chen together disclose the optoelectronic semiconductor device of claim 13 as applied above, but Lim fails to disclose wherein a ratio of the second thickness to the first thickness is larger than 1 and smaller than or equal to 5.
In the similar field of endeavor light emitting devices, Fig. 13 of Chen discloses wherein a ratio of the second thickness to the first thickness is larger than 1 and smaller than or equal to 5 (“the second insulating layer 60 comprises a thickness between 1000 angstrom and 20,000 angstrom”, “the third insulating layer 80 comprises a thickness ranged between 2000 angstrom and 60,000 angstrom”, ¶ [0102] and [0151]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the insulating structures of Lim with the thicknesses as disclosed by Chen, to obtain the desired layer coverage and etch selectivity (see Chen, ¶ [0103]).
Regarding claim 15, Lim and Chen together disclose the optoelectronic semiconductor device of claim 13 as applied above, but Lim fails to disclose wherein the first thickness is between 50 nm and 150 nm, and the second thickness is between 200 nm and 800 nm.
In the similar field of endeavor light emitting devices, Fig. 13 of Chen discloses wherein the first thickness is between 15 nm and 150 nm (“the second insulating layer 60 comprises a thickness between 1000 angstrom and 20,000 angstrom”, ¶ [0102]), and the second thickness is between 200 nm and 800 nm (“the third insulating layer 80 comprises a thickness ranged between 2000 angstrom and 60,000 angstrom”, ¶ [0151]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the insulating structures of Lim with the thicknesses as disclosed by Chen, to obtain the desired layer coverage and etch selectivity (see Chen, ¶ [0103]).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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