DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-17, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2020/0091063 A1).
Regarding claim 1, Chen discloses a semiconductor structure (Figs 2D & 11, per ¶87 the Figs are considered together), comprising: a first substrate (110B’) and a second substrate (110C’) stacked with each other; a first passive element (150A) located in the first substrate and a second passive element (150B) is located in the second substrate; a first wire layer (CS2) located on a top surface of the first substrate, directly contacting and electrically connected to the first passive element; and a first conductive pad (134D) located on a bottom surface of the second substrate and directly contacting the first wire layer.
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Regarding claim 2, Chen discloses that the first substrate and the second substrate comprise silicon substrates (¶25; ¶60).
Regarding claim 3, Chen discloses that the first passive element and the second passive element comprise deep trench capacitors (¶26; ¶61).
Regarding claim 4, Chen discloses that each deep trench capacitor comprises a first electrode layer (151), an insulating layer (152) and a second electrode layer (153), which are located in a plurality of parallel trenches in the first substrate or the second substrate.
Regarding claim 5, Chen discloses a first dielectric layer (135C & 135D) between the first substrate and the second substrate, wherein the first wire layer and the first conductive pad are located in the first dielectric layer.
Regarding claim 8, Chen discloses a conductive plug (142) penetrating through the second substrate and electrically connected to a second conductive pad (lower element 164).
Regarding claim 9, Chen discloses a second wire layer (upper element 164) on the top surface of the second substrate, wherein the second wire layer is electrically connected with the second passive element and the conductive plug.
Regarding claim 10, Chen discloses a semiconductor structure (Figs 2D & 11, per ¶87 the Figs are considered together), comprising: a first substrate (110B’) and a second substrate (110C’) stacked with each other; a first passive element (150A) located in the first substrate and a second passive element (150B) located in the second substrate; a first wire layer (131C) located on a top surface of the first substrate and electrically connected to the first passive element; a first conductive pad (131D) located on a bottom surface of the second substrate; and a conductive bump (134C & 134D) located between the first substrate and the second substrate and directly contacts the first wire layer and the first conductive pad.
Regarding claim 11, Chen discloses that the first substrate and the second substrate comprise silicon substrates (¶25; ¶60).
Regarding claim 12, Chen discloses that the first passive element and the second passive element comprise deep trench capacitors (¶26; ¶61).
Regarding claim 13, Chen discloses that each deep trench capacitor comprises a first electrode layer (151), an insulating layer (152) and a second electrode layer (153), which are located in a plurality of parallel trenches in the first substrate or the second substrate.
Regarding claim 14, Chen discloses a first dielectric layer (132C) located on the top surface of the first substrate, wherein the first wire layer is located in the first dielectric layer.
Regarding claim 15, Chen discloses a bottom dielectric layer (132D) located on the bottom surface of the second substrate, wherein the first conductive pad is located in the bottom dielectric layer.
Regarding claim 16, Chen discloses a filling layer (135C & 135D) located between the first dielectric layer and the bottom dielectric layer, wherein the conductive bump is located in the filling layer.
Regarding claim 19, Chen discloses a conductive plug (142) penetrating through the second substrate, and electrically connected with the conductive bump through the first conductive pad (131D).
Regarding claim 20, Chen discloses a second wire layer (160) on a top surface of the second substrate, wherein the second wire layer is electrically connected to the conductive plug.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 7, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding claim 6, Chen discloses a structure (160) located above the second substrate and electrically connected with the second passive element circuit substrate (110A; ¶20), however for consideration of this claim the structure can be reoriented such that 110C’ is considered the first substrate and 110B’ is considered the second substrate, such that circuit structure 160 is located below the first substrate and electrically connected with the first passive element 150B. Per ¶68, circuit structure 160 is adapted for connection with further elements. Chen does not disclose such a further element being a circuit substrate. However, it would be obvious to one of ordinary skill in the art at the time of filing to select a chip as the further element as is typical in electronics manufacturing where further connections may be made to either a chip or circuit board (i.e. circuit substrate).
Regarding claim 7, Chen discloses that the circuit structure of Fig 2D is adapted for connection with further elements (¶68), where said connections are provided above the second substrate and provide electrical connection to the second passive element. Chen does not disclose such a further element being a chip. However, it would be obvious to one of ordinary skill in the art at the time of filing to select a chip as the further element as is typical in electronics manufacturing where further connections may be made to either a chip or circuit board.
Regarding claim 17, Chen discloses a structure (160) located above the second substrate and electrically connected with the second passive element circuit substrate (110A; ¶20), however for consideration of this claim the structure can be reoriented such that 110C’ is considered the first substrate and 110B’ is considered the second substrate, such that circuit structure 160 is located below the first substrate and electrically connected with the first passive element 150B. Per ¶68, circuit structure 160 is adapted for connection with further elements. Chen does not disclose such a further element being a circuit substrate. However, it would be obvious to one of ordinary skill in the art at the time of filing to select a chip as the further element as is typical in electronics manufacturing where further connections may be made to either a chip or circuit board (i.e. circuit substrate).
Regarding claim 18, Chen discloses that the circuit structure of Fig 2D is adapted for connection with further elements (¶68), where said connections are provided above the second substrate and provide electrical connection to the second passive element. Chen does not disclose such a further element being a chip. However, it would be obvious to one of ordinary skill in the art at the time of filing to select a chip as the further element as is typical in electronics manufacturing where further connections may be made to either a chip or circuit board.
Response to Arguments
Applicant's arguments filed 24 June 2026 have been fully considered but they are not persuasive. Chen discloses the subject matter of applicant’s amended claims per the rejections above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL P SHOOK whose telephone number is (571)270-7890. The examiner can normally be reached 9:00 am - 5:00 pm, Mon-Fri.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached at (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL P SHOOK/Primary Examiner, Art Unit 2896
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