DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4 and 13 refer to the structure of “the deep trench capacitor” whereas claims 3 and 12 require that both the first passive element and the second passive element are deep trench capacitors, meaning that there are two deep trench capacitors. The language of claims 4 and 13 are unclear as to which deep trench capacitor is supposed to have the claimed structure, or if it is at least one of them or both. For examining purposes, the claims shall be read as “wherein each deep trench capacitor comprises…” as the claimed elements are required components of a deep trench capacitor regardless of if they are claimed or not.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-17, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2020/0091063 A1).
Regarding claim 1, Chen discloses a semiconductor structure (Fig 2D), comprising: a first substrate (110B) and a second substrate (110C) stacked with each other; a first passive element (150A) located in the first substrate and a second passive element (150B) is located in the second substrate; a first wire layer (134C) located on a top surface of the first substrate and electrically connected to the first passive element; and a first conductive pad (134D) located on a bottom surface of the second substrate and directly contacting the first wire layer.
PNG
media_image1.png
554
784
media_image1.png
Greyscale
Regarding claim 2, Chen discloses that the first substrate and the second substrate comprise silicon substrates (¶25; ¶60).
Regarding claim 3, Chen discloses that the first passive element and the second passive element comprise deep trench capacitors (¶26; ¶61).
Regarding claim 4, Chen discloses that each deep trench capacitor comprises a first electrode layer (151), an insulating layer (152) and a second electrode layer (153), which are located in a plurality of parallel trenches in the first substrate or the second substrate.
Regarding claim 5, Chen discloses a first dielectric layer (135C & 135D) between the first substrate and the second substrate, wherein the first wire layer and the first conductive pad are located in the first dielectric layer.
Regarding claim 6, Chen discloses a circuit substrate (110A; ¶20) located below the first substrate and electrically connected with the first passive element.
Regarding claim 8, Chen discloses a conductive plug (142) penetrating through the second substrate and electrically connected to a second conductive pad (lower element 164).
Regarding claim 9, Chen discloses a second wire layer (upper element 164) on the top surface of the second substrate, wherein the second wire layer is electrically connected with the second passive element and the conductive plug.
Regarding claim 10, Chen discloses a semiconductor structure (Fig 2D), comprising: a first substrate (110B) and a second substrate (110C) stacked with each other; a first passive element (150A) located in the first substrate and a second passive element (150B) located in the second substrate; a first wire layer (131C) located on a top surface of the first substrate and electrically connected to the first passive element; a first conductive pad (131D) located on a bottom surface of the second substrate; and a conductive bump (134C & 134D) located between the first substrate and the second substrate and directly contacts the first wire layer and the first conductive pad.
Regarding claim 11, Chen discloses that the first substrate and the second substrate comprise silicon substrates (¶25; ¶60).
Regarding claim 12, Chen discloses that the first passive element and the second passive element comprise deep trench capacitors (¶26; ¶61).
Regarding claim 13, Chen discloses that each deep trench capacitor comprises a first electrode layer (151), an insulating layer (152) and a second electrode layer (153), which are located in a plurality of parallel trenches in the first substrate or the second substrate.
Regarding claim 14, Chen discloses a first dielectric layer (132C) located on the top surface of the first substrate, wherein the first wire layer is located in the first dielectric layer.
Regarding claim 15, Chen discloses a bottom dielectric layer (132D) located on the bottom surface of the second substrate, wherein the first conductive pad is located in the bottom dielectric layer.
Regarding claim 16, Chen discloses a filling layer (135C & 135D) located between the first dielectric layer and the bottom dielectric layer, wherein the conductive bump is located in the filling layer.
Regarding claim 17, Chen discloses a circuit substrate (110A; ¶20) located below the first substrate and electrically connected with the first passive element.
Regarding claim 19, Chen discloses a conductive plug (142) penetrating through the second substrate, and electrically connected with the conductive bump through the first conductive pad (131D).
Regarding claim 9, Chen discloses a second wire layer (upper element 164) on the top surface of the second substrate, wherein the second wire layer is electrically connected with the second passive element and the conductive plug.
Regarding claim 20, Chen discloses a second wire layer (160) on a top surface of the second substrate, wherein the second wire layer is electrically connected to the conductive plug.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding claim 7, Chen discloses that the circuit structure of Fig 2D is adapted for connection with further elements (¶68), where said connections are provided above the second substrate and provide electrical connection to the second passive element. Chen does not disclose such a further element being a chip. However, it would be obvious to one of ordinary skill in the art at the time of filing to select a chip as the further element as is typical in electronics manufacturing where further connections may be made to either a chip or circuit board.
Regarding claim 18, Chen discloses that the circuit structure of Fig 2D is adapted for connection with further elements (¶68), where said connections are provided above the second substrate and provide electrical connection to the second passive element. Chen does not disclose such a further element being a chip. However, it would be obvious to one of ordinary skill in the art at the time of filing to select a chip as the further element as is typical in electronics manufacturing where further connections may be made to either a chip or circuit board.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL P SHOOK whose telephone number is (571)270-7890. The examiner can normally be reached 9:00 am - 5:00 pm, Mon-Fri.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached at (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL P SHOOK/Primary Examiner, Art Unit 2896
Prosecution Insights