DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to a Restriction Requirement mailed on 04/03/2026, the Applicant elected without traverse Group I (claims 1-16) and withdrew claims 17-20 in a reply filed on 05/14/2026.
Currently, claims 1-16 are examined as below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 01/04/2024. The IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Display Panel Having Package Structures of Different Resistivities and Display Apparatus Including the Display Panel
(Clean Version) Display Panel Having Package Structures of Different Resistivities and Display Apparatus Including the Display Panel
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-7 and 10-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 is indefinite, because the limitation “a first connection part” in line 8 renders the claim indefinite. It is unclear whether such first connection part is the same structure as “a first connection” recited in lines 7-8 of claim 5. The limitation will be interpreted as the same structure.
Claim 10 is indefinite, because the limitation “a volume concentration of the first conductive material in the first part is P21, a volume concentration of the first conductive material in the second part is P22, and P21 ≤ P22” renders the claim indefinite. According to the intervening claim 8, the first conductive material is included in the first package structure and the second conductive material is included in the second package structure, and claim 10 recites the second package structure comprises the first part and the second part. In other words, the second package structure does not include the first conductive material and thus the first and second parts of the second package structure do not include the first conductive material. It is unclear how the first conductive material is in the first and second parts of the second package structure, or if it should be the second conductive material that is in the first and second parts of the second package structure.
Claim 11 is indefinite, because the limitation “a volume concentration of the first conductive material in the third part is P23, a volume concentration of the first conductive material in the fourth part is P24, and P23≥P24” renders the claim indefinite. According to the intervening claim 8, the first conductive material is included in the first package structure and the second conductive material is included in the second package structure, and claim 11 recites the second package structure comprises the third part and the fourth part. In other words, the second package structure does not include the first conductive material and thus the third and fourth parts of the second package structure do not include the first conductive material. It is unclear how the first conductive material is in the third and fourth parts of the second package structure, or if it should be the second conductive material that is in the third and fourth parts of the second package structure.
Note the dependent claims 6-7 necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0381474 A1 to Choi et al. (“Choi”).
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Regarding independent claim 1, Choi in Figs. 5A-5B, 6 and Annotated Fig. 5A teaches a display panel DP (Fig. 5A & ¶ 65, display panel DP), comprising:
a base substrate BS2 (¶ 132, base layer BS2);
a plurality of light-emitting devices LD1-LD3 (Fig. 5A, ¶ 148, first light emitting diodes LD1, second light emitting diodes LD2, and third light emitting diodes LD3) located on a side (Fig. 5A, upper side) of the base substrate BS2, wherein the light-emitting device LD1, LD2, LD3 comprises a first semiconductor layer SCP (Figs. 5A, 6, ¶ 158, p-type semiconductor layer SCP), a second semiconductor layer SCN (Figs. 5A, 6, ¶ 158, n-type semiconductor layer SCN) and a light-emitting layer AL (Figs. 5A, 6, ¶ 158, active layer AL) located between the first semiconductor layer SCP and the second semiconductor layer SCN, and the second semiconductor layer SCN is located on a side of the light-emitting layer AL away from the base substrate BS2 (Figs. 5A-5B & 6);
a first package structure EP, ILL (Figs. 5A-5B, ¶ 144, ¶ 154, a collective of polymer resin layer EP and insulating layer ILL), located on the side of the base substrate BS2, wherein the first package structure EP, ILL comprises a first package part pp1 (Annotated Fig. 5A) located between two adjacent light-emitting devices LD1, LD2, LD3 of the plurality of light-emitting devices LD1-LD3; and
a second package structure CE (Fig. 5A, ¶ 155, common electrode CE), wherein at least part of the second package structure CE is located on a side of a light-emitting device LD1, LD2, LD3 away from the base substrate BS2 (Figs. 5A-5B), a resistivity of at least a part of the first package structure EP, ILL is σ1 (¶ 144, ¶ 154, insulating layer ILL including photoresist is an electrical insulator that would have high resistivity), a resistivity of the second package structure CE is σ2 (¶ 155, common electrode CE includes IZO or ITO which is electrical conductor that would have low resistivity), and σ2 < σ1 (¶ 144, ¶ 154-¶ 155, electrical conductor CE has a resistivity lower than the electrical insulator ILL).
Regarding independent claim 16, Choi in Figs. 1B, 5A-5B, 6 and Annotated Fig. 5A teaches a display apparatus DD (Fig. 1B & ¶ 53, display device DD), comprising a display panel DP (Fig. 1B, ¶ 56, ¶ 64, display panel DP, in which the display device DD includes a display module DM that comprises the display module DP),
the display panel DP comprising:
a base substrate BS2 (¶ 132, base layer BS2);
a plurality of light-emitting devices LD1-LD3 (Fig. 5A, ¶ 148, first light emitting diodes LD1, second light emitting diodes LD2, and third light emitting diodes LD3) located on a side (Fig. 5A, upper side) of the base substrate BS2, wherein the light-emitting device LD1, LD2, LD3 comprises a first semiconductor layer SCP (Figs. 5A, 6, ¶ 158, p-type semiconductor layer SCP), a second semiconductor layer SCN (Figs. 5A, 6, ¶ 158, n-type semiconductor layer SCN) and a light-emitting layer AL (Figs. 5A, 6, ¶ 158, active layer AL) located between the first semiconductor layer SCP and the second semiconductor layer SCN, and the second semiconductor layer SCN is located on a side of the light-emitting layer AL away from the base substrate BS2 (Figs. 5A-5B & 6);
a first package structure EP, ILL (Figs. 5A-5B, ¶ 144, ¶ 154, a collective of polymer resin layer EP and insulating layer ILL), located on the side of the base substrate BS2, wherein the first package structure EP, ILL comprises a first package part pp1 (Annotated Fig. 5A) located between two adjacent light-emitting devices LD1, LD2, LD3; and
a second package structure CE (Fig. 5A, ¶ 155, common electrode CE), wherein at least part of the second package structure CE is located on a side of a light-emitting device LD1, LD2, LD3 away from the base substrate BS2 (Figs. 5A-5B), a resistivity of at least a part of the first package structure EP, ILL is σ1 (¶ 144, ¶ 154, insulating layer ILL including photoresist is an electrical insulator that would have high resistivity), a resistivity of the second package structure CE is σ2 (¶ 155, common electrode CE includes IZO or ITO which is electrical conductor that would have low resistivity), and σ2 < σ1 (¶ 144, ¶ 154-¶ 155, electrical conductor CE would have a resistivity lower than the electrical insulator ILL).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable and obvious over Choi.
Regarding claim 8, Choi in Fig. 5A and Annotated Fig. 5A teaches the first package structure EP, ILL comprises a first conductive material (¶ 147, polymer resin layer EP includes conductive particles), a volume concentration of the first conductive material in the first package structure EP, ILL is P1 (¶ 147, concentration of the conductive particles), the second package structure CE comprises a second conductive material CE (¶ 155, transparent electrode including IZO or ITO), a volume concentration of the second conductive material CE in the second package structure CE is P2 (¶ 155, the conductive material CE including IZO or ITO must have a volume concentration), and P1 < P2.
Choi does not explicitly disclose P1 < P2.
However, Choi teaches a general condition in which the first conductive material has a volume concentration P1 (¶ 147, concentration of the conductive particles) and the second conductive material has a volume concentration P2 (¶ 155, the conductive material CE including IZO or ITO must have a volume concentration).
According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, since Choi teaches said general conditions, it would not be inventive to discover the optimum or workable ranges by routine experimentation before the effective filing date of the claimed invention. Unless the Applicant can show that the specific conditions of P1 < P2 produce unexpected results that are different in kind and not different in degree, said general conditions taught by Choi renders claim 8 obvious.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2-4, 9 and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 2 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 2, wherein the second semiconductor layer is in direct contact with the second package structure.
Claims 3-4 would be allowable, because they depend from the allowable claim 2.
Claim 9 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 9, wherein the first package structure and the second package structure both comprise a first insulating material; and the first conductive material is the same as the second conductive material.
Claim 12 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 12, a resistivity of the third package structure is σ3, and σ3 < σ2.
Claim 13 would be allowable, because claim 13 depends from the allowable claim 12.
Claim 14 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 14, a support structure located in the non-display area, wherein the support structure at least partly surrounds the first package structure; and the array layer comprises a first connection part located in the non-display area, and the first connection part is located on a side of the support structure closer to the display area.
Claim 15 would be allowable, because claim 13 depends from the allowable claim 14.
Claims 5-7 and 10-11 are rejected, but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 5 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 5, a support structure located in the non-display area, wherein the support structure at least partly surrounds the second package structure; and the array layer comprises a first connection located in the non-display area, and a first connection part is located on a side of the support structure closer to the display area, wherein at least part of the second package structure is in contact connection with the first connection part.
Claims 6-7 would be allowable, because they depend from the allowable claim 5.
Claim 10 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 10, a volume concentration of the first conductive material in the first part is P21, a volume concentration of the first conductive material in the second part is P22, and P21 ≤ P22.
Claim 11 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 11, a wavelength of light emitted by the first light-emitting device is greater than a wavelength of light emitted by the second light-emitting device; a volume concentration of the first conductive material in the third part is P23, a volume concentration of the first conductive material in the fourth part is P24, and P23 ≥ P24.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2019/0013306 A1 to Wu et al. relates to a micro LED display panel with enhanced display properties including a substrate, a plurality of micro LEDs on the substrate, at least one common electrode, and a plurality of contact electrodes. Each micro LED includes top and bottom ends and a sidewall between them. The common electrode is coupled to the top end and a contact electrode is coupled to the bottom end. An adjustment electrode insulated from the other electrodes is formed on the sidewall of each of the plurality of micro LEDs.
US 2022/0005994 A1 to Morita et al. relates to a display device including a substrate, a pixel electrode disposed on the substrate, a light emitting element mounted on the pixel electrode, a drive transistor configured to control a current supplied to the light emitting element through the pixel electrode, and a conductive layer formed between the pixel electrode and the drive transistor so as to at least partially overlap with the pixel electrode in a planar view.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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