Prosecution Insights
Last updated: April 19, 2026
Application No. 18/403,779

PHOTOELECTRIC DEVICE, OPTICAL TRANSCEIVER, AND METHOD OF OPERATING PHOTOELECTRIC DEVICE

Non-Final OA §102§103§112
Filed
Jan 04, 2024
Examiner
CAPUTO, LISA M
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
8%
Grant Probability
At Risk
1-2
OA Rounds
2y 2m
To Grant
0%
With Interview

Examiner Intelligence

Grants only 8% of cases
8%
Career Allow Rate
3 granted / 38 resolved
-60.1% vs TC avg
Minimal -8% lift
Without
With
+-7.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
22 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§101
4.5%
-35.5% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
25.4%
-14.6% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 38 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-17 (and additionally added claims 21-23) in the reply filed on 12/16/2025 is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 23 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention. Claim 23 recites the limitation "The optical transceiver" in line 1. There is insufficient antecedent basis for this limitation in the claim. It appears that either it should be either dependent on the photoelectric device of claim 22, or if indeed an optical transceiver, one of the earlier claims 9-17. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6, 8, and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Alpati et al (U.S. Patent No. 11,107,799). Regarding claim 1, Alpati teaches a photoelectric device, comprising: a first die (Fig. 10, 1040 and Col 13 Ln 4-32) including a first back side and a first front side opposite to the first back side (Fig. 10, bottom surface of 1040); and a second die (Fig. 10, 1030) disposed over the first die, and including a second front side and a second back side (Fig. 10, bottom surface of 1030) opposite to the second front side and bonded to the first back side, wherein the second die comprises: an optical circuitry configured to generate or process a first optical signal (see Fig. 7, 623-626 and Col 12 Ln 8-13); and an electrical circuitry electrically coupled to the first die, configured to control an operation of the optical circuitry by a first electrical signal inputted into the first die or to generate a second electrical signal and provide the second electrical signal to the first die in response to the first optical signal (Fig. 7, Logic, 646, etc. ; Col 12 Ln 101-18 and Col 18 Ln 21-23). Regarding claim 2, Alpati teaches that the electronic die comprises: a substrate (Fig. 10, 1040); a dielectric layer (Col 9 Ln 8-13) disposed on the substrate and at the first front side of the electronic die; an electronic component (Col 8 Ln 30-41) disposed in or on the substrate; a conductive pillar (Fig. 10, 1044) extending through the dielectric layer and to the substrate; and a interconnect structure (Fig. 10, dashed lines indicate electrical interconnection layers, 1042, 1044, etc.) disposed on the substrate and at the first back side of the electronic die, wherein the interconnect structure connects the conductive pillar to the electronic component; wherein the conductive pillar is utilized to receive the first electrical signal from an external circuitry or to transmit the second electrical signal to the external circuitry (Fig. 10, 1022, 1024, etc.). Regarding claim 3, Alpati teaches the electronic component is disposed at the first front side of the first die (Fig. 10, silicon layer 1040)and is separated laterally from the conductive pillar (Fig. 10, 1044); the first interconnect structure comprises a plurality of first conductive features (Fig. 10, dashed line structures); and the electronic component is overlapped by the first conductive features from a top-view perspective (the conductive features will overlap the components at least at the connection point between the two features). Regarding claim 4, Alpati teaches that the second die further comprises: a semiconductor layer (Fig. 10, 1030; Col 8 Ln 3-29), wherein the optical circuitry is disposed therein or thereover; and a second interconnect structure (Fig. 10, dashed lines indicate electrical interconnection layers of 1030) disposed on the semiconductor layer and at the second back side of the second die, wherein the second interconnect structure is physically and electrically coupled to the first interconnect structure (Col 8 Ln 61 – Col 9 Ln 19). With respect to claim 5, Alpati teaches that the optical circuitry comprises an optical feature operable to generate or process the first optical signal (Fig. 10, unlabeled, Fig. 7, waveguide 623 or photodetector 634), the optical feature is disposed in or on the semiconductor layer and electrically coupled to the electrical circuitry, and the optical feature overlaps the electronic component from a top-view perspective (Fig. 6, components 630 and 640 overlap). Regarding claim 6, Alpati teaches that the second die is hybrid-bonded to the first die (Col 8 Ln 61 – Col 9 Ln 19). Regarding claim 8, Alpati teaches that the first optical signal enters or exits the second die through the second front side (Fig. 10, top surface of 1030), the first electrical signal is inputted into the first die through the first front side, and the second electrical signal exits the first die through the first front side (Fig. 10, electric signals input/output from bond pads 1042). Regarding claim 21, Alpati teaches a photoelectric device, comprising: an electronic die (Fig. 10, 1040 and Col 13 Ln 4-32) including a first back side (Fig. 10, bottom surface of 1040) and a first front side opposite to the first back side; and an optical die (Fig. 10, 1030) disposed over the electronic die, and including a second front side and a second back side (Fig. 10, top surface of 1030) opposite to the second front side, wherein the second back side is bonded to the first back side, wherein the optical die comprises: an optical circuitry configured to generate or process a first optical signal (see Fig. 7, 623-626 and Col 12 Ln 8-13); an insulating layer (Col 9 Ln 8-13) disposed at the second front side of the optical die, wherein the insulating layer surrounds and covers the optical circuitry; and an electrical circuitry electrically coupled to the electronic die (Fig. 7, Logic, 646, etc. ; Col 12 Ln 101-18 and Col 18 Ln 21-23). Regarding claim 22, Alpati teaches that the electronic die comprises: a substrate (Fig. 10, 1040); a dielectric layer (Col 9 Ln 8-13) disposed on the substrate and at the first front side of the electronic die; an electronic component (Col 8 Ln 30-41) disposed in or on the substrate; a conductive pillar (Fig. 10, 1044) extending through the dielectric layer and to the substrate; and a interconnect structure (Fig. 10, dashed lines indicate electrical interconnection layers, 1042, 1044, etc.) disposed on the substrate and at the first back side of the electronic die, wherein the interconnect structure connects the conductive pillar to the electronic component. Regarding claim 23, Alpati teaches the electronic component (Col 8 Ln 30-41) is disposed at the first front side of the electronic die (Fig. 10, front side of silicon wafer), is separated laterally from the conductive pillar (Fig. 10, 1044), and electrically connected to the interconnect structure (Fig. 10, dashed line structures). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 7 and 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Alpati, in view of Yu et al (USPGPub 2020/0003975). Regarding claim 7, Alpati does not teach a dummy die laterally separated from the first die and bonded to the second die. Yu teaches a dummy die (Fig. 10, portion D of dummy die 100b) laterally separated from the first die (Fig. 8, 300a) and bonded to the second die (Fig. 8, 200). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a dummy die bonded to the second die of Alpati as taught by Yu in order to improve the form factor and yield rate of the assembly (Paragraph 36 and 4, and 50). Regarding claim 9, Alpati teaches an optical device comprising: a first electronic die (Fig. 9-11, 1040 and Col 13 Ln 4-32) including a first back side and a first front side opposite to the first back side; and a first optical die (Fig. 9-11, 1030) disposed over the first electronic die, and including a second front side and a second back side opposite to the second front side, wherein the first optical die comprises: an optical circuitry configured to generate or process a first optical signal (see Fig. 7, 623-626 and Col 12 Ln 8-13); and an electrical circuitry electrically coupled to the first electronic die (Fig. 7, Logic, 646, etc. ; Col 12 Ln 101-18 and Col 18 Ln 21-23), wherein the electrical circuitry is configured to control an operation of the optical circuitry by a first electrical signal inputted into the first electronic die; an optical receiver (Fig. 10, photodetector 634 and/or waveguide 632; Fig. 7); and an optical fiber (Fig. 10, 1060; Fig. 9, 960) configured to transmit the first optical signal to the optical receiver. Alpati does not teach specifically and directly that the assembly is an optical transceiver. Yu teaches an optical assembly that is an optical transceiver (Fig. 3K, OTC), wherein the optical die (Fig. 3K, 200) is configured an optical receiver and transmitter (Paragraph 20). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the optical assembly of Alpati as an optical transceiver as taught by Yu in order to configure the assembly for use in a high speed optical communication systems (Paragraph 2) Regarding claim 10, Alpati teaches that the optical fiber (Fig. 10, 1060) is attached to the second front side or the second back side of the first optical die (Fig. 10, 1030). Regarding claim 11, Alpati teaches that the first optical die further comprises: a semiconductor layer (Col 6 Ln 51-52), wherein the optical circuitry is disposed therein or thereover (see Fig. 7, 623-626 and Col 12 Ln 8-13); an insulating layer (Col 9 Ln 8-13) disposed on the semiconductor layer and at the second front side of the first optical die, wherein the insulating layer is used to surround and cover the optical circuitry; and a coupler recess (Fig. 9, 932 and 1132 overlap with the optical circuitry portion of 930 and 1130) disposed in the insulating layer, wherein the coupler recess overlaps a part of optical circuitry from a top-view perspective (Figs. 9 and 11, the 9, wherein the optical fiber (Fig. 9, 960) is disposed on or in the coupler recess. Regarding claim 12, Alpati teaches that the first optical die further comprises an alignment mark (Fig. 9, 932) disposed in or on the insulating layer and exposed through the coupler recess. Regarding claim 13, Alpati teaches that the optical circuitry comprises a two-dimensional grating coupler (Col 8 Ln 10) overlapped by the coupler recess from the top-view perspective. Regarding claim 14, Alpati teaches that the first optical die further comprises: a semiconductor layer (Col 6 Ln 51-52), wherein the optical circuitry is disposed therein or thereover (see Fig. 7, 623-626 and Col 12 Ln 8-13); an insulating layer (Col 9 Ln 8-13) disposed on the semiconductor layer and at the second front side of the first optical die, wherein the insulating layer surrounds and covers the optical circuitry; and a coupler trench penetrating through the insulating layer at an edge of the semiconductor layer (Fig. 9, insulating portion on semiconductor layer 930 is etched/singulated at the edges to create a trench through the top surface of the insulating layer to the groove 932), wherein a portion of the optical fiber (Fig. 9, 960) is disposed in the coupler trench. Regarding claim 15, Alpati teaches that the first optical die further comprises an alignment mark (Fig. 9, 932) disposed on a sidewall exposed through the coupler trench. Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Alpati and Yu, in view of Roth et al (U.S. Patent 9,122,006). Regarding claim 16, Alpati teaches that the optical circuitry comprises an edge coupler (Col 9 Ln 43-44) but does not teach a polarizing beam splitter connected to the edge coupler. Roth teaches a PIC comprising a polarizing beam splitter (Fig. 4, 404) connected to the coupler. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a beam splitter in the optical circuitry of Alpati as taught by Roth in order to enable the optical circuitry to split components of the received light and then process separately (Col 1 Ln 18-30). Regarding claim 17, Alpati does not teach that the optical circuitry further comprises a polarization rotator interposed between the edge coupler and the polarizing beam splitter. Roth teaches a polarization rotator (Fig. 4, 403 and Col 4 Ln 27-38) interposed between the coupler and the polarizing beam splitter (Fig. 4, 404). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a polarization rotator interposed between the edge coupler of Alpati and the polarizing beam splitter as taught by Roth in order to convert between modes of received light (Col 2 Ln 61-67). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LISA M CAPUTO whose telephone number is (571)272-2388. The examiner can normally be reached Monday-Friday 9-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LISA M CAPUTO/Primary Patent Examiner, Art Unit 2874
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Prosecution Timeline

Jan 04, 2024
Application Filed
Feb 06, 2026
Non-Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
8%
Grant Probability
0%
With Interview (-7.9%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 38 resolved cases by this examiner. Grant probability derived from career allow rate.

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