DETAILED ACTION
Claims 1, 5-6, 9, and 15 are pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 11/17/2025 have been fully considered but they are not persuasive. Applicant asserts, as amended, claim 1 (and claims 9 and 15), recite two parts of the semiconductor storage device (i.e., a first receive unit, etc., and a second receive unit, etc.), wherein these two parts share the same reference potential (e.g. VREF) provided by a voltage generator. Applicant alleges, Tang does not teach or suggest the combination of these features.
Tang discloses,
“It is noted that the input buffer 432DQx may represent any digit (e.g., bit) of data of the integrated circuit device 400A, where a value of x may represent a significance of the corresponding digit. For example, for eight digits of data, the integrated circuit device 400A may include eight input buffers 432DQ0-432DQ7 of the same (e.g., similar) configuration as input buffer 432DQx depicted in FIG. 4A.” (See Tang at para. [0042])
That is, Tang clearly teaches that the input buffer 432DQx (corresponding to a first comparison circuit), and the input buffer’s associated connections with peripheral components, is an example embodiment for multiple instances of input buffers for any number of digits of data that may be received by a memory device.
Additionally, Tang does not teach or suggest any other duplicate input buffer for another digit of data would be connected to any reference voltage other than Vrefq (provided by voltage node 460 in FIG. 4A), nor is there any evidence to presume otherwise.
Therefore, a person having ordinary skill in the art may induce that Tang teaches a first receive unit, a first comparison circuit, and a first variable current source along with a second receive unit, a second comparison circuit, and a second variable current source; wherein the first and the second comparison circuits share the same reference potential. The rejections of claims 1, 5-6, 9, and 15 are maintained below.
Claim Objections
Claims 1 and 9 objected to because of the following informalities:
Claim 1, lines 5-6, should read, “a first comparison circuit having a first input terminal connected to the first receive unit . . .”
Claim 9, lines 8-9, should read, “a first comparison circuit having a first input terminal connected to the first receive unit . . .”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 9, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tang et al. (US 3 B1; hereinafter "Tang").
Regarding claim 1, Tang discloses a semiconductor storage device comprising (FIG. 1: memory device 100): a voltage generator configured to generate a reference potential (Para. [0041]: “The reference voltage Vrefq might be received from an external device, or it might be generated internal to the integrated circuit device 400A.” – Voltage generators are also common in the art; therefore, it may be presumed the memory device of Tang includes a voltage generator based on the disclosure in para. [0041]); a first receive unit configured to receive a first toggle signal supplied outside of the semiconductor device (FIG. 4A: integrated circuit device 400A including conductive node 454DQx); a first comparison circuit (FIG. 4A: input buffer 432DQx) having a first input terminal connected to the first receiving unit (FIG. 4A: first input 436DQx), a second terminal connected to the voltage generator (FIG. 4A and para. [0041]: voltage node 460 is configured to receive a reference voltage such as Vrefq), and an output terminal, wherein the first comparison circuit is configured to generate and output a second toggle signal through its output terminal (FIG. 4A: output 440DQx), and wherein the second toggle signal switches based on a relationship of the first toggle signal relative to the reference potential (FIG. 3A and 3B demonstrate the output switching characteristic of the input buffers 432 relative to the reference voltage Vrefq); a first variable current source connected to the output terminal of the first comparison circuit and configured to provide a first current output (FIG. 4A and para. [0043]: calibration circuitry 434DQx is depicted with variable current sources; FIG. 5A: calibration circuitry 434A includes variable current source 555 connected to the node providing the output 440); a second receive unit configured to receive a third toggle signal supplied from the outside of the semiconductor storage device (FIG. 4A: integrated circuit device 400A including conductive node 454DQx – see notes with respect to para. [0042] in the response to arguments above); a second comparison circuit (FIG. 4A: input buffer 432DQx) having a first input terminal connected to the second receive unit (FIG. 4A: first input 436DQx), a second input terminal connected to the voltage generator (FIG. 4A and para. [0041]: voltage node 460 is configured to receive a reference voltage such as Vrefq), and an output terminal, wherein the second comparison circuit is configured to generate and output a fourth toggle signal through its output terminal (FIG. 4A: output 440DQx), and wherein the fourth toggle signal switches based on a relationship of the third toggle signal relative to the reference potential (FIG. 3A and 3B demonstrate the output switching characteristic of the input buffers 432 relative to the reference voltage Vrefq); a second variable current source connected to the output terminal of the second comparison circuit and configured to provide a second current output (FIG. 4A and para. [0043]: calibration circuitry 434DQx is depicted with variable current sources; FIG. 5A: calibration circuitry 434A includes variable current source 555 connected to the node providing the output 440); and a sequencer configured to supply a first adjustment signal to the first variable current source so as to adjust the first current output and supply a second adjustment signal to the second variable current source so as to adjust the second current output ((FIG. 1: the command register 124, in conjunction with the calibration logic 126, form an equivalent structure as a sequencer and performs the same claimed function; FIG. 4A and para. [0043]: “The calibration logic 126 may be in communication with, and provide a control signal to, . . . the calibration circuitry 434DQx for each input buffer 432DQx.”).
Regarding claim 5, Tang discloses the sequencer is configured to individually adjust the first current output and the second current output (FIG. 4A and para. [0043]: “The calibration logic 126 may be in communication with, and provide a control signal to, . . . the calibration circuitry 434DQx for each input buffer 432DQx.”; para. [0072]: “These control signals might be provided by the calibration logic 126. Similarly, where a variable current device of a calibration circuitry 434 is used in more than one instance, e.g., the variable current device 554 and variable current device 555 of FIG. 5A, separate sets of control signals might be provided to each instance of a variable current device.”).
Regarding claim 9, Tang discloses a memory system, comprising: a memory controller (FIG. 1: processor 130) configured to provide a first toggle signal and a second toggle signal (FIG. 4A: driver 458DQx); and a plurality of semiconductor storage devices (FIG. 1: memory device 100), each of the semiconductor storage devices comprising: a first receive unit configured to receive the first toggle signal from the memory controller (FIG. 4A: integrated circuit device 400A including conductive node 454DQx); a first comparison circuit (FIG. 4A: input buffer 432DQx) having a first input terminal connected to the first receiving unit (FIG. 4A: first input 436DQx), a second terminal connected to a voltage generator generating a reference potential (FIG. 4A and para. [0041]: voltage node 460 is configured to receive a reference voltage such as Vrefq), and an output terminal, wherein the first comparison circuit is configured to generate and output a third toggle signal through its output terminal (FIG. 4A: output 440DQx), and wherein the third toggle signal switches based on a magnitude relationship of the first toggle signal relative to the reference potential (FIG. 3A and 3B demonstrate the output switching characteristic of the input buffers 432 relative to the reference voltage Vrefq); a first variable current source connected to the output terminal of the first comparison circuit and configured to provide a first current output (FIG. 4A and para. [0043]: calibration circuitry 434DQx is depicted with variable current sources; FIG. 5A: calibration circuitry 434A includes variable current source 555 connected to the node providing the output 440); a second receive unit configured to receive the second toggle signal (FIG. 4A: integrated circuit device 400A including conductive node 454DQx – see notes with respect to para. [0042] in the response to arguments above); a second comparison circuit (FIG. 4A: input buffer 432DQx) having a first input terminal connected to the second receive unit (FIG. 4A: first input 436DQx), a second input terminal connected to the voltage generator (FIG. 4A and para. [0041]: voltage node 460 is configured to receive a reference voltage such as Vrefq), and an output terminal, wherein the second comparison circuit is configured to generate and output a fourth toggle signal through its output terminal (FIG. 4A: output 440DQx), and wherein the fourth toggle signal switches based on a magnitude relationship of the second toggle signal relative to the reference potential (FIG. 3A and 3B demonstrate the output switching characteristic of the input buffers 432 relative to the reference voltage Vrefq); a second variable current source connected to the output terminal of the second comparison circuit and configured to provide a second current output (FIG. 4A and para. [0043]: calibration circuitry 434DQx is depicted with variable current sources; FIG. 5A: calibration circuitry 434A includes variable current source 555 connected to the node providing the output 440); and a sequencer configured to supply a first adjustment signal to the first variable current source so as to adjust the first current output and supply a second adjustment signal to the second variable current source so as to adjust the second current output ((FIG. 1: the command register 124, in conjunction with the calibration logic 126, form an equivalent structure as a sequencer and performs the same claimed function; FIG. 4A and para. [0043]: “The calibration logic 126 may be in communication with, and provide a control signal to, . . . the calibration circuitry 434DQx for each input buffer 432DQx.”).
Regarding claim 15, Tang discloses a method, comprising: receiving a first toggle signal (FIG. 4A: integrated circuit device 400A including conductive node 454DQx); generating and outputting a second toggle signal (FIG. 4A: input buffer 432DQx and output 440DQx), wherein the second toggle signal switches based on a magnitude relationship of the first toggle signal relative to a reference potential (FIG. 3A and para. [0036]: “The output 324 may represent the output voltage signal of the I/O buffer, transitioning at each crossing of the input 320 and Vrefq 322.”; FIG. 4A and para. [0041]: voltage node 460 that is configured to receive a reference voltage such as Vrefq); adjusting a first current output from a first current source based on a first adjustment signal (FIG. 4A and para. [0043]: “The calibration logic 126 may be in communication with, and provide a control signal to, . . . the calibration circuitry 434DQx for each input buffer 432DQx.”); receiving a third toggle signal (FIG. 4A: via conductive node 454DQx – see notes with respect to para. [0042] in the response to arguments above); generating and outputting a fourth toggle signal, wherein the fourth toggle signal switches based on a magnitude relationship of the third toggle signal relative to the reference potential (FIG. 3A and 3B); and adjusting a second current output from a second current source based on a second adjustment signal (FIG. 4A and para. [0043]: “The calibration logic 126 may be in communication with, and provide a control signal to, . . . the calibration circuitry 434DQx for each input buffer 432DQx.”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 5
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 10325659 B1; hereinafter "Tang") in view of Ok (US 20180130517 A1).
Regarding claims 6, Tang discloses the semiconductor storage device and adjusting the first and second current output from the first and second variable current sources based on the first and second adjustment signals, respectively, as set forth in the anticipation rejections of claims 1.
However, Tang does not teach an adjustment of the reference potential based on the first adjustment signal.
Ok, in the same field of endeavor, discloses an input buffer reference voltage control unit 101 (FIGs. 2 and 7) including a selection signal generation unit 710, an internal voltage generation unit 720 and a reference voltage output unit 730. Ok also discloses, “The input buffer reference voltage control unit 101 may set an internal voltage corresponding to reference voltage generation codes P0[n:0] inputted from the external controller (e.g. controller 200 of FIG. 1) as the input buffer reference voltage of the semiconductor memory device 100.” (See Ok at para. [0136]).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the memory system of Tang to include a reference voltage control unit, as taught by Ok to adjust the reference potential. One of ordinary skill in the art would have been motivated to make this modification for the benefit of adjusting the input buffer reference voltage to operate optimally according to lifetime, manufacturing processes, an operating voltage, changes in operating temperature, or other various factors of the semiconductor memory device (Ok at para. [0045]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827