Prosecution Insights
Last updated: April 19, 2026
Application No. 18/404,400

DEVICE FOR CONTROLLING TRAPPED IONS

Non-Final OA §102§103
Filed
Jan 04, 2024
Examiner
CHANG, HANWAY
Art Unit
2878
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies Austria AG
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
538 granted / 626 resolved
+17.9% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
65 currently pending
Career history
691
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
38.4%
-1.6% vs TC avg
§102
34.8%
-5.2% vs TC avg
§112
6.0%
-34.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 626 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 4, 7-8, 10, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bautista-Salvador et al. (US PGPub 2021/0233756, hereinafter Bautista). Regarding claim 1, Bautista discloses a micro-fabricated device for controlling trapped ions (a method for producing an atom trap, see abstract), the micro-fabricated device comprising: a first substrate having a main surface (substrate 1, see Fig. 1 paragraph [0091]; upon which the rest of the layers are built upon); a structured first metal layer disposed over the main surface of the first substrate, the structure first metal layer comprising electrodes of at least one ion trapping zone configured to trap an ion in a space above the structure first metal layer (starting layer 2 acts as a counter electrode, see paragraph [0095]; form multilayer atom trap 20, see paragraphs [0109-0110]); and a dielectric element fixedly attached to the first substrate (insulation layer 7 composed of a dielectric or a mix of different dielectrics, see paragraph [0031]; attached to the substrate 1, see paragraph [0101]); wherein the dielectric element comprises at least one laser light path and a surface covered with a layer (insulation layer 7 composed of a dielectric or a mix of different dielectrics, see paragraph [0031]; where a laser beam 25 is used to trap ions 24.1, see paragraph [0113]; insulation layer 7 covered by an additional starting layer 12, see paragraph [0106]), wherein the layer is arranged between the at least one laser light path and the at least one ion trapping zone (a laser beam 25 is used to trap ions 24.1, see paragraph [0113]; insulation layer 7 covered by an additional starting layer 12, see paragraph [0106]), and wherein the layer is an electrically conductive layer (additional starting layer 12 comprises additional electric conductor elements 14.1, see paragraph [0107]). Regarding claim 4, Bautista discloses the layer is formed by a metal layer (additional electrically conductive starting layer 12 (e.g. metal) is applied to the insulation layer 7, see paragraph [0106]). Regarding claim 7, Bautista discloses the layer is electrically grounded (multilayer conductor structure 23 (connected to additional electrically conductive starting layer 12) is grounded, see paragraph [0114]). Regarding claim 8, Bautista discloses the surface of the dielectric element is a side face of the dielectric element (insulation layer 7 composed of a dielectric or a mix of different dielectrics, see paragraph [0031]). Regarding claim 10, Bautista discloses a method of manufacturing a micro-fabricated device for controlling trapped ions (a method for producing an atom trap, see abstract), the method comprising: providing a first substrate having a main surface (substrate 1, see Fig. 1 paragraph [0091]; upon which the rest of the layers are built upon); forming a first metal layer over the main surface of the first substrate (starting layer 2 acts as a counter electrode, see Fig. 2 and paragraph [0095]); structuring the first metal layer to form electrodes of at least one ion trapping zone configured to trap an ion in a space above the structured first metal layer (starting layer 2 acts as a counter electrode, see paragraph [0095]; form multilayer atom trap 20, see paragraphs [0109-0110]); covering a surface of a dielectric element comprising at least one laser light path with a layer, wherein the layer is an electrically conductive layer (insulation layer 7 composed of a dielectric or a mix of different dielectrics, see paragraph [0031]; attached to the substrate 1, see paragraph [0101]; where a laser beam 25 is used to trap ions 24.1, see paragraph [0113]; insulation layer 7 covered by an additional starting layer 12, see paragraph [0106]); and bonding the dielectric element in a positionally fixed relationship to the first substrate such that the layer is arranged between the at least one laser light path and the at least one ion trapping zone (insulation layer 7 covered by an additional starting layer 12, see paragraph [0106]; a laser beam 25 is used to trap ions 24.1, see Fig. 5 and paragraph [0113]). Regarding claim 12, Bautista discloses the first substrate is a wafer and the bonding comprises wafer bonding of a structure dielectric wafer comprising a plurality of dielectric elements to the first substrate (substrate 1, see Fig. 1 paragraph [0091]; upon which the rest of the layers are built upon; insulation layer 7 composed of a dielectric or a mix of different dielectrics, see paragraph [0031]; attached to the substrate 1, see paragraph [0101]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2-3, 9, 11, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Bautista in view of Roessler et al. (US PGPub 2023/0009741, hereinafter Roessler). Regarding claim 2, Bautista discloses the dielectric element is made of at least one dielectric element (insulation layer 7 composed of a dielectric or a mix of different dielectrics, see paragraph [0031]). Bautista does not explicitly disclose the dielectric element comprises glass, quartz glass, alkali-free glass, borosilicate glass, or fused silica. Roessler discloses dielectric materials include glass (e.g. spacer 360 may be glass or any other dielectric material, see paragraph [0046]). Roessler teaches any dielectric material (e.g. glass) provides for low RF loss during operation (see paragraph [0046]). Roessler modifies Bautista by suggesting glass is a suitable dielectric material. Since both inventions are drawn atom traps, it would have been obvious to the ordinary artisan before the effective filing date to modify Bautista by using glass as a dielectric material for the purpose of reducing RF loss as taught by Roessler. Regarding claim 3, Bautista does not disclose the laser light path comprises a waveguide formed by an optical layer structure. Roessler discloses an optical duct 520 as an etched waveguide (horizontal optical duct may be formed by one or more horizontally etched openings, see paragraph [0063]; may be an optical waveguide, see paragraph [0064]). Roessler modifies Bautista by suggesting providing a waveguide for the laser light path. Since both inventions are drawn to atom traps, it would have been obvious to the ordinary artisan before the effective filing date to modify Bautista by providing a waveguide for the laser light path for the purpose of directing the laser light to the desired location for atom trapping as taught by Roessler. Regarding claim 9, Bautista does not disclose a second substrate spaced apart from the first substrate, wherein the at least one ion trapping zone is located in a space between the first substrate and second substrate, wherein the dielectric element forms a spacer structure between the first substrate and the second substrate. Roessler discloses a second substrate spaced apart from the first substrate (second substrate 140 disposed opposite the first substrate 120, see paragraph [0029]), where the ion trapping zone is located in a space between the substrates (ions 180 trapped in a processing zone PZ, see Fig. 3 and paragraph [0038]), where the dielectric element forms a spacer structure between the first and second substrates (spacer 360 defines the distance between the first and second substrates 120 and 140, see Fig. 3 and paragraph [0045]; spacer 360 made of dielectric material, see paragraph [0046]). Roessler modifies Bautista by providing a second substrate opposite the first substrate. Since both inventions are drawn to atom traps, it would have been obvious to the ordinary artisan before the effective filing date to modify Bautista by providing a second substrate opposite the first substrate for the purpose of having greater control over the formation of the atom trap made from the first and second substrates. Regarding claim 11, Bautista does not disclose forming the at least one light path by generating an optical layer structure in the dielectric element. Roessler discloses an optical duct 520 as an etched waveguide (horizontal optical duct may be formed by one or more horizontally etched openings, see paragraph [0063]; may be an optical waveguide, see paragraph [0064]). Roessler modifies Bautista by suggesting providing a waveguide for the laser light path. Since both inventions are drawn to atom traps, it would have been obvious to the ordinary artisan before the effective filing date to modify Bautista by providing a waveguide for the laser light path for the purpose of directing the laser light to the desired location for atom trapping as taught by Roessler. Regarding claim 13, Bautista does not disclose bonding a second substrate to the structured dielectric wafer, wherein the second substrate is spaced apart from the first substrate, wherein the at least one ion trapping zone is located in a space between the first substrate and the second substrate. Roessler discloses a second substrate spaced apart from the first substrate (second substrate 140 disposed opposite the first substrate 120, see paragraph [0029]), where the ion trapping zone is located in a space between the substrates (ions 180 trapped in a processing zone PZ, see Fig. 3 and paragraph [0038]), where the dielectric element forms a spacer structure between the first and second substrates (spacer 360 defines the distance between the first and second substrates 120 and 140, see Fig. 3 and paragraph [0045]; spacer 360 made of dielectric material, see paragraph [0046]). Roessler modifies Bautista by providing a second substrate opposite the first substrate. Since both inventions are drawn to atom traps, it would have been obvious to the ordinary artisan before the effective filing date to modify Bautista by providing a second substrate opposite the first substrate for the purpose of having greater control over the formation of the atom trap made from the first and second substrates. Regarding claim 14, Bautista does not disclose bonding of the second substrate comprises wafer bonding of the second substrate to the structure dielectric wafer, and wherein the plurality of dielectric elements of the structured dielectric wafer form a plurality of spacer structures which define the distance between the first substrate and second substrate. Roessler discloses a second substrate spaced apart from the first substrate (second substrate 140 disposed opposite the first substrate 120, see paragraph [0029]), where the ion trapping zone is located in a space between the substrates (ions 180 trapped in a processing zone PZ, see Fig. 3 and paragraph [0038]), where the dielectric element forms a spacer structure between the first and second substrates (spacer 360 defines the distance between the first and second substrates 120 and 140, see Fig. 3 and paragraph [0045]; spacer 360 made of dielectric material, see paragraph [0046]). Roessler modifies Bautista by providing a second substrate opposite the first substrate. Since both inventions are drawn to atom traps, it would have been obvious to the ordinary artisan before the effective filing date to modify Bautista by providing a second substrate opposite the first substrate for the purpose of having greater control over the formation of the atom trap made from the first and second substrates. Regarding claim 15, Bautista does not disclose dicing the wafer forming the first substrate and the structured dielectric to provide a plurality of micro-fabricated devices. Roessler teaches device singulation may be carried out at the wafer stack along common cutting lines CL (see Fig. 9a-c and paragraph [0090]). Roessler modifies Bautista by suggesting forming a plurality of devices on a wafer to perform singulation after the layers have been formed. Since both inventions are drawn to atom traps, it would have been obvious to the ordinary artisan before the effective filing date to modify Bautista by forming a plurality of devices on a wafer to perform singulation after the layers have been formed for the purpose of increasing throughput of forming the atom traps as taught by Roessler. Furthermore, it would have been obvious at the time of invention to a person of ordinary skill in the art since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bautista. Regarding claim 5, Bautista discloses the insulation layer 7 is preferably less than 250 nm (see Fig. 2(F) and paragraph [0038]). Bautista depicts the layer to be smaller than the insulation layer 7 (additional starting layer 12 is the layer, see Fig. 2(F)). Bautista does not explicitly disclose the layer has a layer thickness equal to or less than 200 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to choose an appropriate thickness of the additional starting layer 12, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Allowable Subject Matter Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 6, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including, the layer is optically transparent for laser light with a wavelength in a range from 200 nm to 2.5 μm. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HANWAY CHANG whose telephone number is (571)270-5766. The examiner can normally be reached Monday - Friday 7:30 AM - 4:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Georgia Epps can be reached at (571) 272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Hanway Chang /HC/ Examiner, Art Unit 2878 /GEORGIA Y EPPS/ Supervisory Patent Examiner, Art Unit 2878
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Prosecution Timeline

Jan 04, 2024
Application Filed
Mar 13, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+7.6%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 626 resolved cases by this examiner. Grant probability derived from career allow rate.

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