Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant' s arguments with respect to claims 2-7 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7 are rejected under 35 U.S.C. 103 as being unpatentable over Umezaki (US 2011/0193836) in view of Miyairi et al. (US 2010/0102313).
Regarding claim 2, Umezaki (figures 15B-19) discloses a display device comprising:
a pixel portion comprising a first pixel and a second pixel (connected to 112 and 114; figure 15B); and
a gate driver circuit (figures 15B-19) electrically connected to the pixel portion, wherein the first pixel and the second pixel are positioned in different rows,
wherein the gate driver circuit comprises a plurality of stages each comprises a unit (401_1 – 401_m, 402; figure 15B),
wherein the shift register unit in one stage is configured to output a signal to the first pixel and the second pixel,
wherein the shift register unit in one stage comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor (101 and 203),
wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the fifth transistor (203 and 226),
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor (203 and 205),
wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor (204 and 205),
wherein a gate of the third transistor is electrically connected to a first clock signal line (204 and 116; see at least paragraph 0102),
wherein a gate of the fourth transistor is electrically connected to a second clock signal line (205 and 117; see at least paragraph 0102),
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor (226 and 101),
wherein the shift register unit in the one stage has a first width in a direction where a signal line extends and a second width in a direction where a scan line extends.
Umezaki discloses the claimed invention except for wherein, when seen from above, the first width of the shift register unit in the one stage being larger than the second width of the shift register unit in the one stage. It would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width of the shift register unit in the one stage being larger than the second width of the shift register unit in the one stage, since it has been held that the configuration of the claimed width was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape of the opening was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The applicant has not provided any criticality for the first width of the shift register unit in the one stage being larger than the second width.
In addition, Miyairi et al. (figure 5) teaches wherein the shift register unit in the one each stage has a first width in a first direction where a signal line extends and a second width in a second direction where a scan line extends perpendicular to the first direction, and wherein, when seen from above, the first width of the shift register unit in the one stage is larger than the second width (351; see at least paragraphs 0108-0110). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the shift register unit as taught by Miyairi et al. in order to reduce an area occupied by the driver circuit and narrowing a frame.
Regarding claim 3, Umezaki (figures 15B-19) discloses wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon (see at least paragraph 0091).
Regarding claim 4, Umezaki (figures 15B-19) discloses wherein the shift register unit is in another stage next to the one stage electrically connected to a third clock signal line (101, 111, 115-117).
Regarding claim 5, Umezaki (figures 15B-19) discloses a display device comprising:
a pixel portion (connected to 112 and 114) comprising pixels arranged in a matrix in a row direction and a column direction; and
a gate driver circuit (figures 15B-19) electrically connected to the pixel portion,
wherein the gate driver circuit comprises a plurality of stages each comprises a unit (401_1 – 401_m, 402; figure 15B),
wherein the first unit is configured to output a signal to the first pixel and the second pixel,
wherein the first unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor (101 and 203),
wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the fifth transistor (203 and 226),
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor (203 and 205),
wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor (204 and 205),
wherein a gate of the third transistor is electrically connected to a first clock signal line (204 and 116; see at least paragraph 0102),
wherein a gate of the fourth transistor is electrically connected to a second clock signal line (205 and 117; see at least paragraph 0102),
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor (226 and 101),
wherein the shift register unit in the one stage has a first width in the column direction and a second width in a row direction, and
Umezaki discloses the claimed invention except for wherein, when seen from above, the first width of the shift register unit in the one stage being larger than the second width of the shift register unit in the one stage. It would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width of the shift register unit in the one stage being larger than the second width of the shift register unit in the one stage, since it has been held that the configuration of the claimed shape of the opening was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape of the opening was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The applicant has not provided any criticality for the first width of the shift register unit in the one stage being larger than the second width.
In addition, Miyairi et al. (figure 5) teaches wherein the shift register unit in the one each stage has a first width in a first direction where a signal line extends and a second width in a second direction where a scan line extends perpendicular to the first direction, and wherein, when seen from above, the first width of the shift register unit in the one stage is larger than the second width (351; see at least paragraphs 0108-0110). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the shift register unit as taught by Miyairi et al. in order to reduce an area occupied by the driver circuit and narrowing a frame.
Regarding claim 6, Umezaki (figures 15B-19) discloses wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon (see at least paragraph 0091).
Regarding claim 7, Umezaki (figures 15B-19) discloses wherein the shift register unit is in another stage next to the one stage electrically connected to a third clock signal line (101, 111, 115-117).
Claims 2, 4-5, 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otose (US 2010/0085294) in view of Miyairi et al..
Regarding claim 2, Otose (figures 2-5A) discloses a display device comprising:
a pixel portion comprising a first pixel and a second pixel (connected to OUT1/OUT2); and
a gate driver circuit (figure 5A) electrically connected to the pixel portion,
wherein the first pixel and the second pixel are positioned in different rows,
wherein the gate driver circuit comprises a plurality of stages each comprises a unit (shift registers as shown in figure 4 and see annotated drawing 1),
wherein unit in one stage is configured to output a signal to the first pixel and the second pixel,
wherein the in the one stage comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,
wherein one of a source and a drain of the first transistor (Tr8) is electrically connected to one of a source and a drain of the second transistor (Tr7),
wherein the other of the source and the drain of the second transistor (Tr7) is electrically connected to one of a source and a drain of the fifth transistor (Tr4),
wherein a gate of the second transistor (Tr7) is electrically connected to one of a source and a drain of the fourth transistor (Tr5; via other transistors and layers),
wherein one of a source and a drain of the third transistor (Tr2) is electrically connected to the other of the source and the drain of the fourth transistor (Tr5; via other transistors and layers),
wherein a gate of the third transistor is electrically connected to a first clock signal line (TR2 and REF; see at least paragraph 0084),
wherein a gate of the fourth transistor is electrically connected to a second clock signal line (Tr5 and DRV2; see at least paragraph 0084),
wherein the other of the source and the drain of the fifth transistor (Tr4) is electrically connected to one of a source and a drain of the sixth transistor (Tr1; via other transistors and layers),
wherein the shift register unit in the one stage has a first width in a direction where a signal line extends and a second width in a direction where a scan line extends.
Otose discloses the claimed invention except for wherein, when seen from above, the first width of the shift register unit in the one stage being larger than the second width of the shift register unit in the one stage. It would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width of the shift register unit in the one stage being larger than the second width of the shift register unit in the one stage, since it has been held that the configuration of the claimed shape of the opening was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape of the opening was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The applicant has not provided any criticality for the first width of the shift register unit in the one stage being larger than the second width.
In addition, Miyairi et al. (figure 5) teaches wherein the shift register unit in the one each stage has a first width in a first direction where a signal line extends and a second width in a second direction where a scan line extends perpendicular to the first direction, and wherein, when seen from above, the first width of the shift register unit in the one stage is larger than the second width (351; see at least paragraphs 0108-0110). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the shift register unit as taught by Miyairi et al. in order to reduce an area occupied by the driver circuit and narrowing a frame.
Regarding claim 4, Otose (figures 2-5A) discloses wherein the shift register unit in another stage next to the one stage is electrically connected to a third clock signal line (REF, DRV1, DRV2).
Regarding claim 5, Otose (figures 2-5A) discloses a display device comprising:
a pixel portion (connected to OUT1/OUT2) comprising pixels arranged in a matrix in a row direction and a column direction; and
a gate driver circuit (figure 5A) electrically connected to the pixel portion,
wherein the gate driver circuit comprises a plurality of stages each comprises a unit (shift registers as shown in figure 4 and see annotated drawing 1),
wherein the shift register unit in one stage is configured to output a signal to the first pixel and the second pixel,
wherein the first unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,
wherein one of a source and a drain of the first transistor (Tr8) is electrically connected to one of a source and a drain of the second transistor (Tr7),
wherein the other of the source and the drain of the second transistor (Tr7) is electrically connected to one of a source and a drain of the fifth transistor (Tr4),
wherein a gate of the second transistor (Tr7) is electrically connected to one of a source and a drain of the fourth transistor (Tr5; via other transistors and layers),
wherein one of a source and a drain of the third transistor (Tr2) is electrically connected to the other of the source and the drain of the fourth transistor (Tr5; via other transistors and layers),
wherein a gate of the third transistor is electrically connected to a first clock signal line (TR2 and REF; see at least paragraph 0084),
wherein a gate of the fourth transistor is electrically connected to a second clock signal line (Tr5 and DRV2; see at least paragraph 0084),
wherein the other of the source and the drain of the fifth transistor (Tr4) is electrically connected to one of a source and a drain of the sixth transistor (Tr1; via other transistors and layers),
wherein the shift register unit in the ones stage has a first width in the column direction and a second width in a row direction.
Otose discloses the claimed invention except for wherein, when seen from above, the first width of the shift register unit in the one stage being larger than the second width of the shift register unit in the one stage. It would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width of the shift register unit in the one stage being larger than the second width of the shift register unit in the one stage, since it has been held that the configuration of the claimed shape of the opening was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape of the opening was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The applicant has not provided any criticality for the first width of the shift register unit in the one stage being larger than the second width.
In addition, Miyairi et al. (figure 5) teaches wherein the shift register unit in the one each stage has a first width in a first direction where a signal line extends and a second width in a second direction where a scan line extends perpendicular to the first direction, and wherein, when seen from above, the first width of the shift register unit in the one stage is larger than the second width (351; see at least paragraphs 0108-0110). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the shift register unit as taught by Miyairi et al. in order to reduce an area occupied by the driver circuit and narrowing a frame.
Regarding claim 7, Otose (figures 2-5A) discloses wherein the shift register unit in another stage next to the one stage is electrically connected to a third clock signal line (REF, DRV1, DRV2).
Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Otose in view of Miyairi et al.; further in view of Chang et al. (US 2011/0316833).
Regarding claim 3, Otose discloses the limitations as shown in the rejection of claim 2 above. However, Otose is silent regarding wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon. Chang et al. teaches wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon (see at least paragraph 0043). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor layer as taught by Chang et al. in order to lower the manufacturing costs.
Regarding claim 6, Otose discloses the limitations as shown in the rejection of claim 5 above. However, Otose is silent regarding wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon. Chang et al. teaches wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon (see at least paragraph 0043). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor layer as taught by Chang et al. in order to lower the manufacturing costs.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAUREN NGUYEN whose telephone number is (571)270-1428. The examiner can normally be reached on Monday - Thursday, 8:00 AM -6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth, can be reached at 571-272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN NGUYEN/Primary Examiner, Art Unit 2871
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