Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/01/2025 has been entered.
Response to Amendment
Applicant’s arguments filed 10/01/2025 have been fully considered but they are not persuasive.
The applicant argues that none of the cited references teaches the limitations as amended in claims 2 and 5. The examiner respectfully disagrees. Umezaki discloses the claimed invention except for wherein, when seen from above, the first width of the unit in the one stage being larger than the second width of the unit in the one stage. It would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width of the unit in the one stage being larger than the second width of the unit in the one stage, since it has been held that the configuration of the claimed shape of the opening was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape of the opening was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The applicant has not provided any criticality for the first width of the unit in the one stage being larger than the second width.
In addition, Otose discloses the claimed invention except for wherein, when seen from above, the first width of the unit in the one stage being larger than the second width of the unit in the one stage. It would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width of the unit in the one stage being larger than the second width of the unit in the one stage, since it has been held that the configuration of the claimed shape of the opening was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape of the opening was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The applicant has not provided any criticality for the first width of the unit in the one stage being larger than the second width. The claim language therefore does not patentably distinguish over the applied reference[s], and the previous rejections are maintained.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the specific limitation “wherein the unit in the one stage has a first width in a direction where a signal line extends and a second width in a direction where a scan line extends, and wherein, when seen from above, the first width of the unit in the one stage is larger than the second width of the unit in the one stage” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specific limitation “wherein the gate driver circuit comprises a plurality of stages each comprises a unit and wherein the unit in the one stage has a first width in a direction where a signal line extends and a second width in a direction where a scan line extends, and wherein, when seen from above, the first width of the unit in the one stage is larger than the second width of the unit in the one stage” as represented in claims 2 and 5 are not supported by the originally filed application. As shown in figure 18B of the current application, the shift register SR appears to be the only unit in the driver circuit. The examiner is not sure which stage and unit are being referred to. For examining purposes, the examiner assumes any circuit can comprises of stages and units. Appropriate correction is required. Being depended on claims 2 and 5, claims 3-4 and 6-7 are also rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The specific limitation “wherein the unit in the one stage has a first width in a direction where a signal line extends and a second width in a direction where a scan line extends, and wherein, when seen from above, the first width of the unit in the one stage is larger than the second width of the unit in the one stage” as represented in claims 2 and 5 are unclear. As shown in figure 18B of the instant application, it is not clear which direction is the extension direction of the signal line and / or the scan line. Appropriate correction is required. Being depended on claims 2 and 5, claims 3-4 and 6-7 are also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7 are rejected under 35 U.S.C. 103 as being unpatentable over Umezaki (US 2011/0193836).
Regarding claim 2, Umezaki (figures 15B-19) discloses a display device comprising:
a pixel portion comprising a first pixel and a second pixel (connected to 112 and 114; figure 15B); and
a gate driver circuit (figures 15B-19) electrically connected to the pixel portion, wherein the first pixel and the second pixel are positioned in different rows,
wherein the gate driver circuit comprises a plurality of stages each comprises a unit (401_1 – 401_m, 402; figure 15B),
wherein the unit in one stage is configured to output a signal to the first pixel and the second pixel,
wherein the unit in one stage comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor (101 and 203),
wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the fifth transistor (203 and 226),
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor (203 and 205),
wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor (204 and 205),
wherein a gate of the third transistor is electrically connected to a first clock signal line (204 and 116; see at least paragraph 0102),
wherein a gate of the fourth transistor is electrically connected to a second clock signal line (205 and 117; see at least paragraph 0102),
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor (226 and 101),
wherein the unit in the one stage has a first width in a direction where a signal line extends and a second width in a direction where a scan line extends.
Umezaki discloses the claimed invention except for wherein, when seen from above, the first width of the unit in the one stage being larger than the second width of the unit in the one stage. It would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width of the unit in the one stage being larger than the second width of the unit in the one stage, since it has been held that the configuration of the claimed shape of the opening was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape of the opening was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The applicant has not provided any criticality for the first width of the unit in the one stage being larger than the second width.
Regarding claim 3, Umezaki (figures 15B-19) discloses wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon (see at least paragraph 0091).
Regarding claim 4, Umezaki (figures 15B-19) discloses wherein the unit is in another stage next to the one stage electrically connected to a third clock signal line (101, 111, 115-117).
Regarding claim 5, Umezaki (figures 15B-19) discloses a display device comprising:
a pixel portion (connected to 112 and 114) comprising pixels arranged in a matrix in a row direction and a column direction; and
a gate driver circuit (figures 15B-19) electrically connected to the pixel portion,
wherein the gate driver circuit comprises a plurality of stages each comprises a unit (401_1 – 401_m, 402; figure 15B),
wherein the first unit is configured to output a signal to the first pixel and the second pixel,
wherein the first unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor (101 and 203),
wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the fifth transistor (203 and 226),
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor (203 and 205),
wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor (204 and 205),
wherein a gate of the third transistor is electrically connected to a first clock signal line (204 and 116; see at least paragraph 0102),
wherein a gate of the fourth transistor is electrically connected to a second clock signal line (205 and 117; see at least paragraph 0102),
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor (226 and 101),
wherein the unit in the one stage has a first width in the column direction and a second width in a row direction, and
Umezaki discloses the claimed invention except for wherein, when seen from above, the first width of the unit in the one stage being larger than the second width of the unit in the one stage. It would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width of the unit in the one stage being larger than the second width of the unit in the one stage, since it has been held that the configuration of the claimed shape of the opening was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape of the opening was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The applicant has not provided any criticality for the first width of the unit in the one stage being larger than the second width.
Regarding claim 6, Umezaki (figures 15B-19) discloses wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon (see at least paragraph 0091).
Regarding claim 7, Umezaki (figures 15B-19) discloses wherein the unit is in another stage next to the one stage electrically connected to a third clock signal line (101, 111, 115-117).
Claims 2, 4-5, 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otose (US 2010/0085294).
Regarding claim 2, Otose (figures 2-5A) discloses a display device comprising:
a pixel portion comprising a first pixel and a second pixel (connected to OUT1/OUT2); and
a gate driver circuit (figure 5A) electrically connected to the pixel portion,
wherein the first pixel and the second pixel are positioned in different rows,
wherein the gate driver circuit comprises a plurality of stages each comprises a unit (shift registers as shown in figure 4 and see annotated drawing 1),
wherein unit in one stage is configured to output a signal to the first pixel and the second pixel,
wherein the in the one stage comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,
wherein one of a source and a drain of the first transistor (Tr8) is electrically connected to one of a source and a drain of the second transistor (Tr7),
wherein the other of the source and the drain of the second transistor (Tr7) is electrically connected to one of a source and a drain of the fifth transistor (Tr4),
wherein a gate of the second transistor (Tr7) is electrically connected to one of a source and a drain of the fourth transistor (Tr5; via other transistors and layers),
wherein one of a source and a drain of the third transistor (Tr2) is electrically connected to the other of the source and the drain of the fourth transistor (Tr5; via other transistors and layers),
wherein a gate of the third transistor is electrically connected to a first clock signal line (TR2 and REF; see at least paragraph 0084),
wherein a gate of the fourth transistor is electrically connected to a second clock signal line (Tr5 and DRV2; see at least paragraph 0084),
wherein the other of the source and the drain of the fifth transistor (Tr4) is electrically connected to one of a source and a drain of the sixth transistor (Tr1; via other transistors and layers),
wherein the unit in the one stage has a first width in a direction where a signal line extends and a second width in a direction where a scan line extends.
Otose discloses the claimed invention except for wherein, when seen from above, the first width of the unit in the one stage being larger than the second width of the unit in the one stage. It would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width of the unit in the one stage being larger than the second width of the unit in the one stage, since it has been held that the configuration of the claimed shape of the opening was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape of the opening was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The applicant has not provided any criticality for the first width of the unit in the one stage being larger than the second width.
Regarding claim 4, Otose (figures 2-5A) discloses wherein the unit in another stage next to the one stage is electrically connected to a third clock signal line (REF, DRV1, DRV2).
Regarding claim 5, Otose (figures 2-5A) discloses a display device comprising:
a pixel portion (connected to OUT1/OUT2) comprising pixels arranged in a matrix in a row direction and a column direction; and
a gate driver circuit (figure 5A) electrically connected to the pixel portion,
wherein the gate driver circuit comprises a plurality of stages each comprises a unit (shift registers as shown in figure 4 and see annotated drawing 1),
wherein the unit in one stage is configured to output a signal to the first pixel and the second pixel,
wherein the first unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,
wherein one of a source and a drain of the first transistor (Tr8) is electrically connected to one of a source and a drain of the second transistor (Tr7),
wherein the other of the source and the drain of the second transistor (Tr7) is electrically connected to one of a source and a drain of the fifth transistor (Tr4),
wherein a gate of the second transistor (Tr7) is electrically connected to one of a source and a drain of the fourth transistor (Tr5; via other transistors and layers),
wherein one of a source and a drain of the third transistor (Tr2) is electrically connected to the other of the source and the drain of the fourth transistor (Tr5; via other transistors and layers),
wherein a gate of the third transistor is electrically connected to a first clock signal line (TR2 and REF; see at least paragraph 0084),
wherein a gate of the fourth transistor is electrically connected to a second clock signal line (Tr5 and DRV2; see at least paragraph 0084),
wherein the other of the source and the drain of the fifth transistor (Tr4) is electrically connected to one of a source and a drain of the sixth transistor (Tr1; via other transistors and layers),
wherein the unit in the ones stage has a first width in the column direction and a second width in a row direction.
Otose discloses the claimed invention except for wherein, when seen from above, the first width of the unit in the one stage being larger than the second width of the unit in the one stage. It would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width of the unit in the one stage being larger than the second width of the unit in the one stage, since it has been held that the configuration of the claimed shape of the opening was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape of the opening was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The applicant has not provided any criticality for the first width of the unit in the one stage being larger than the second width.
Regarding claim 7, Otose (figures 2-5A) discloses wherein the unit in another stage next to the one stage is electrically connected to a third clock signal line (REF, DRV1, DRV2).
Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Otose (US 2010/0085294) in view of Chang et al. (US 2011/0316833).
Regarding claim 3, Otose discloses the limitations as shown in the rejection of claim 2 above. However, Otose is silent regarding wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon. Chang et al. teaches wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon (see at least paragraph 0043). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor layer as taught by Chang et al. in order to lower the manufacturing costs.
Regarding claim 6, Otose discloses the limitations as shown in the rejection of claim 5 above. However, Otose is silent regarding wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon. Chang et al. teaches wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a semiconductor layer comprising crystalline silicon (see at least paragraph 0043). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor layer as taught by Chang et al. in order to lower the manufacturing costs.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAUREN NGUYEN whose telephone number is (571)270-1428. The examiner can normally be reached on Monday - Thursday, 8:00 AM -6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth, can be reached at 571-272-97911. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN NGUYEN/Primary Examiner, Art Unit 2871