DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species 1 in the reply filed on 5/4/2026 is acknowledged. Claim 21-23 are understood as being withdrawn as being directed to an unelected species. Claims 1-20 are examined on the merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3, 5-11, and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20220122970 A1 to Do et al. (hereinafter “Do”).
Regarding claim 1, Do teaches an integrated circuit (figs. 21, 22 and 27) comprising:
a plurality of standard cells (plurality of cells in fig. 27) on a front surface (top surface) of a substrate (100; fig. 27) [0035];
a front wiring layer (layer M1; fig. 22) [0133] extending in a first direction (D2; fig. 27) [0045] on the front surface (top surface) of the substrate (100); and
a backside wiring layer (PDN; fig, 22) [0084] on a rear surface (bottom in at least fig. 22) of the substrate (100),
wherein a first standard cell (a first TC in fig. 27) of the plurality of standard cells (cells of TC in fig. 27) comprises:
a first gate line (electrodes GEd left having the same structure as gate electrode GE; fig. 21) [0090] and a second gate line (electrodes GEd right having the same structure as gate electrode GE; fig. 21) [0090] arranged apart from each other (separated) in the first direction (D2) to each extend in a second direction (D1; figs. 21 & 27) [0045] perpendicular to the first direction (D1); and
a plurality of power tap cells (TC; fig. 27 and 31) [0047] between (each cell comprising AC structures near their borders in the first direction) the first gate line (left GEd) and the second gate line (right GEd),
the plurality of power tap cells (TC) comprises a first power tap cell (any one of TC, hereinafter “TC1” in fig. 27) and a second power tap cell (any one of TC which is not TC1, hereinafter “TC2” in fig. 27) apart (separated) from the first power tap cell (TC1) by a first interval (first spacing) in the first direction (D2), and
each of the first power tap cell (TC1) and the second power tap cell (TC2) is configured to electrically connect (through via TV; fig. 22 among other figures) [0133] the backside wiring layer (PDN; see fig. 22) with the front wiring layer (M1).
It is noted that Do teaches multiple embodiments for the cell arrangement (compare figs. 26 and 27, for example), devices (compare figs. 30A and 30B for example), and tap cells (compare figs. 20 & 22 for example). The embodiments for cell arrangement and tap cells are considered to be compatible e.g., any tap cell embodiment may be arranged within to a cell arrangement embodiment. However, to clarify and simplify the rejection, the embodiments chosen to read on the claims are figs. 21, 22 and 27.
Regarding claim 2, Do teaches the integrated circuit of claim 1, wherein the front wiring layer (M1) comprises a first power rail (M1_R1 in TC1; see fig. 21) and a second power rail (M1_R2: see fig. 21) apart from each other in the second direction (D1), the backside wiring layer (PDN) comprises a first backside wiring pattern (lines LM1; fig. 22) [0085] and a second backside wiring pattern (line LM2; fig. 22) [0085], the first power tap cell (TC1) comprises a first via (TV1 of TC1; fig. 22) [0094] extending in a vertical direction (D3; fig. 22) between the first power rail (M1_R1 of TC1) and the first backside wiring pattern (PDN of TC1), and the second power tap cell (TC2) comprises a second via (TV1 of TC2) extending in the vertical direction (D3) between the second power rail (M1_R1 of TC2) and the second backside wiring pattern (PDN of TC2).
Regarding claim 3, Do teaches the integrated circuit of claim 1, wherein the front wiring layer (M1) comprises a first power rail (M1_R1 in TC1; see fig. 21) and a second power rail (M1_R2: see fig. 21) apart from each other in the second direction (D1), the backside wiring layer (PDN) comprises a first backside wiring pattern (lines LM1; fig. 22) [0085] and a second backside wiring pattern (line LM2; fig. 22) [0085], the first power tap cell (TC1) comprises a first via (TV1 of TC1; fig. 22) [0094] extending in a vertical direction (D3; fig. 22) between the first power rail (M1_R1 of TC1) and the first backside wiring pattern (PDN of TC1), extending in the vertical direction (D3) between the first power rail (M1_R1) and the first backside wiring pattern (LM1).
Regarding claim 5, Do teaches the integrated circuit of claim 1, wherein the plurality of power tap cells (plurality of TC in fig. 27) further comprise a third power tap cell (Third cell TC, hereinafter “TC3”) apart from the second power tap cell (TC2) by the first interval (spacing in fig. 27) in the first direction (D1).
Regarding claim 6, Do teaches the integrated circuit of claim 1, wherein the first power tap cell (TC1) is configured to transfer a positive supply voltage (source voltage VSS, present in M1_R2) [0035] from the backside wiring layer (PDN) to the front wiring layer (M1).
Regarding claim 7, Do teaches the integrated circuit of claim 1, wherein the first power tap cell (TC1) is configured to transfer a negative supply voltage (drain voltage VDD present in M1-R1) [0035] from the backside wiring layer (PDN) to the front wiring layer (M1).
Regarding claim 8, Do teaches the integrated circuit of claim 1, wherein a length of each of the plurality of power tap cells (plurality of TCs) in the second direction (D1) is equal to a length of the first standard cell (standard TC in fig. 27) in the second direction (D1).
Regarding claim 9, Do teaches the integrated circuit of claim 1, wherein the first power tap cell (TC1) is apart from a first cell boundary of the first standard cell (standard TC) in the first direction (D1), the second power tap cell (TC2) is apart from a second cell boundary of the first standard cell (standard TC) in the first direction (D1), and the first cell boundary is opposite to the second cell boundary in the first direction. It is noted that most cells are eligible to be the “standard” cell and TC1, TC2 can be chosen at positions to meet the limitations of claim 9 e.g., standard TC is chosen from the middle row of fig. 27 and TC1 and TC2 are chosen accordingly.
Regarding claim 10, Do teaches an integrated circuit (figs. 21, 22 and 27) comprising:
a plurality of standard cells (plurality of cells in fig. 27) on a substrate (100; fig. 27) [0035];
a front wiring layer (layer M1; fig. 22) [0133] extending in a first direction (D2; figs. 21 & 27) [0045] on a front surface (top surface) of the substrate (100); and
a backside wiring layer (PDN; fig, 22) [0084] on a rear surface (bottom in at least fig. 22) of the substrate (100),
wherein a first standard cell (any of cells in fig. 27 which includes a TC) of the plurality of standard cells (cells of fig. 27) comprises:
a first gate line (electrodes GEd left having the same structure as gate electrode GE; fig. 21) [0090] and a second gate line (electrodes GEd right having the same structure as gate electrode GE; fig. 21) [0090] arranged apart from each other (separated) in the first direction (D2) to each extend in a second direction (D1; figs. 21 & 27) [0045] perpendicular to the first direction (D1); and
a power tap cell (TC; fig. 27 and 31) [0047] between the first gate line (left GEd) and the second gate line (right GEd), the power tap cell (TC) including at least one via (through via TV; fig. 22) [0094] electrically connecting (making electrical contact) the backside wiring layer (PDN) with the front wiring layer (M1).
It is noted that Do teaches multiple embodiments for the cell arrangement (compare figs. 26 and 27, for example), devices (compare figs. 30A and 30B for example), and tap cells (compare figs. 20 & 22 for example). The embodiments for cell arrangement and tap cells are considered to be compatible e.g., any tap cell embodiment may be arranged according to a cell arrangement embodiment. However, to clarify and simplify the rejection, the embodiments chosen to read on the claims are figs. 21, 22 and 27.
Regarding claim 11, Do teaches the integrated circuit of claim 10, wherein the front wiring layer (M1) comprises a first power rail (M1_R1) overlapping a first cell boundary (boundary of M1_R1; see fig. 27 for cell boundaries, the rails comprising the cell borders) of the first standard cell (standard TC), the backside wiring layer (PDN) comprises a first backside wiring pattern (line LM1; fig. 22) [0085], the at least one via (TV) comprises a first via (TV1; fig. 22) overlapping the first power rail (M1_R1) and extending in a vertical direction (D3) between the first backside wiring pattern (LM1) and the first power rail (M1_R1), and the first cell boundary (boundaries of fig. 27) extends in the first direction (D2).
Regarding claim 13, Do teaches the integrated circuit of claim 11, wherein the first via (TV1) is configured to transfer a positive supply voltage (source voltage VSS, present in M1_R2) [0035] from the first backside wiring (LM1) pattern to the first power rail (M1_R1). It is noted that the voltage flowing through M1_R2 may change as the device operates, allowing for Do to read on claim 13.
Regarding claim 14, Do teaches the integrated circuit of claim 11, wherein the first via (TC1) is configured to transfer a negative supply voltage (drain voltage VDD present in M1-R1) [0035] from the first backside wiring layer (LM1) to the front power rail (M1_R1).
Regarding claim 15, Do teaches the integrated circuit of claim 10, wherein a length of the power tap cell (TC) in the second direction (D1) is equal to a length of the first standard cell (standard TC in fig. 27) in the second direction (D1).
Regarding claim 16, Do teaches the integrated circuit of claim 10, wherein the power tap cell (TC) is apart from a first cell boundary of the first standard cell (standard TC) in the first direction (D1) and is apart from a second cell boundary of the first standard cell (standard TC) in the first direction (D1), and the first cell boundary is opposite to the second cell boundary in the first direction. It is noted that most cells are eligible to be the “standard” cell and TC1 and TC2 can be chosen at positions to meet the limitations of claim 9 e.g., standard TC is chosen from the middle row of fig. 27 and TC1 and TC2 are chosen accordingly.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4, 12, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Do in view of Do of a separate embodiment.
Regarding claim 4, Do teaches the integrated circuit of claim 1, wherein the front wiring layer (M1) comprises a first power rail (M1_R1 in TC1; see fig. 21) and a second power rail (M1_R2: see fig. 21) apart from each other in the second direction (D1), the backside wiring layer (PDN) comprises a first backside wiring pattern (lines LM1; fig. 22) [0085] and a second backside wiring pattern (line LM2; fig. 22) [0085], the first power tap cell (TC1) comprises: a first via (TV1 of TC1; fig. 22) [0094] extending in a vertical direction (D3; fig. 22) between the first power rail (M1_R1 of TC1) and the first backside wiring pattern (PDN of TC1);
Do, in the embodiment of figs. 21, 22, and 27, does not teach a second via extending in the vertical direction between the second power rail and the second backside wiring pattern, and the second power tap cell comprises: a third via extending in the vertical direction between the first power rail and the first backside wiring pattern; and a fourth via extending in the vertical direction between the second power rail and the second backside wiring pattern. Do teaches a single via in this embodiment.
However, Do teaches, in the embodiment of fig.10, figs. 7-8B showing exemplary cross-sections of a single through via structure [0013]-[0016], a second via (TV2; fig. 10) [0110] extending in the vertical direction (D3; reference fig. 8A) between the second power rail (M1_R2) and the second backside wiring pattern (LM2), and the second power tap cell (TC2) comprises: a third via (TV1 of TC2; fig. 10) extending in the vertical direction (D3) between the first power rail (M1_R1) and the first backside wiring pattern (LM1); and a fourth via (TV2 of TC2) extending in the vertical direction (D3) between the second power rail (M1_R2) and the second backside wiring pattern (LM2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the cells of Do to comprise two vias each, the vias being connected to the power rails, to increase circuit density i.e., each cell having double the vias.
Regarding claim 12, Do teaches the integrated circuit of claim 11, wherein the front wiring layer (M1) further comprises a second power rail (M1_R2; figs. 22 and 27) [0035] overlapping a second cell boundary (boundary created by M1_R2) of the first standard cell (standard TC), the backside wiring layer (PDN) comprises a second backside wiring pattern (line LM2; fig. 22) [0085], the second cell boundary (boundary of M1_R2) extends in the first direction (D2) and is opposite to the first cell boundary (boundary of M1_R1).
Do, in the embodiment of figs. 21, 22, and 27, does not teach the at least one via further comprises a second via overlapping the second power rail and extending in the vertical direction between the second backside wiring pattern and the second power rail, and
However, Do teaches, in the embodiment of fig.10, figs. 7-8B showing exemplary cross-sections of a single through via structure [0013]-[0016], a second via (TV2; fig. 10) [0110] overlapping the second power rail (M1_R2) and extending in the vertical direction (D3) between the second backside wiring pattern (LM2) and the second power rail (M1_R2), and
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the cells of Do to comprise two vias each, the vias being connected to the power rails, to increase circuit density i.e., each cell having double the vias.
Regarding claim 17, Do teaches an integrated circuit (figs. 21, 22 and 27) comprising:
a plurality of standard cells (plurality of cells in fig. 27) on a front surface (top surface) of a substrate (100; fig. 27) [0035];
a front wiring layer (layer of M1; fig. 22) [0133] including a front wiring pattern (pad M1_P; fig. 22) [0133] arranged apart from one another (separated) in a second direction (D1; fig. 27) [0045] perpendicular to a first direction (D2; fig. 27) [0045] to each extend in the first direction (D2) on the front surface (top) of the substrate (100);
a backside wiring layer (PDN; fig, 22) [0084] on a rear surface (lower surface; fig. 22) of the substrate (100); and
a plurality of first inline power tap cells (cells in fig. 27 which includes a TC) arranged in one row (see fig. 27) in the second direction (D1) to electrically connect (comprise electrical contact; see fig. 22) the backside wiring layer (PDN) with the front wiring layer (M1),
wherein a first standard cell (any of cells in fig. 27 which includes a TC) of the plurality of standard cells (cells of fig. 27) comprises:
a first gate line (electrodes GEd left having the same structure as gate electrode GE; fig. 21) [0090] and a second gate line (electrodes GEd right having the same structure as gate electrode GE; fig. 21) [0090] arranged apart from each other (separated) in the first direction (D2) to each extend in a second direction (D1; figs. 21 & 27)
a first power tap cell (TC; fig. 27 and 31) [0047] between the first gate line (left GEd) and the second gate line (right GEd) to electrically connect (comprise electrical contact) the backside wiring layer (PDN) with the front wiring layer (M1), and
the first power tap cell (any of TC) is aligned with the plurality of first inline power tap cells (cells of fig. 27).
It is noted that Do teaches multiple embodiments for the cell arrangement (compare figs. 26 and 27, for example), devices (compare figs. 30A and 30B for example), and tap cells (compare figs. 20 & 22 for example). The embodiments for cell arrangement and tap cells are considered to be compatible e.g., any tap cell embodiment may be arranged according to a cell arrangement embodiment. However, to clarify and simplify the rejection, the embodiments chosen to read on the claims are figs. 21, 22 and 27.
Do, in the embodiment of figs. 21, 22, and 27, does not teach a plurality of front wiring patterns.
However, Do teaches, in the embodiment of fig.10, figs. 7-8B showing exemplary cross-sections of a single through via structure [0013]-[0016], a plurality of front wiring layers (expanded portions EXP 1 and EXP2; fig. 10) [0092].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the cells of Do to comprise two front side wiring patterns, to increase circuit density i.e., each cell having double the front side wiring.
Regarding claim 18, Do teaches the integrated circuit of claim 17, wherein a second standard cell (second standard TC; fig. 27) of the plurality of standard cells (plurality of TC) comprises a second power tap cell (second TC cell, hereinafter “TC2”; fig. 27) configured to electrically connect the backside wiring layer (PDN) with the front wiring layer (M1), and the second power tap cell (TC2) is not aligned with the plurality of first inline power tap cells (see fig. 27 showing inline cells and other rows of cells).
Regarding claim 19, Do teaches the integrated circuit of claim 18, further comprising a plurality of second inline power tap cells (at least two TCs) arranged in one row in the second direction (D1) and disposed apart from the plurality of first inline power tap cells (first inline TCs) in the first direction (D2) to electrically connect the backside wiring layer (PDN) with the front wiring layer (M1), wherein the second power tap cell (TC in center row) is between the plurality of first inline power tap cells (first inline TCs, see fig. 27) and the plurality of second inline power tap cells (second inline TCs, see fig. 27).
Regarding claim 20, Do teaches the integrated circuit of claim 19, wherein the second standard cell (TC in center row) further comprises a third power tap cell (third TC in same row as first inline TCs) configured to electrically connect the backside wiring layer (PDN) with the front wiring layer (M1), and the third power tap cell (third TC) is aligned with the plurality of first inline power tap cells (first inline TCs).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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