Prosecution Insights
Last updated: July 17, 2026
Application No. 18/404,538

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Jan 04, 2024
Priority
Feb 20, 2023 — JP 2023-024212
Examiner
SEVEN, EVREN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
542 granted / 733 resolved
+5.9% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
36 currently pending
Career history
768
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
82.2%
+42.2% vs TC avg
§102
6.7%
-33.3% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 733 resolved cases

Office Action

§103 §112
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 9 rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Specifically, “a cooler” is introduced a second time and it is unclear if the previously introduced cooler is recalled. It is assumed to be the same cooler. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1- are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20160276245 to Murai et al. (Murai). Regarding Claim 1, Murai teaches in Fig. 11 at least, a semiconductor device comprising: a heat dissipation surface (surface of 32 facing down on page) to which a cooler 40G is attached; and a heat dissipation surface wire 49 bonded to at least one location in the heat dissipation surface, but does not explicitly teach that an amount of protrusion of the heat dissipation surface wire from the heat dissipation surface is 10 um or more and 200 um or less. However, Murai does teach that the height of the wires directly affects the standoff [0094] and is therefore a result effective variable that may be optimized by the person of ordinary skill. Regarding Claim 2, Murai teaches the semiconductor device according to claim 1, wherein the heat dissipation surface wires are provided at one or more locations within a region overlapping with a semiconductor chip the semiconductor device includes [0094]. Regarding Claim 3, Murai teaches the semiconductor device according to claim 1, wherein the heat dissipation surface wires are provided at one or more locations on each of both sides of a median line drawn in a longitudinal direction of the heat dissipation surface (see Fig. 11). Regarding Claim 4, Murai teaches the semiconductor device according to claim 1, further comprising a TIM 64 being a thermal interface material provided on the heat dissipation surface. Regarding Claim 7, Murai teaches the semiconductor device according to claim 4, wherein the TIM is a heat dissipation sheet having slits at locations corresponding to locations of the heat dissipation surface wires (see Fig. 11). Regarding Claim 9, Murai teaches the semiconductor device according to claim 4, further comprising a cooler attached to the heat dissipation surface via the heat dissipation surface wires and the TIM (see Fig. 11). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Murai as applied to claim 4 above, and further in view of U.S. Pat. Pub. No. 20240258190 to Hefai-Ahmed et al. (Refai). Regarding Claim 5, Murai teaches the semiconductor device according to claim 4, but does not explicitly teach that the TIM is a PC-TIM being a phase change thermal interface material. However, in analogous art, Refai teaches that a TIM may be a PCTIM [0030]. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Refai since Refai teaches that TIM and PCTIM are interchangeable (MPEP 2144.06-07). Allowable Subject Matter Claims 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the cited prior art does not teach that a thickness of the PC-TIM is greater than an amount of protrusion of the heat dissipation surface wire from the heat dissipation surface or that a thickness of the heat dissipation sheet is greater than an amount of protrusion of the heat dissipation surface wire from the heat dissipation surface in context with the remainder of the superseding claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVREN SEVEN/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jan 04, 2024
Application Filed
May 18, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684789
SEMICONDUCTOR DEVICE INCLUDING ACTIVE DIODE AREA
2y 8m to grant Granted Jul 14, 2026
Patent 12684765
SEMICONDUCTOR DEVICE
2y 8m to grant Granted Jul 14, 2026
Patent 12666712
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
3y 1m to grant Granted Jun 23, 2026
Patent 12666838
Light Emitting Display Device
2y 6m to grant Granted Jun 23, 2026
Patent 12666971
HIGH-FREQUENCY SEMICONDUCTOR PACKAGE
2y 7m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
82%
With Interview (+8.6%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 733 resolved cases by this examiner. Grant probability derived from career allowance rate.

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