Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-11, 13-14, and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suh et al. (US20170110507A1, hereinafter Suh).
Regarding claim 1, Suh discloses a semiconductor device comprising:
a first structure including a first impurity region (Fig. 26A source region 9s), a second impurity region (Fig. 26A drain region 9d), and an isolation region (Fig. 26A gate capping pattern 21c);
a second structure on the first structure, the second structure including a contact opening penetrating therethrough and exposing the first impurity region (Fig. 26A cell interconnecting structure 48c within contact opening above source region 9s);
a pattern structure including a contact portion connected to the first impurity region in the contact opening, and a line portion on the contact portion and the second structure (Fig. 26A cell interconnecting structure 48c comprises lower pattern 36c in contact with source region 9s and bit line structure 96 is on cell interconnecting structure 48c); and
a spacer structure between a side surface of the contact opening and the contact portion,
wherein the spacer structure includes,
a first spacer layer on the side surface of the contact opening (Fig. 26A insulating liner 55 on side surface of the opening in which cell interconnecting structure 48c is disposed), and
a second spacer layer between the first spacer layer and the contact portion (Fig. 26A interconnecting spacers 51c disposed between insulating liner 55 and cell interconnection structure 48c),
wherein a lower end of the second spacer layer is at a higher level than a lower surface of the contact portion (Fig. 26A the lower end of interconnecting spacer 51c is at a higher level than a lower surface of lower pattern 36c), and
wherein the contact portion includes,
a first contact region connected to the first impurity region, and
a first extension portion protruding from the first contact region and extending between the lower surface of the second spacer layer and a bottom surface of the contact opening (Fig. 26A lower pattern 36c is connected to source region 9c and comprises a portion that protrudes from the central region of lower pattern 36c to extend between the lower surface of interconnecting spacer 51c and gate capping pattern 21c).
Regarding claim 4, Suh discloses the semiconductor device of claim 1, wherein
the first structure further includes a gate structure, the gate structure including
a gate electrode extending in a first horizontal direction (Fig. 26A gate electrode 18c),
a gate capping pattern on the gate electrode (Fig. 26A gate capping pattern 21c), and
a gate dielectric layer covering a side surface of the gate electrode and a side surface of the gate capping pattern (Fig. 26A gate dielectric layer 16 covers side surface of gate electrode 18c and gate capping pattern 21c),
the first impurity region is adjacent to the gate capping pattern (Fig. 26A source region 9s is adjacent to gate capping pattern 21c), and
a portion of the gate dielectric layer is between the first impurity region and the gate capping pattern (Fig. 26A at least a portion of gate dielectric layer 16 is between source region 9s and gate capping pattern 21c).
Regarding claim 5, Suh discloses the semiconductor device of claim 4, wherein
the gate capping pattern includes,
a first capping region vertically overlapping the contact portion (Fig. 26A gate capping pattern 21c vertically overlap the extension portion of lower pattern 36c), and
a second capping region vertically overlapping the second structure (Fig. 26A interlayer insulating layer 94 vertically overlaps cell interconnection structures 48c),
an upper surface of the second capping region of the gate capping pattern is at a higher level than an upper surface of the first capping region of the gate capping pattern (Fig. 26A upper surface of interlayer insulating layer 94 is at a higher level than an upper surface of the gate capping pattern 21c), and
the contact portion covers an upper surface of the first impurity region and an upper surface of the first capping region of the gate capping pattern (Fig. 26A lower pattern 36c covers upper surface of source region 9s and a portion of gate capping pattern 21c).
Regarding claim 6, Suh discloses the semiconductor device of claim 4, wherein
the contact portion further includes a second extension portion extending between the first impurity region and the gate capping pattern and being in contact with the gate dielectric layer (Fig. 26A the extension portion of lower pattern 36c extends between source region 9s and gate capping pattern 21c).
Regarding claim 7, Suh discloses the semiconductor device of claim 1, wherein
the isolation region includes,
a first isolation region vertically overlapping the contact portion (Fig. 26A gate capping pattern 21c vertically overlap the extension portion of lower pattern 36c), and
a second isolation region vertically overlapping the second structure (Fig. 26A interlayer insulating layer 94 vertically overlaps cell interconnection structures 48c),
an upper surface of the second isolation region is at a higher level than an upper surface of the first isolation region (Fig. 26A upper surface of interlayer insulating layer 94 is at a higher level than an upper surface of the gate capping pattern 21c), and
the contact portion covers an upper surface of the first impurity region and an upper surface of the first isolation region (Fig. 26A lower pattern 36c covers upper surface of source region 9s and at least a portion of gate capping pattern 21c).
Regarding claim 8, Suh discloses the semiconductor device of claim 7, wherein
the upper surface of the first isolation region and the upper surface of the first impurity region are coplanar with each other (Fig. 26A upper surface of gate capping pattern 21c is coplanar with the upper surface of source region 9s).
Regarding claim 9, Suh discloses the semiconductor device of claim 7, wherein
the contact portion covers the upper surface of the first impurity region and an upper region of a side surface of the first impurity region (Fig. 26A lower pattern 36c covers the upper surface of source region 9s and the upper surface region of a side surface of source region 9s as lower pattern overlaps the horizontal edges of source region 9s).
Regarding claim 10, Suh discloses the semiconductor device of claim 1, wherein
the second structure includes,
a pad pattern connected to the second impurity region (Fig. 26A lower contact patterns 374 connected to drain region 9d),
an insulating isolation pattern on a side surface of the pad pattern (Fig. 26A isolation pattern 363 on a side surface of lower contact patterns 374), and
an insulating buffer pattern on the pad pattern and the insulating isolation pattern (Fig. 26A cell barrier patterns 82c disposed on pad pattern 374 and isolation pattern 363), and
the pad pattern includes at least one conductive layer (Examiner notes that a contact pattern such as contact pattern 374 would include at least a conductive layer in order to provide contact).
Regarding claim 11, Suh discloses the semiconductor device of claim 10, wherein
the pattern structure further includes an insulating capping pattern on the line portion (Fig. 26A/26B interlayer insulating layer 94 on bit line 96),
the pattern structure includes,
a doped silicon layer connected to the first impurity region(Fig. 26A cell contact silicide layer 80c connected to source region 9c), and
at least one conductive layer on the doped silicon layer (Fig. 26A upper contact pattern 84c disposed on cell contact silicide layer 80c), and
the doped silicon layer and the at least one conductive layer of the pattern structure are included in the contact portion and the line portion (Fig. 26A cell contact silicide layer 80c and upper contact pattern 85c both comprise the cell contact structure 86c and are in contact with bit line 96).
Regarding claim 13, Suh discloses a semiconductor device comprising:
a first structure including a first impurity region (Fig. 26A source region 9s), a second impurity region (Fig. 26A drain region 9d), and an isolation region (Fig. 26A gate capping pattern 21c);
a second structure including a pad pattern connected to the second impurity region (Fig. 26A lower contact patterns 374 connected to drain region 9d), an insulating isolation pattern having a side surface in contact with a side surface of the pad pattern (Fig. 26A isolation pattern 363 on a side surface of lower contact patterns 374), and an insulating buffer pattern on the pad pattern and the insulating isolation pattern (Fig. 26A cell barrier patterns 82c disposed on pad pattern 374 and isolation pattern 363), the second structure including a contact opening penetrating therethrough and exposing an upper surface of the first impurity region and a first portion of the isolation region (Fig. 26A cell interconnecting structure 48c within contact opening is above source region 9s);
a pattern structure including a contact portion in the contact opening and a line portion on the contact portion and the second structure (Fig. 26A cell interconnecting structure 48c comprises lower pattern 36c in contact with source region 9s and bit line structure 96 is on cell interconnecting structure 48c);
a contact spacer structure between a side boundary of the contact opening defined by the second structure and the contact portion (Fig. 26A buffer insulating layer 24); and
a contact structure connected to an upper surface of the pad pattern (Fig. 26A cell interconnecting structure 48c), the contact structure extending upwardly, wherein the contact spacer structure includes,
a first spacer layer on the side boundary of the contact opening (Fig. 26A insulating liner 55 on side surface of the opening in which cell interconnecting structure 48c is disposed), and
a second spacer layer between the first spacer layer and the contact portion (Fig. 26A interconnecting spacers 51c disposed between insulating liner 55 and cell interconnection structure 48c),
wherein the second spacer layer has a first side surface in contact with the first spacer layer and a second side surface opposing the first side surface (Fig. 26A interconnecting spacer 51c has a left surface opposing the side surface of the opening in which cell interconnect 48c is disposed and interconnecting spacer 51c also has a right surface opposing its left surface),
wherein a lower end of the second spacer layer is at a higher level than a lower end of the first spacer layer (Fig. 26A the lower end of insulating liner 55 is at a higher level than a lower surface of interconnection spacers 51c), and
wherein a lower end of the second side surface of the second spacer layer does not vertically overlap the first spacer layer (Fig. 26A the lower end of the second side surface of interconnection spacer 51c does not vertically overlap insulating liner 55).
Regarding claim 14, Suh discloses the semiconductor device of claim 13, wherein
the contact spacer structure has a ring shape in plan view (Fig. 26A interconnection spacer 51c surrounds cell interconnection structures 48c and has a plan view as can be seen from fig. 4).
Regarding claim 16, Suh discloses the semiconductor device of claim 13, wherein
the pad pattern covers the second impurity region and a second portion of the isolation region, adjacent to the second impurity region (Fig. 26A lower contact patterns 374 covers drain region 9d and a portion of gate gapping pattern 21c),
the isolation region includes,
a first isolation region vertically overlapping the contact portion (Fig. 26A gate capping pattern 21c vertically overlap the extension portion of lower pattern 36c), and
a second isolation region vertically overlapping the pad pattern (Fig. 26A interlayer insulating layer 94 vertically overlaps cell interconnection structures 48c),
an upper surface of the second isolation region is at a higher level than an upper surface of the first isolation region (Fig. 26A upper surface of interlayer insulating layer 94 is at a higher level than an upper surface of the gate capping pattern 21c),
wherein the contact spacer structure includes:
a first spacer region not vertically overlapping the line portion (Fig. 26A insulating liner 55 on side surface of the opening in which cell interconnecting structure 48c is disposed); and
a second spacer region vertically overlapping the line portion, wherein the first spacer region is in contact with a side surface of the pad pattern and a portion of a side surface of the isolation region below the pad pattern, and wherein the second spacer region is in contact with a side surface of the insulating isolation pattern and a side surface of the insulating buffer pattern (Fig. 26A isolation pattern 363 on a side surface of lower contact patterns 374).
Regarding claim 17, Suh discloses a semiconductor device comprising:
a first structure (Fig. 26A substrate 3);
a second structure on the first structure, the second structure including a contact opening penetrating therethrough (Fig. 26A contact opening above source region 9s in which cell interconnecting structure 48c is disposed);
a pattern structure including a contact portion in the contact opening, and a line portion on the contact portion and the second structure (Fig. 26A cell interconnecting structure 48c comprises lower pattern 36c in contact with source region 9s and bit line structure 96 is on cell interconnecting structure 48c); and
a contact spacer structure between a side boundary of the contact opening defined by the second structure and the contact portion (Fig. 26A buffer insulating layer 24),
wherein the first structure includes,
a substrate (Fig. 26A substrate 3),
a first active region and a second active region on the substrate (Fig. 26A portions of substrate below source region 9s and drain region 9d),
an isolation region on side surfaces of the first and second active regions (Fig. 26A gate capping pattern 21c),
a first impurity region in an upper region of the first active region (Fig. 26A source region 9s) and a second impurity region in an upper region of the second active region (Fig. 26A drain region 9d),
a gate trench traversing the first and second active regions and extending into the isolation region (Fig. 26A cell gate trenches 12c), and
a gate structure in the gate trench (Fig. 26A gate electrode 18c represents the gate structure),
wherein the gate structure includes
a gate dielectric layer covering an inner wall of the gate trench (Fig. 26A gate dielectric layer 16 covers side surface of gate electrode 18c and gate capping pattern 21c),
a gate electrode partially filling the gate trench on the gate dielectric layer (Fig. 26A gate electrode 18c); and
a gate capping pattern on the gate electrode in the gate trench (Fig. 26A gate capping pattern 21c),
wherein the gate electrode has a linear shape extending in a first horizontal direction,
wherein the line portion has a linear shape extending in a second horizontal direction, perpendicular to the first horizontal direction (Fig. 26A bit line 29 and gate electrode 18c extend perpendicularly from each other as represented by fig. 4),
wherein the second structure includes,
a pad pattern connected to the second active region (Fig. 26A lower contact patterns 374 connected to drain region 9d),
an insulating isolation pattern in contact with side surfaces of the pad pattern (Fig. 26A isolation pattern 363 on a side surface of lower contact patterns 374), and
an insulating buffer pattern on the pad pattern and the insulating isolation pattern (Fig. 26A cell barrier patterns 82c disposed on pad pattern 374 and isolation pattern 363),
wherein the contact opening exposes the first impurity region, the isolation region adjacent to the first impurity region, and the gate capping pattern adjacent to the first impurity region (Fig. 26A the opening in which cell interconnection structure 48 is disposed exposes source region 9s, gate capping layer 21c, and gate dielectric 16),
wherein the contact spacer structure includes a first spacer layer on the side boundary of the contact opening (Fig. 26A insulating liner 55 on side surface of the opening in which cell interconnecting structure 48c is disposed) and a second spacer layer between the first spacer layer and the contact portion (Fig. 26A interconnecting spacers 51c disposed between insulating liner 55 and cell interconnection structure 48c),
wherein a material of the first spacer layer is different from a material of the second spacer layer (Par. 156 teaches that “[t]he interconnection spacers 51 c and the peripheral gate spacers 51 p may be formed of…silicon oxide” and par. 157 teaches that “[t]he insulating liner 55 may be formed of or include an insulating material such as, for example, a silicon nitride”) and ,
wherein a lower end of the first spacer layer is at a lower level than a lower end of the second spacer layer (Fig. 26A the lower end of insulating liner 55 is at a higher level than a lower surface of interconnection spacers 51c), and
wherein each of the first and second spacer layers has a ring shape in plan view (Fig. 26A interconnection spacer 51c surrounds cell interconnection structures 48c and has a plan view as can be seen from fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Suh (US20170110507A1).
Regarding claim 2, Suh teaches the semiconductor device of claim 1, wherein
the second spacer layer has a first side surface opposing the side surface of the contact opening and a second side surface opposing the first side surface (Fig. 26A interconnecting spacer 51c has a left surface opposing the side surface of the opening in which cell interconnect 48c is disposed and interconnecting spacer 51c also has a right surface opposing its left surface),
the first side surface of the second spacer layer is in contact with the first spacer layer (Fig. 26A left surface of interconnecting spacer 51c is in contact with insulating liner 55), and
the contact portion is in contact with the second side surface of the second spacer layer and the lower surface of the second spacer layer (Fig. 26A lower pattern 36c is in contact with right surface of interconnecting spacer 51c and extends under interconnecting spacer 51c. While Suh does not explicitly disclose the extension portion of lower pattern 36c contacting the lower surface of insulating liner 55, the primary function of the combination of the insulating pattern and contact region is to provide electrical contact with the source region below. A rearrangement of the extension portion of lower pattern 36c to contacting the lower surface of insulating liner 55 would not provide any new or unexpected results as the primary function of providing electrical contact with the source region below is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange the extension portion of lower pattern 36c to contact the lower surface of insulating liner 55, see MPEP 2144.04(VI)(B)).
Regarding claim 3, Suh teaches the semiconductor device of claim 1, wherein
the second spacer layer has a first side surface opposing the side surface of the contact opening and a second side surface opposing the first side surface (Fig. 26A interconnecting spacer 51c has a left surface opposing the side surface of the opening in which cell interconnect 48c is disposed and interconnecting spacer 51c also has a right surface opposing its left surface),
the contact portion is in contact with the second side surface of the second spacer layer and the lower surface of the second spacer layer (Fig. 26A lower pattern 36c is in contact with right surface of interconnecting spacer 51c and extends under interconnecting spacer 51c. While Suh does not explicitly disclose the extension portion of lower pattern 36c contacting the lower surface of insulating liner 55, the primary function of the combination of the insulating pattern and contact region is to provide electrical contact with the source region below. A rearrangement of the extension portion of lower pattern 36c to contacting the lower surface of insulating liner 55 would not provide any new or unexpected results as the primary function of providing electrical contact with the source region below is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange the extension portion of lower pattern 36c to contact the lower surface of insulating liner 55, see MPEP 2144.04(VI)(B)), and
the first extension portion extends in a direction toward the side surface of the contact opening to vertically overlap at least a portion of the first spacer layer (Fig. 26A lower pattern 36c extends in a direction towards the opening containing cell interconnection structure 48c. While Suh does not explicitly disclose the extension portion of lower pattern 36c vertically overlapping at least a portion of insulating liner 55, the primary function of the combination of the insulating pattern and contact region is to provide electrical contact with the source region below. A rearrangement of lower pattern 36c to vertically overlap at least a portion of insulating liner 55 would not provide any new or unexpected results as the primary function of providing electrical contact with the source region below is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange lower pattern 36c to vertically overlap at least a portion of insulating liner 55, see MPEP 2144.04(VI)(B)).
Regarding claim 15, Suh teaches the semiconductor device of claim 13, wherein
a thickness of the first spacer layer is greater than a thickness of the second spacer layer (While Suh does not explicitly disclose the thickness of insulating liner 55 being greater than the thickness of interconnection spacer 51, the primary function of the insulating liners 51c/55 is to provide electrical isolation to cell interconnection structure 48c. A change in size of the insulating liners 51c/55 such that the thickness of insulating liner 55 is greater than the thickness of interconnection spacer 51 would not provide any new or unexpected results as the primary function of providing electrical isolation to cell interconnection structure 48c is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore change the size of insulating liners 51c/55 such that the thickness of insulating liner 55 is greater than the thickness of interconnection spacer 51, see MPEP 2144.04(VI)(A)).
Allowable Subject Matter
Claims 12 and 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 12. The closest prior art (US20170110507A1, US9379004B1) teaches the semiconductor device of claim 10, further comprising:
a line spacer on a side surface of the line portion (Fig. 26A interlayer insulating layer 94 on side surface of bit line 96);
a contact spacer structure below the line spacer and on at least a portion of a side surface of the contact portion in the contact opening (Fig. 26A buffer insulation layer 24);
a contact structure electrically connected to the pad pattern (Fig. 26A cell contact structures 86c electrically connected to lower contact patterns 76); and
a data storage structure on the contact structure and electrically connected to the contact structure (Fig. 26A data storage elements 92 on cell contact structure 86c).
However, the closest prior art does not teach in combination with the other claimed elements wherein
the contact structure includes a pad portion vertically overlapping at least a portion of an upper surface of the pattern structure and on a level higher than that of the upper surface of the pattern structure.
Regarding claim 18, the closest prior art (US20170110507A1, US9379004B1)) teaches the semiconductor device of claim 17.
However, the closest prior art does not teach in combination with the other claimed elements
wherein in a cross-sectional structure in which the contact portion and the line portion are cut in the first horizontal direction, the contact spacer structure is in contact with both a side surface of the pad pattern and a side surface of the contact portion that is between the pad pattern and the contact portion.
Regarding claim 19, the closest prior art (US20170110507A1, US9379004B1)) teaches the semiconductor device of claim 17.
However, the closest prior art does not teach in combination with the other claimed elements
wherein in a cross-sectional structure in which the contact portion and the line portion are cut in the second horizontal direction, the contact spacer structure is in contact with both a side surface of the second structure and a side surface of the contact portion, and the side surface of the second structure is a side surface of the insulating isolation pattern and a side surface of the insulating buffer pattern.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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