DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5, 12-14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mahvash et al. US 2024/0060914 A1 (“Mahvash”) in view of Shi et al. US 2023/0417682 A1 (“Shi”).
As to claim 1, Mahvash discloses an apparatus for predicting a structure of a semiconductor device, the apparatus comprising:
a storage configured to store a learned model configured to predict the structure of the semiconductor device (Mahwash Figure 1 or Paragraph 131 – e.g., use of a computer, Paragraphs 69-72 – e.g., use of trained ML to predict parameters);
a memory configured to store at least one code (Mahwash Figure 1 or Paragraph 131 – e.g., use of a computer), and
at least one processor operatively connected to the memory (Mahwash Figure 1 or Paragraph 131 – e.g., use of a computer) and configured to execute the at least one code to:
input non-destructive metrology data measured from the semiconductor device into the learned model (Mahwash Paragraphs 38-39 or 68-74 – e.g., x-ray scatterometry and/or metrology system), and
predict the structure of the semiconductor device, based on the learned model, wherein the learned model is trained with training data including first data which is non-destructive metrology data and second data which is structural metrology data as reference data of the first data (Mahwash Paragraphs 69-74 – e.g., use of trained ML to predict parameters, in combination with Shi, see below), and
wherein the training data is refined based on a similarity of the training data in a space having a first axis corresponding to the first data and a second axis corresponding to the second data as reference axes (Mahwash Paragraphs 69-74 – e.g., use of trained ML, in combination with Shi, see below).
Mahwash discloses many elements of claim 1, including the use of a trained ML model to predict circuit parameters. Mahwash does not provide specific details on how the model is trained. However, the missing element is well known in the art because while teaching the use of machine learning in circuit fabrication, Shi discloses using metrology data and reference data in order to train a machine learning model (Shi Paragraphs 22 or 50), including training in order to have ML outputs follow expected values. This is equivalent to trying to achieve similarity between measured and reference results. It would have been obvious to one having ordinary skill in the art at the time the invention was made to train the ML as in Shi, because doing so would result in a more accurate ML model and predictions.
As to claim 2, Mahwash and Shi disclose the apparatus of claim 1. Mahwash and Shi further disclose wherein the first data is metrology data of the semiconductor device based on spectrum (Mahwash Paragraphs 38-39 or 68-74 – e.g., necessary in x-ray scatterometry and/or metrology system), and the second data is structure data obtained by measuring at least a part of the structure of the semiconductor device (Shi Paragraphs 22 or 50 -e.g., structure parameters).
Claims 3, 5, and 13 recite elements similar to claims 1 or 2, and are rejected for the same reasons.
As to claim 4, Mahwash and Shi disclose the method of claim 3. Mahwash and Shi further disclose wherein the first axis is scaled within a range of the second data. Shi discloses training in order to have ML outputs follow expected values (Shi Paragraphs 22 or 50). It would have been obvious to one having ordinary skill in the art at the time the invention was made for the first and second axis to have similar ranges/scales because the ML model is trained to follow each other.
As to claim 12, Mahwash and Shi disclose the method of claim 3. Mahwash and Shi further disclose wherein the similarity is based on at least one of cosine similarity, a correlation coefficient, and a linear regression model evaluation method based on a residual of the training data in the first space (Shi Paragraphs 22 or 50 – e.g., training in order to have ML outputs follow expected values). It would have been obvious to one having ordinary skill in the art at the time the invention was made to use one or more of a correlation coefficient or linear regression model because those were both common ways of evaluating how correlated two sets of data are.
Claims 14 and 20 recite elements similar to claims 4 and 12, and are rejected for the same reasons.
Allowable Subject Matter
Claims 6-11 and 15-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest a method or apparatus for predicting a semiconductor structure having the combination of steps/elements of the claims including, among other elements, the search and refinement details of the claims, in combination with the analysis and prediction elements of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571)272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRYCE M AISAKA/Primary Examiner, Art Unit 2851
Prosecution Insights