Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
With regards to the applicants arguments filed on 08/03/2026, a new rejection is formulated below upon a new reference, thus the arguments are not pertinent to the current rejection. Additionally, the language surrounding “approximate horizontal span” has overcome the 112(b) rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20110089575).
Lee teahces
[claim 1] A semiconductor device assembly, comprising: a substrate; a first semiconductor die above the substrate and comprising: an edge; a second semiconductor die in a stacked arrangement above the first semiconductor die and comprising: an overhang portion extending beyond the edge ( figure 2C, paragraph 0078, where element 201 is the substrate, element 202 is the first semiconductor die, and element 203 is the second semiconductor die, where the first semiconductor die has an edge [right side edge], and the second semiconductor die is stacked over the first such that there is an overhand portion [as shown by element 216 in the place of the overhang portion], which is situated beyond the edge),
and a legged support structure, comprising a first leg and a second leg, between the overhang portion and the substrate and comprising: an approximately horizontal span traversing a path that is approximately parallel to the substrate, approximately orthogonal to the second semiconductor die, and directly below the overhang portion (figure 2C, paragraph 0076, where element 216 is the legged support structure and comprises a first leg [left-hand side leg that attaches to element 214 as labeled] and a second leg which is the right-hand side leg of element 216 which attaches to the unlabeled element 214, it spans a horizontal path that is parallel to the substrate [element 201] and orthogonal to the second die [figure 3A shows the legged structure extends in the z-direction whereas the second semiconductor die extends in the x-direction, which are approximately orthogonal to each other),
wherein the first leg and the second leg are spaced from each other on a same axis as the approximately horizontal span (figures 2A and 3A, paragraph 0076, where element 216 [legged structure made up of first and second leg] are spaced apart from each other in the z-direction which is the axis of the horizontal span and parallel to the substrate [element 201]).
[claim 20] A semiconductor device assembly, comprising: a substrate; a first semiconductor die above the substrate and comprising: an edge; a second semiconductor die in a stacked arrangement above the first semiconductor die and comprising: an overhang portion extending beyond the edge ( figure 2C, paragraph 0078, where element 201 is the substrate, element 202 is the first semiconductor die, and element 203 is the second semiconductor die, where the first semiconductor die has an edge [right side edge], and the second semiconductor die is stacked over the first such that there is an overhand portion [as shown by element 216 in the place of the overhang portion], which is situated beyond the edge);
and a support structure, comprising a first leg and a second leg, between the overhang portion and the substrate and including a profile comprising: an approximately horizontal span that is approximately parallel to the substrate, approximately orthogonal to the second semiconductor die, and directly below the overhang portion (figure 2C, paragraph 0076, where element 216 is the legged support structure and comprises a first leg [left-hand side leg that attaches to element 214 as labeled] and a second leg which is the right-hand side leg of element 216 which attaches to the unlabeled element 214, it spans a horizontal path that is parallel to the substrate [element 201] and orthogonal to the second die [figure 3A shows the legged structure extends in the z-direction whereas the second semiconductor die extends in the x-direction, which are approximately orthogonal to each other),
wherein the first leg and the second leg are spaced from each other on a same axis as the approximately horizontal span; and radially curved portions between the first leg and the second leg (figure 2C, paragraph 0076, where element 216 is the legged support structure with first and second legs that are separated from each other on the same axis [as seen clearly in figure 3A], where the span comprises a radially curved portion between the two legs [element 216 is curved]).
[claim 21] herein the first leg and the second leg extend from the radially curved portions to bond pads below the overhang portion (figure 2C, paragraph 0074, where the radially curved portion of element 216 extends into both the first and second leg as shown connected to pads in figure 2C).
Claim(s) 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon et al (US 20130277831).
Yoon et al teaches
[claim 13] A semiconductor device assembly, comprising: a substrate; a first semiconductor die, in a first stack of dies, above the substrate and comprising: a first edge (figure 3, paragraph 0044, where element 200A is the first semiconductor die stacked above the substrate [element 100] and has a first edge [left-hand side edge of the element]),
a second semiconductor die, in a second stack of dies, above the substrate, proximate to the first semiconductor die, and comprising: a second edge that is approximately parallel to the first edge and separated from the first edge (figure 3, paragraph 0044, where element 200B is the second semiconductor die and is above the substrate [element 100] and is proximate to the first die [element 200A] with a second edge [left-hand side vertical edge] which is approximately parallel to the first edge),
a third semiconductor die in a stacked arrangement above the first semiconductor die in the first stack of dies and comprising: a first overhang portion extending beyond the first edge (figure 3, paragraph 0044, where element 200C is the third semiconductor die stacked above the first [element 200A] and coprises a first overhand portion [portion underneath element 200C on the left-hand side not covered by element 200A or 200B]),
a fourth semiconductor die in a stacked arrangement above the second semiconductor die in the second stack of dies and comprising: a second overhang portion extending beyond the second edge (figure 3, paragraph 0044, where element 200D is the fourth semiconductor die, and a second overhand portion is situated underneath element 200D and no under elements 200A-C);
and a legged support structure, comprising a first leg and a second leg, between the first semiconductor die and the second semiconductor die and comprising: wherein a first portion the first leg is directly under the first overhang portion and configured to support the first overhang portion, and a second portion he second leg is directly under the second overhang portion and configured to support the second overhang portion (figure 3, paragraphs 0044 and 0068, where element 300 is the legged support structure and has a portion situated between the first and second semiconductor die in a diagonal direction, where the first leg [element above element 130C] is situated under the first overhand portion and supports the first overhand portion, and the second leg [element 340 above element 130D] is the second leg and supports the second overhand portion – note the interpretation of the “legged support structure” is simply a support structure that contains leg like features).
[claim 14] The semiconductor device assembly of claim 13, wherein at least one of the first semiconductor die, the second semiconductor die, the third semiconductor die, or fourth semiconductor die comprises: a NAND memory device (figure 3, paragraph 0056, where at least one of the die [elements 200A-D] comprises a NAND memory device such as a flash memory chip [often NOR or NAND in nature]).
[claim 15] The semiconductor device assembly of claim 13, wherein at least one of the first semiconductor die, the second semiconductor die, the third semiconductor die, or the fourth semiconductor die comprises: a dynamic random access memory device (figure 3, paragraph 0056, where at least one of the die [elements 200A-D] comprises a DRAM device).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-6 and 11-12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20110089575) in view of Yoo et al (US 20190067248).
Lee teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 2] The semiconductor device assembly of claim 1, wherein the second semiconductor die comprises: an adhesive layer on an underside surface of the overhang portion.
[claim 3] The semiconductor device assembly of claim 2, wherein the approximately horizontal span and the adhesive layer are in contact.
[claim 4] The semiconductor device assembly of claim 1, wherein the approximately horizontal span comprises: a cross section having an approximately trapezoidal shape.
[claim 5] The semiconductor device assembly of claim 1, wherein the approximately horizontal span comprises: a cross section having at least one approximately linear edge.
[claim 6] The semiconductor device assembly of claim 1, wherein the approximately horizontal span comprises: a cross section having at least one curved edge.
[claim 7] The semiconductor device assembly of claim 1, wherein the substrate comprises: a bond pad, and wherein a leg of the legged support structure is bonded to the bond pad.
[claim 11] The semiconductor device assembly of claim 1, wherein a cross-section of the approximately horizontal span comprises: a width that is included in a range of approximately 30 microns to approximately 38 microns.
[claim 12] The semiconductor device assembly of claim 1, wherein the first semiconductor die comprises: a first memory device, and wherein the second semiconductor die comprises: a second memory device.
However, Yoo et al does teach
[claim 2] The semiconductor device assembly of claim 1, wherein the second semiconductor die comprises: an adhesive layer on an underside surface of the overhang portion (figure 3A, paragraph 0039, where element 344 is an adhesive material on the underside surface of the overhand portion of element 320 [defined as the portion of 320 from the edge of the right-hand side of element 310 to the right-hand side of element 320]).
[claim 3] The semiconductor device assembly of claim 2, wherein the approximately horizontal span and the adhesive layer are in contact (figure 3A, where the horizontal span is in the plane into the page and also vertical on the page, the one-dimensional span being a distance cannot be “in contact” with anything, but the span does present itself at the bottom of the adhesive layer).
[claim 4] The semiconductor device assembly of claim 1, wherein the approximately horizontal span comprises: a cross section having an approximately trapezoidal shape (figure 3A, paragraph 0039, where the horizontal span in the plane into the page is a one-dimensional measurement, thus it is approximately trapezoidal in said dimensional space – that is a trapezoid in one-dimension is a line in one direction).
[claim 5] The semiconductor device assembly of claim 1, wherein the approximately horizontal span comprises: a cross section having at least one approximately linear edge (figure 3A, paragraph 0039, where the horizontal span going into the page is a linear edge as it is one-dimensional distance – thus linear).
[claim 6] The semiconductor device assembly of claim 1, wherein the approximately horizontal span comprises: a cross section having at least one curved edge (figure 3A, paragraph 0039, where the cross-sectional area of a one-dimensional measurement is a one-dimensional measurement in one direction – thus a curved edge would also collapse to a single line in one-dimension, thus the span into the page in one-dimension maps onto a one-dimensional projection of a curved edge in two dimensions).
[claim 7] The semiconductor device assembly of claim 1, wherein the substrate comprises: a bond pad, and wherein a leg of the legged support structure is bonded to the bond pad (figure 3A, paragraph 0042, where element 334 is the bonding pad on the substrate [element 330] and the legged support structure [element 306] is bonded to the pad).
[claim 11] The semiconductor device assembly of claim 1, wherein a cross-section of the approximately horizontal span comprises: a width that is included in a range of approximately 30 microns to approximately 38 microns (figure 1A, paragraph 0027, where element D has a thickness less than 50 micrometers, where element D is as thick as element 106, where the vertical projection of element 106 is a cross-section of the approximately horizontal span can range approximately between 30 and 38 microns).
[claim 12] The semiconductor device assembly of claim 1, wherein the first semiconductor die comprises: a first memory device, and wherein the second semiconductor die comprises: a second memory device (figure 3A, paragraph 0012, where element 310 [first die] and element 320 [second die] can both be memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee to incorporate the teachings of Yoo et al in order to bond the die together with the support structure to create a more physically stable device, improving physical durability.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20110089575), Yoo et al (US 20190067248) and in view of Chiu et al (US 20100044861).
Lee as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 8] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a wire loop structure.
However, Chiu et al teaches
[claim 8] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a wire loop structure (paragraph 0052, figure 14, where element 360 is part of the support structure and is in the shape of a balcony loop).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee as modified to incorporate the teachings of Chiu et al to use a wire loop structure instead of a rigid structure to distribute the load more efficiently to allow for greater structural stability.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20110089575), Yoo et al (US 20190067248) and in view of Dogiamis et al (US 20210398922).
Lee as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 9] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a copper material.
However, Dogiamis et al teaches
[claim 9] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a copper material (paragraph 0077, where the support structure [element 450] is made of copper).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee as modified with the teachings of Dogiamis to use a thermally conductive materially to help dissipate the thermal load from the die and thus promote greater efficiency of the device.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20110089575), Yoo et al (US 20190067248) and in view of Oi et al (US 20080142944).
Lee as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 10] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a material having a modulus of elasticity that is included in a range of approximately 115 gigapascal to approximately 130 gigapascal.
However, Oi et al does teach
[claim 10] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a material having a modulus of elasticity that is included in a range of approximately 115 gigapascal to approximately 130 gigapascal (paragraph 0050, where elastically-deformable pillar like structures are in place of the structural supports of Yoo et al, and have a modulus of elasticity between 100 and 230 gigapascals which lies within the range of 115 and 130 gigapascals).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee as modified with the teachings of Oi et al in order to provide a spring like structure that allows for some movement but still remain sturdy, compared to a rigid structure that could break easily with a stress force, to provide maximal structural stability.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al (US 20130277831) in view of Wang et al (US 20230361048).
Yoon et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 16] The semiconductor device assembly of claim 13, wherein at least one of the first semiconductor die, the second semiconductor die, the third semiconductor die, or the fourth semiconductor die has a thickness that is included in a range of approximately 40 microns to approximately 50 microns.
However, Wang et al does teach
[claim 16] The semiconductor device assembly of claim 13, wherein at least one of the first semiconductor die, the second semiconductor die, the third semiconductor die, or the fourth semiconductor die has a thickness that is included in a range of approximately 40 microns to approximately 50 microns (paragraph 0047, where the memory die can have various ranges, of which fall in the range of 40 to 50 micron).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yoon et al to incorporate the teachings of Wang et al in order to maximize space by keeping the memory die at a minimal thickness to preserve performance but optimize spatial density.
Claim(s) 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al (US 20130277831) in view of Fay et al (US 20220084977).
Yoon et al teaches all of the limitations of the parent claim, claim 13, and further discloses
[claim 17] The semiconductor device assembly of claim 13, further comprising: a fifth semiconductor die below an approximately horizontal span of the legged support structure.
[claim 19] The semiconductor device assembly of claim 17, wherein the fifth semiconductor die comprises: a controller device.
However, Fay et al does teach
[claim 17] The semiconductor device assembly of claim 13, further comprising: a fifth semiconductor die below an approximately horizontal span of the legged support structure (figure 1C, paragraph 0015, where element 102 is the fifth semiconductor die which is situated below a horizontal span of the support structure as read from Cui et al [the horizontal span is the area under the second semiconductor die from the substrate when reading Fay et al onto Cui et al]).
[claim 19] The semiconductor device assembly of claim 17, wherein the fifth semiconductor die comprises: a controller device (paragraph 0015, where element 102 is the fifth semiconductor die that is a controller device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yoon et al to incorporate the teachings of Fay et al in order to have a fifth semiconductor die to control the memory die to optimize performance while optimizing spatial density by situating the device beneath the horizontal span.
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al (US 20130277831) and Fay et al (US 20220084977) in view of Keeth et al (US 20190121560)
Yoon et al as modified teaches all of the limitations of the parent claim, claim 1, and Yoon et al further teaches,
[claim 18] and wherein a leg of the legged support structure is connected to the bond pad (figure 3, paragraph 0050, where element 130 [A-D] is the bond pad and the legged support structure [element 300] is connected to said pads).
However, Yoon et al does not specifically teach
[claim 18] wherein the substrate comprises: a bond pad between the fifth semiconductor die and the first semiconductor die
However, Keeth et al does teach
[claim 18] wherein the substrate comprises: a bond pad between the fifth semiconductor die and the first semiconductor die (figure 6A, paragraph 0065 where element 605 is the fifth semiconductor and also has electrical contacts connected to the substrate, when put onto Cui et al signifies that the first semiconductor die [as shown in Keeth et al, element 720 on the bottom of the right-hand side stack of die] is also connected to the fifth semiconductor die).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yoon et al to incorporate the teachings of Keeth et al in order to electrical connect the semiconductor die together through the substrate and with the support legged structure to form a functioning device.
Claim(s) 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20110089575) in view of Chong et al (US 20220336417).
Lee as modified teaches all of the limitations of the parent claim, claim 20, but does not specifically disclose
[claim 22] The semiconductor device assembly of claim 20, wherein the substrate comprises: a thermal via structure, and wherein a legged support structure of the support structure connects to the thermal via structure
However, Chong et al does teach
[claim 22] The semiconductor device assembly of claim 20, wherein the substrate comprises: a thermal via structure, and wherein a legged support structure of the support structure connects to the thermal via structure (paragraph 0036, where the device can have attached to it, namely through the substrate, a head sink or some thermal coupler to help dissipate the heat. When read onto Cui et al, where the support structure is attached to the substrate, naturally the legged support structure would also be attached to said thermal dissipation structure that is attached to the substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee as modified with the teachings of Chong et al in order to dissipate heat from the device to allow for maximal efficiency of operation by keeping temperature regulated.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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