Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-22 in the reply filed on April 8, 2026 is acknowledged. Claims 23-35 are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “approximately horizontal span” in claims 1, 3, 4, 5, 6, 11, 17, and 20 is used by the claim to mean “two-dimensional shape in a plan where the horizontal direction is one of the basis vectors for said plane” while the accepted meaning is “a one-dimensional line/direction in a two-dimensional space.” The term is indefinite because the specification does not clearly redefine the term.
Please note that every two-dimensional shape needs to be able to be spanned by two basis vectors that are orthogonal to each other, thus it is physically and mathematically impossible to have a “horizontal span” considering the horizontal direction is only one direction, a second direction needs to be identified to create a two-dimensional shape. The examiner takes the present meaning to mean a single direction, and thus a horizontal span cannot have a trapezoid shape (similar to a circle cannot be a square, a one-dimensional line cannot take on a two-dimensional shape), but rather the horizontal span can extend in one direction [span] and can only take up one-dimension, not two. Additionally, the term “approximately” as a modifier to “horizontal” renders the term even more ambiguous, as approximate without any qualifier of measurement
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoo et al (US 20190067248).
[claim 1] A semiconductor device assembly, comprising: a substrate (figure 3A, paragraph 0043, element 330 is the substrate),
a first semiconductor above the substrate and comprising: an edge (figure 3A, paragraph 0043, where element 310 is the first semiconductor above the substrate and contain an edge, in the present case the right-hand side edge);
a second semiconductor die in a stacked arrangement above the first semiconductor die and comprising: an overhang portion extending beyond the edge (figure 3A, paragraph 0043, where element 320 is the second semiconductor die and is in a stacked arrangement over the first die [element 310] where an overhand portion extends beyond the edge [not portion of element 320 from the right-hand side edge of element 310 to the right-hand side of element 320]);
and a legged support structure between the overhang portion and the substrate and comprising: an approximately horizontal span traversing a path that is approximately parallel to the edge and directly below the overhang portion (figure 3A, paragraph 0039, where element 306 is the legged support structure between the overhand portion of element 320 and the substrate [element 330], where the horizontal span traverses a path that is parallel to the edge in a direction into the page [defined as the horizontal direction]).
[claim 2] The semiconductor device assembly of claim 1, wherein the second semiconductor die comprises: an adhesive layer on an underside surface of the overhang portion (figure 3A, paragraph 0039, where element 344 is an adhesive material on the underside surface of the overhand portion of element 320 [defined as the portion of 320 from the edge of the right-hand side of element 310 to the right-hand side of element 320]).
[claim 3] The semiconductor device assembly of claim 2, wherein the approximately horizontal span and the adhesive layer are in contact (figure 3A, where the horizontal span is in the plane into the page and also vertical on the page, the one-dimensional span being a distance cannot be “in contact” with anything, but the span does present itself at the bottom of the adhesive layer).
[claim 4] The semiconductor device assembly of claim 1, wherein the approximately horizontal span comprises: a cross section having an approximately trapezoidal shape (figure 3A, paragraph 0039, where the horizontal span in the plane into the page is a one-dimensional measurement, thus it is approximately trapezoidal in said dimensional space – that is a trapezoid in one-dimension is a line in one direction).
[claim 5] The semiconductor device assembly of claim 1, wherein the approximately horizontal span comprises: a cross section having at least one approximately linear edge (figure 3A, paragraph 0039, where the horizontal span going into the page is a linear edge as it is one-dimensional distance – thus linear).
[claim 6] The semiconductor device assembly of claim 1, wherein the approximately horizontal span comprises: a cross section having at least one curved edge (figure 3A, paragraph 0039, where the cross-sectional area of a one-dimensional measurement is a one-dimensional measurement in one direction – thus a curved edge would also collapse to a single line in one-dimension, thus the span into the page in one-dimension maps onto a one-dimensional projection of a curved edge in two dimensions).
[claim 7] The semiconductor device assembly of claim 1, wherein the substrate comprises: a bond pad, and wherein a leg of the legged support structure is bonded to the bond pad (figure 3A, paragraph 0042, where element 334 is the bonding pad on the substrate [element 330] and the legged support structure [element 306] is bonded to the pad).
[claim 11] The semiconductor device assembly of claim 1, wherein a cross-section of the approximately horizontal span comprises: a width that is included in a range of approximately 30 microns to approximately 38 microns (figure 1A, paragraph 0027, where element D has a thickness less than 50 micrometers, where element D is as thick as element 106, where the vertical projection of element 106 is a cross-section of the approximately horizontal span can range approximately between 30 and 38 microns).
[claim 12] The semiconductor device assembly of claim 1, wherein the first semiconductor die comprises: a first memory device, and wherein the second semiconductor die comprises: a second memory device (figure 3A, paragraph 0012, where element 310 [first die] and element 320 [second die] can both be memory devices).
Claim(s) 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cui et al (US 20210407967).
[claim 13] A semiconductor device assembly, comprising: a substrate (figure 10, paragraph 0045, where element 106 is the substrate);
a first semiconductor die, in a first stack of dies, above the substrate and comprising: a first edge (figure 10, paragraph 0043, where the bottom most element 123 is the first semiconductor die in a first stack of dies [stack of element 123] above the substrate, with a first edge [most left-handed side of bottom element 123]);
a second semiconductor die, in a second stack of dies, above the substrate, proximate to the first semiconductor die, and comprising: a second edge that is approximately parallel the first edge and separated from the first edge (figure 10, paragraph 0043, where the second from the bottom most element 123 is the second semiconductor die in a first stack of dies [stack of element 123] above the substrate, with a second edge [most left-handed side of bottom element 123] which is parallel to the first edge);
a third semiconductor die in a stacked arrangement above the first semiconductor die in the first stack of dies and comprising: a first overhang portion extending beyond the first edge (figure 10, paragraph 0043, where the third from the bottom most element 123 is the third semiconductor die in a first stack of dies [stack of element 123] above the substrate, with a first overhang portion that extends beyond the first edge [specifically the region of the third from bottom element 123 between the left-hand side of said element and the left-hand side of the first bottom element 123])
a fourth semiconductor die in a stacked arrangement above the second semiconductor die in the second stack of dies and comprising: a second overhang portion extending beyond the second edge ((figure 10, paragraph 0043, where the fourth from the bottom most element 123 is the fourth semiconductor die in a first stack of dies [stack of element 123] above the substrate, with a second overhang portion that extends beyond the second edge [specifically the region of the fourth from bottom element 123 between the left-hand side of said element and the left-hand side of the second bottom element 123]),
and a legged support structure between the first semiconductor die and the second semiconductor die and comprising: a first portion directly under the first overhang portion and configured to support the first overhang portion; and a second portion directly under the second overhang portion and configured to support the second overhang portion (figure 10, paragraph 0043, where element 104 is the legged support structure situated between the first semiconductor and second semiconductor die [first from bottom and second from bottom element 123], configured to support botht he first and second overhang portions [regions under the fourth from the bottom die and second from the bottom die left of the left-hand side of the bottom most element 123 and second to bottom element 123]).
[claim 14] The semiconductor device assembly of claim 13, wherein at least one of the first semiconductor die, the second semiconductor die, the third semiconductor die, or fourth semiconductor die comprises: a NAND memory device (figure 10, paragraph 0063, where element 123 [any of the first through fourth semiconductor die] can be a NAND memory device).
[claim 15] The semiconductor device assembly of claim 13, wherein at least one of the first semiconductor die, the second semiconductor die, the third semiconductor die, or the fourth semiconductor die comprises: a dynamic random access memory device (figure 10, paragraph 0063, where element 123 [any of the first through fourth semiconductor die] can be a dynamic random access memory device).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al (US 20190067248) in view of Chiu et al (US 20100044861).
Yoo et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 8] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a wire loop structure.
However, Chiu et al teaches
[claim 8] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a wire loop structure (paragraph 0052, figure 14, where element 360 is part of the support structure and is in the shape of a balcony loop).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yoo et al to incorporate the teachings of Chiu et al to use a wire loop structure instead of a rigid structure to distribute the load more efficiently to allow for greater structural stability.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al (US 20190067248) in view of Dogiamis et al (US 20210398922).
Yoo et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 9] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a copper material.
However, Dogiamis et al teaches
[claim 9] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a copper material (paragraph 0077, where the support structure [element 450] is made of copper).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yoo et al with the teachings of Dogiamis to use a thermally conductive materially to help dissipate the thermal load from the die and thus promote greater efficiency of the device.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al (US 20190067248) in view of Oi et al (US 20080142944).
Yoo et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 10] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a material having a modulus of elasticity that is included in a range of approximately 115 gigapascal to approximately 130 gigapascal.
However, Oi et al does teach
[claim 10] The semiconductor device assembly of claim 1, wherein the legged support structure comprises: a material having a modulus of elasticity that is included in a range of approximately 115 gigapascal to approximately 130 gigapascal (paragraph 0050, where elastically-deformable pillar like structures are in place of the structural supports of Yoo et al, and have a modulus of elasticity between 100 and 230 gigapascals which lies within the range of 115 and 130 gigapascals).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yoo et al with the teachings of Oi et al in order to provide a spring like structure that allows for some movement but still remain sturdy, compared to a rigid structure that could break easily with a stress force, to provide maximal structural stability.
Claim(s) 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cui et al (US 20210407967) in view of Fay et al (US 20220084977).
Cui et al teaches all of the limitations of the parent claim, claim 13, and further discloses
[claim 17] The semiconductor device assembly of claim 13, further comprising: a fifth semiconductor die below an approximately horizontal span of the legged support structure.
[claim 19] The semiconductor device assembly of claim 17, wherein the fifth semiconductor die comprises: a controller device.
However, Fay et al does teach
[claim 17] The semiconductor device assembly of claim 13, further comprising: a fifth semiconductor die below an approximately horizontal span of the legged support structure (figure 1C, paragraph 0015, where element 102 is the fifth semiconductor die which is situated below a horizontal span of the support structure as read from Cui et al [the horizontal span is the area under the second semiconductor die from the substrate when reading Fay et al onto Cui et al]).
[claim 19] The semiconductor device assembly of claim 17, wherein the fifth semiconductor die comprises: a controller device (paragraph 0015, where element 102 is the fifth semiconductor die that is a controller device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Cui et al to incorporate the teachings of Fay et al in order to have a fifth semiconductor die to control the memory die to optimize performance while optimizing spatial density by situating the device beneath the horizontal span.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Cui et al (US 20210407967) in view of Wang et al (US 20230361048).
Cui et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 16] The semiconductor device assembly of claim 13, wherein at least one of the first semiconductor die, the second semiconductor die, the third semiconductor die, or the fourth semiconductor die has a thickness that is included in a range of approximately 40 microns to approximately 50 microns.
However, Wang et al does teach
[claim 16] The semiconductor device assembly of claim 13, wherein at least one of the first semiconductor die, the second semiconductor die, the third semiconductor die, or the fourth semiconductor die has a thickness that is included in a range of approximately 40 microns to approximately 50 microns (paragraph 0047, where the memory die can have various ranges, of which fall in the range of 40 to 50 micron).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Cui et al to incorporate the teachings of Wang et al in order to maximize space by keeping the memory die at a minimal thickness to preserve performance but optimize spatial density.
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Cui et al (US 20210407967) in view of Keeth et al (US 20190121560)
Cui et al teaches all of the limitations of the parent claim, claim 1, and further teaches,
[claim 18] and wherein a leg of the legged support structure is connected to the bond pad (figure 1A, paragraph 0042, where elements 146 are electrical contacts to the substrate which has electrical contacts embedded in it to bond to the support structure)
However, Cui et al does not specifically teach
[claim 18] The semiconductor device assembly of claim 17, wherein the substrate comprises: a bond pad between the fifth semiconductor die and the first semiconductor die
However, Keeth et al does teach
[claim 18] The semiconductor device assembly of claim 17, wherein the substrate comprises: a bond pad between the fifth semiconductor die and the first semiconductor die (figure 6A, paragraph 0065 where element 605 is the fifth semiconductor and also has electrical contacts connected to the substrate, when put onto Cui et al signifies that the first semiconductor die [as shown in Keeth et al, element 720 on the bottom of the right-hand side stack of die] is also connected to the fifth semiconductor die).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Cui et al to incorporate the teachings of Keeth et al in order to electrical connect the semiconductor die together through the substrate and with the support legged structure to form a functioning device.
Claim(s) 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Cui et al (US 20210407967).
Cui et al teaches
[claim 20] A semiconductor device assembly, comprising: a substrate (figure 1A, paragraph 0042, where element 106 is the substrate);
a first semiconductor die above the substrate and comprising: an edge (figure 3, paragraph 0042, where element 123 directly above element 108 is the first semiconductor die above the substrate and comprises an edge, which is the left-hand most side edge as shown in figure 3);
a second semiconductor die in a stacked arrangement above the first semiconductor die and comprising: an overhang portion extending beyond the edge (figure 3, paragraph 0042, where element 123 directly above the first die [which is element 123 directly above element 108] is the second semiconductor die and comprises an overhang portion which extends beyond the edge of the first die which is the portion of said element situated between the left-hand side of said element and the first die);
and a support structure between the overhang portion and the substrate and including a profile comprising: an approximately horizontal span directly below the overhang portion (figures 1A and 3, paragraph 0042-0043, where element 104 is the support structure situated in the overhang portion above the substrate, where a profile of said support structure contains an approximately horizontal span directly below the overhang portion);
However Cui et al does not specifically disclose
[claim 22] and radially curved portions at opposing ends of the approximately horizontal span.
However, according to MPEP 2144 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
B. Changes in Shape
In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Cui et al to have modified the specific shape of the end of the structure to have a partially curved section in order to improve mechanical stability as it is well known in all physical arts that a curved structure redistributes pressure more evenly than flat structures with edges.
Cui et al further teaches
[claim 21] The support structure of claim 20, further comprising: legged support structures extending from the radially curved portions to bond pads below the overhang portion (figures 1A and 3, paragraphs 0042-0043, element 146 is the bond pads situated throughout the bottom layer of element 104, where one of the bond pads exists at the edge under the overhang portion [portion between left-hand side of the second from the bottom and bottom elements 123]).
Claim(s) 22 is rejected under 35 U.S.C. 103 as being unpatentable over Cui et al (US 20210407967) in view of Chong et al (US 20220336417).
Cui et al as modified teaches all of the limitations of the parent claim, claim 20, but does not specifically disclose
[claim 22] The semiconductor device assembly of claim 20, wherein the substrate comprises: a thermal via structure, and wherein a legged support structure of the support structure connects to the thermal via structure
However, Chong et al does teach
[claim 22] The semiconductor device assembly of claim 20, wherein the substrate comprises: a thermal via structure, and wherein a legged support structure of the support structure connects to the thermal via structure (paragraph 0036, where the device can have attached to it, namely through the substrate, a head sink or some thermal coupler to help dissipate the heat. When read onto Cui et al, where the support structure is attached to the substrate, naturally the legged support structure would also be attached to said thermal dissipation structure that is attached to the substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Cui et al as modified with the teachings of Chong et al in order to dissipate heat from the device to allow for maximal efficiency of operation by keeping temperature regulated.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chang (US 20210193621), Chen et al (US 20190341366), Wu et al (US 10276546), Watanabe et al (US 20180294249), and Foster, SR. et al (US 20110108972).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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