DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 9, the limitation “wherein the tip includes a portion of at least one of the semiconductor layer, the gate electrode, the first insulating layer, the source electrode, or the drain electrode of the thin-film transistor protruding toward the hole area,” is not described in the original disclosure in such a way to convey possession. Specifically, this aspect of the claimed invention has not been described with sufficient particularity such that one skilled in the art would recognize that the inventor had possession of the claimed invention at the time of filing. Further, the feature appears to be an essential or critical feature which is not adequately described in the specification and is not conventional or known in the art. (see MPEP 2163.A). It is noted that, while the disclosure recites the common layer (shown as 620 in Fig. 6A and understood as having layers 420/430/431/433/435/437 therein, see [0128]) as a whole may comprises at least one of these layers, there is no evidence of any layer of the TFT (e.g. semiconductor layer 428 or metal layer of 422) extending throughout the entirety of the layer and/or to the tip. If anything, the semiconductor and metal layers of the TFT are explicitly shown in Fig. 4 as being discontinuous and confined to the portion of the common layer which is in the region of the transistor. Accordingly, the disclosure does not convey possession for the entire scope of the claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “thin-film transistor layer” is unclear as to what is required by the limitation. Specifically, the claim further recites a “thin-film transistor” and it is unclear how the two are related and/or different. It is additionally noted that “thin-film transistor layer” is not a term of art and is lacks antecedent basis in the specification, so the proper scope of the term cannot be ascertained.
Regarding claim 1, the limitation “light emitting layer” is unclear as to what is required by the limitation. Specifically, the claim further recites a “light emitting element” and it is unclear how the two are related and/or different. It is additionally noted that “light emitting layer” is a term of art, a light emitting element would typically be understood to comprise a light emitting layer, however, the opposite relationship is recited in the claim. Additionally, the term lacks antecedent basis in the specification, so the proper scope of the term cannot be ascertained.
Regarding claim 1, the limitation “wherein thin-film transistor layer including at least one of the semiconductor layer, the gate electrode, the first insulating layer, the source electrode, or the drain electrode of the thin-film transistor extends to the hole area,” is unclear because the previous recitation of “thin-film transistor layer” requires the “thin-film transistor layer” comprises all of the subsequently recited layers and not only “at least one” of them. It is further unclear as to if applicant intends to require one of the semiconductor layer, the gate electrode, the first insulating layer, the source electrode, or the drain electrode of the thin- film transistor to extend to the hole area, or if applicant intends to require the “thin-film transistor layer” to extend to the hole area. Lastly, it is unclear how any of the semiconductor layer, the gate electrode layer, the gate electrode, the source electrode or the drain electrode can extend to the hole area, as each is a claimed as elements of the thin-film transistor, disclosed as 420, and explicitly shown as not extending beyond the transistor 420 in Fig. 4. The proper interpretation of the terms “to” and “hole area” are is therefore unclear.
Regarding claim 1, the limitation “wherein the light emitting layer extends to the hole area and covers an edge portion of the thin-film transistor layer adjacent to the hole area,” is unclear as to what is required by the limitation. Specifically, it is unclear if applicant intends to require the entirety of the “light emitting layer” (i.e. the anode, the light emitting unit, and the cathode) to extend to the hole area and cover an edge portion, if applicant intends to require only a part of the light emitting layer to extend to the hole area and cover an edge portion, or if applicant intends something else. Lastly, it is unclear how either of the anode or the light emitting unit can extend to the hole area, as each is a claimed element of the light emitting element, disclosed as 440, and explicitly shown as not extending beyond the light emitting element 440 in Fig. 4. The proper interpretation of the terms “to” and “hole area” are is therefore unclear.
Regarding claim 7, the limitation “a first common layer including at least one of the semiconductor layer, the gate electrode, the first insulating layer, the source electrode, or the drain electrode of the thin-film transistor,” is unclear as to how it is related to the “thin-film transistor layer.”
Regarding claim 10, the limitation “a portion of at least one layer of a metal layer, an inorganic insulating layer, or a semiconductor layer,” is unclear as to how it is related to the “a portion of at least one of the semiconductor layer, the gate electrode, the first insulating layer, the source electrode, or the drain electrode of the thin-film transistor protruding toward the hole area,” recited in claim 9.
Regarding claim 11, the limitation “further comprising a second common layer on the first common layer and covering an edge of the first common layer” is unclear as to how it is related to the light emitting layer covering an edge portion of the thin-film transistor layer recited in claim 1.
Regarding claim 14, the limitation “an encapsulation layer including…at least one of an encapsulation layer, a particle layer, and a barrier film,” is unclear as to how the latter recitation of “an encapsulation layer,” is related to the first. It is further unclear because it appears to indicate that the encapsulation possibly includes a particle layer or barrier film but not an encapsulation layer.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 20190288047; herein “Jeong”) in view of Kim et al. (US 20180247982; herein “Kim”).
Regarding claim 1, Jeong discloses in Fig. 4A-B and related text a display device, comprising:
an active area (e.g. DA), a non-active area (e.g. NDA) adjacent to the active area, and a hole area (e.g. PA) in the active area;
a flexible substrate including a stack of a plurality of layers (e.g. 11/14/13, see [0076]-[0079]);
a buffer layer (e.g. 12/15) disposed on the flexible substrate;
a thin-film transistor layer including a thin-film transistor (TR) disposed on the buffer layer in the active area, the thin-film transistor comprising:
a semiconductor layer (SL, see [0081]) disposed on the buffer layer;
a gate electrode (CE, see [0083]) disposed on the semiconductor layer;
a first insulating layer (21, see [0081]) disposed between the semiconductor layer and gate electrode; and
a source electrode and a drain electrode (at least via portions of IE and OE, see [0085]) disposed in contact with the semiconductor layer;
planarization layers disposed on the thin-film transistor comprising a first planarization layer (22, see [0085]) and a second planarization layer (23, see [0086]);
a connecting electrode (horizontal extending portion of OE) disposed between the first planarization layer and the second planarization layer;
a light emitting layer including a light-emitting element (OD, see [0087]) on the second planarization layer, the light emitting element comprising:
an anode (E1) disposed on the second planarization layer;
a light-emitting unit (EL/OL, see [0091]-[0092]) on the anode; and
a cathode (E2, see [0089]) disposed on the light-emitting unit,
wherein the thin-film transistor layer including at least one of the semiconductor layer, the gate electrode, the first insulating layer, the source electrode, or the drain electrode of the thin-film transistor extends to the hole area (see Fig. 4A-B);
wherein the light emitting layer extends to the hole area and covers an edge portion of the thin-film transistor layer adjacent to the hole area (see Fig. 4A).
Jeong does not explicitly disclose
the semiconductor layer comprising an oxide semiconductor;
the anode comprising a reflective layer;
the cathode comprising a transparent conductive oxide.
In the same field of endeavor, Kim teaches in Fig. 3 and related text a display device comprising
the semiconductor layer (328) comprising an oxide semiconductor (see [0055]-[0057]);
the anode (342/410) comprising a reflective layer (see [0069] and [0082]);
the cathode (346/470) comprising a transparent conductive oxide (see [0069] and [0112]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jeong by having the semiconductor layer comprising an oxide semiconductor, the anode comprising a reflective layer, and the cathode comprising a transparent conductive oxide in order to achieve a transistor with excellent mobility and uniformity and a top emission device with efficient output (see Jeong [0057] and [0082]).
Regarding claim 2, Jeong further discloses further comprising a first tip (e.g. 14-E) including at least a portion of the flexible substrate protruding toward the hole area (see Fig. 4B).
Regarding claim 3, Jeong further discloses wherein the flexible substrate comprising a first substrate layer (11), a second substrate layer (13), and a substrate protecting layer (14) between the first substrate layer and the second substrate layer.
Regarding claim 4, Jeong further discloses wherein the first tip includes an extension portion of the substrate protecting layer (14) extending toward the hole area.
Regarding claim 5, Jeong further discloses wherein the substrate protecting layer (14) is an inorganic insulating layer (see [0110]).
Regarding claim 6, Jeong further discloses wherein the first tip (14-E) includes a part of the inorganic insulating layer (14).
Regarding claim 7, Jeong further discloses further comprising a first common layer (20) including at least one or more components of the thin-film transistor.
Regarding claim 8, Jeong further discloses wherein the first common layer includes a second tip (e.g. 21-E) protruding toward the hole area (see Fig. 4B).
Regarding claim 9, Jeong further discloses wherein the second tip includes a portion of at least one of the semiconductor layer, the gate electrode, the first insulating layer, the source electrode, or the drain electrode of the thin-film transistor protruding toward the hole area (e.g. 21).
Regarding claim 10, Jeong further discloses wherein the second tip includes a portion of at least one layer of a metal layer, an inorganic insulating layer, or a semiconductor layer (e.g. 21 is inorganic insulating layer).
Regarding claim 11, Jeong further discloses further comprising a second common layer (e.g. at least a portion of 30) on the first common layer and covering an edge of the first common layer.
Regarding claim 12, Jeong further discloses wherein the second common layer including the light-emitting element (OD) within the second common layer (the portion of 30) (see Fig. 4A).
Regarding claim 13, Jeong further discloses further comprising an encapsulation layer (e.g. 32/34, see [0095]) on the second common layer, wherein the encapsulation layer covers a bottom surface of the second tip (see Fig. 4B).
Regarding claim 14, Jeong further discloses wherein the encapsulation layer (32/34) is a combination of a plurality of layers, wherein the plurality of layers include at least one of an encapsulation layer, a particle cover layer, and a barrier film (see [0096]-[0097]).
Regarding claim 15, Jeong further discloses wherein the first substrate layer (11) and the second substrate layer (13) are made of polyimide (see [0076] and [0079]).
Response to Arguments
Applicant's arguments filed 7/22/2026 have been fully considered but they are not persuasive.
Applicant argues (page 5) that paragraphs [0126], [0128], and [0129] provide full support for the limitations of claims 9 and 10.
In response, the examiner disagrees. Specifically, it is noted that the features claimed are not described in the original disclosure in such a way to convey possession. The scope of the claim covers a device having the semiconductor layer or the gate electrode or the insulating layer or the source electrode or the drain electrode of the thin-film transistor to extend to the tip in the hole area. This requires support and conveyance of possession for each of the possibilities covered by the scope. While the disclosure recites the common layer (shown as 620 in Fig. 6A and understood as having layers 420/430/431/433/435/437 therein, see [0128]) as a whole may comprise at least one of these layers, there is no evidence of that each of the possibilities covered by the scope of the claim extends into the tip. The common layer is understood to be a composite layer “in which the thin-film transistor is formed,” and comprising layers which are shown in Fig. 4, i.e. the combination of layers 428, 431, 433, 422, 424, and 426. It is not understood to be a layer separate and distinct from and in addition to those layers shown in Fig. 4. There is no disclosure of which individual layers of the composite layer structure extend to or into the tip, nor has not been described with sufficient particularity such that one skilled in the art would recognize that the inventor had possession of the claimed invention at the time of filing. Rather, which layers of the common layer are or are not in the tip has not been discussed at all. Further, the feature appears to be an essential or critical feature which is not adequately described in the specification and is not conventional or known in the art. (see MPEP 2163.A).
Applicant argues (page 5-6) that Jung and Kim do not teach or suggest the claimed invention because the layers E1, E2, EL, OL do not cover the edge of buffer layer 15 or insulating layer 21 in region PA of Fig. 6A.
In response, the examiner disagrees. Specifically, it is noted that Fig. 6A is not relied upon in the current rejection. It is also noted that in accordance with MPEP 2111, USPTO personnel are to give claims their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997).Therefore the claim limitation “edge portion” has been given its broadest reasonable interpretation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896
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