DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to a Restriction Requirement filed on 05/14/2026, the Applicant elected with traverse claims 1-17 (Group I) in a reply filed on 07/02/2026. The traversal is on the ground(s) that claims 18-20 of the non-elected Group II do not proscribe a specific order of the method of making, based on MPEP 2111 and Altiris Inc. v. Symantec Corp., 318 F.3d 1363, 1371, 65 USPQ2d 1865, 1869-70 (Fed. Cir. 2003) (The court held that it was improper to read a specific order of steps into method claims where, as a matter of logic or grammar, the language of the method claims did not impose a specific order on the performance of the method steps, and the specification did not directly or implicitly require a particular order). The examiner found the arguments persuasive and withdraws the Restriction Requirement filed on 07/02/2026.
Currently, claims 1-20 are examined as below.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statements (IDS) filed on 10/01/2024, 10/30/2024 and 05/30/2025. The IDS have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claim 12 is indefinite, because the abbreviation “CMOS” has not been clearly defined in the claim. It is unclear what is necessarily required by the abbreviation “CMOS.”
Claim 13 is indefinite, because the limitation “optionally” renders the claim indefinite. It is unclear whether or not the inactive areas are at terminal ends of the gate, and if the inactive areas are between the active areas and at terminal ends of the gate at the same time.
Claim 14 is indefinite, because the limitation “inactive areas of the gate” in line 2 renders the claim indefinite. It is unclear whether such inactive areas are the same ones as recited claim 13. The limitation will be interpreted as the same.
Claim 15 is indefinite, because:
(1) The limitation “inactive areas of the gate” in lines 2-3 renders the claim indefinite. It is unclear whether such inactive areas are the same one as recited in claim 13.
(2) The limitation “active areas of the gate” in line 4 renders the claim indefinite. It is unclear whether such active areas are the same one as recited in claim 13.
Claim 17 is indefinite, because:
(1) The limitation “the source side of the gate” in lines 2-3 is not mentioned in claims 12 and 13. There is insufficient antecedent basis.
(2) The limitation “the drain side of the gate” in line 3 is not mentioned in claims 12 and 13. There is insufficient antecedent basis.
Independent claim 18 is indefinite, because the abbreviation “CMOS” has not been clearly defined in the claim. It is unclear what is necessarily required by the abbreviation “CMOS.”
Claim 19 is indefinite, because:
(1) The limitation “optionally” renders the claim indefinite. It is unclear whether or not the inactive areas are at terminal ends of the gate, and if the inactive areas are between the active areas and at terminal ends of the gate at the same time.
(2) The limitation “inactive areas of the gate” in line 6 renders the claim indefinite. It is unclear whether such inactive areas are the same ones as recited earlier in claim 19. The limitation will be interpreted as the same.
Claim 20 is indefinite, because the limitation “active areas of the gate” renders the claim indefinite. It is unclear whether or not such active areas are the same ones are recited in claim 19. The limitation will be interpreted as the same.
Note the dependent claims 13-17 and 19-20 necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Myeong et al. (2019). “Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing IOFF in Various Sub-10-nm 3-D Transistors.” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 1, January 2019, pages 647-654. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8556084. Retrieved on 2026/07/16. Hereinafter “Myeong.”
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Regarding independent claim 1, Myeong in Figs. 1-2 teaches an integrated circuit (Figs. 1-2), comprising:
a substrate sub (Figs. 1-2, pp.648-649, Table I, substrate sub);
a metal layer M10 (Figs. 1-2, pp.648-649, Table II, metal M10, which is the maximum/uppermost metal layer) positioned above the substrate sub;
an oxide layer STI (Figs. 1-2, pp. 647-653, shallow trench isolation (STI) including SiO2) disposed between the substrate sub and the metal layer M10 (Figs. 1-2, the uppermost metal layer M10 would be above the STI);
a transistor S, D, G (Figs. 1-2, pp.647-649, Table I, FET including source S, drain D, and gate G) disposed on the substrate sub between the substrate sub and the oxide layer M10, the transistor S, D, G comprising a source S, a gate G, and a drain D (Figs. 1-2, pp.647-649, Table I); and
a dummy contact (Figs. 1-2, pp.648-649, thermal contact set on the source, drain, and gate) positioned within the oxide layer STI above and in thermal contact with the gate G of transistor S, D, G (Figs. 1-2), wherein the dummy contact is electrically isolated (Figs. 1-2, pp.647-649, thermal contacts are separate structures set only on the respective source S, drain D, and gate G) and configured to convey heat generated by the transistor S, D, G during operation of the integrated circuit to the metal layer M10 (pp.648-650).
Regarding claim 6, Myeong in Fig. 1 further teaches the gate G extends beyond the source S and drain D, and an active area G (Figs. 1-2, pp.647-649, gate G) of the gate G is defined as an area of the gate G directly between the source S and the drain D; and
wherein the dummy contact is positioned outside of the active area G (Figs. 1-2).
Regarding claim 11, Myeong in Figs. 1-2 further teaches an electronic device (p.647, CMOS device) comprising the integrated circuit of claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Myeong in view of US 2023/0031333 A1 to Chen et al. (“Chen”).
Regarding claim 2, Myeong does not explicitly disclose a thermally conductive via formed between the dummy contact and the metal layer.
Chen recognizes a need for improving the performance and reliability of a device by dissipating heat from structures (¶ 21). Chen satisfies the need by providing a thermally conductive via 320 (Fig. 3) formed between a dummy contact 323T (Fig. 3, ¶ 33, dummy metal pattern 323T) and a metal layer 318T (Fig. 3, ¶ 33, thermal contact 318T).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the dummy contact and the metal layer taught by Myeong with the thermally conductive via taught by Chen, so as to improve the performance and reliability of a device by dissipating heat from structures (Chen: ¶ 21).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable and obvious over Myeong.
Regarding claim 8, Myeong does not explicitly disclose a distance between the dummy contact and the drain D is less than a distance between the dummy contact and the source S.
However, it would have been obvious to form the distances within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 3-5, 7 and 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 3 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 3, a second oxide layer disposed on the metal layer; a second metal layer disposed on the second oxide layer; and a thermally conductive via formed through the second oxide layer between the metal layer and the second metal layer, the thermally conductive via configured to convey the heat generated by the transistor to the second metal layer.
Claim 5 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 5, wherein the transistor is disposed within a top integrated circuit of the plurality of stacked integrated circuits; and wherein the top integrated circuit further comprises one or more stacked thermally conductive vias configured to convey the heat generated by the transistor to a top metal layer of the top integrated circuit.
Claim 7 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 7, a second dummy contact positioned within the oxide layer above the active area of the gate and in thermal contact with the gate, wherein the second dummy contact is electrically isolated and configured to convey heat generated by the transistor to the metal layer.
Claims 9-10 would be allowable, because they depend from the allowable claim 7.
Claims 12-20 are rejected. Claims 12-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding independent claim 12, Myeong in Figs. 1-2 teaches a integrated circuit (Figs. 1-2), comprising:
a second CMOS wafer (Figs. 1-2, pp.647, 650) comprises:
a field effect transistor structure S, D, G (Figs. 1-2, pp.647-649, Table I, FET including source S, drain D, and gate G) comprising a gate G (Figs. 1-2, pp.647-649), an aligned pair of source S and drain D (Figs. 1-2), the source S being disposed on one side of the gate G and drain D being disposed on an opposite side of the gate G (Figs. 1-2);
an oxide layer STI (Figs. 1-2, pp. 647-653, shallow trench isolation (STI) including SiO2) disposed on the field effect transistor structure S, D, G;
a metal layer M10 (Figs. 1-2, pp.648-649, Table II, metal M10, which is the maximum/uppermost metal layer) disposed on the oxide layer STI such that the oxide layer STI is between the metal layer M10 and the field effect transistor structure S, D, G (Figs. 1-2); and
a plurality of thermally conductive contacts (Figs. 1-2, pp.648-649, thermal contacts set on the source, drain, and gate) disposed within the oxide layer STI, the thermally conductive contacts each being electrically isolated (Figs. 1-2, pp.647-649, thermal contacts are separate structures set only on the respective source S, drain D, and gate G) and in thermal contact with the field effect transistor structure S, D, G (pp.648-650).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 12, a three-dimensional integrated circuit, comprising: a first CMOS wafer; and a second CMOS wafer disposed on and electrically connected to the first CMOS wafer, and a plurality of aligned pairs of sources and drains, the sources being disposed on one side of the gate and drains being disposed on an opposite side of the gate.
Therefore, independent claim 12 would be allowable.
Claims 13-17 would be allowable, because they depend from the allowable claim 12.
Regarding independent claim 18, Myeong in Figs. 1-2 teaches a method of making a integrated circuit (Figs. 1-2), comprising:
fabricating a second CMOS wafer (Figs. 1-2, pp.647, 650);
wherein the second CMOS wafer comprises:
a field effect transistor structure S, D, G (Figs. 1-2, pp.647-649, Table I, FET including source S, drain D, and gate G) comprising a gate G (Figs. 1-2, pp.647-649), an aligned pair of source S and drain D, the source S being disposed on one side of the gate G and drain D being disposed on an opposite side of the gate G (Figs. 1-2);
an oxide layer STI (Figs. 1-2, pp. 647-653, shallow trench isolation (STI) including SiO2) disposed on the field effect transistor structure S, D, G;
a metal layer M10 (Figs. 1-2, pp.648-649, Table II, metal M10, which is the maximum/uppermost metal layer) disposed on the oxide layer STI such that the oxide layer STI is between the metal layer M10 and the field effect transistor structure S, D, G (Figs. 1-2); and
a plurality of thermally conductive contacts (Figs. 1-2, pp.648-649, thermal contacts set on the source, drain, and gate) disposed above the gate G within the oxide layer STI, the thermally conductive contacts each being electrically isolated (Figs. 1-2, pp.647-649, thermal contacts are separate structures set only on the respective source S, drain D, and gate G) and in thermal contact with the field effect transistor structure S, D, G (pp.648-650).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 18, a method of making a integrated circuit, comprising: a plurality of aligned pairs of sources and drains, the sources being disposed on one side of the gate and drains being disposed on an opposite side of the gate; and electrically connecting the first CMOS wafer and the second CMOS wafer.
Therefore, independent claim 18 would be allowable.
Claims 19-20 would be allowable, because they depend from the allowable claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,840,190 B1 to Yang et al. relates to a semiconductor structure including a first semiconductor substrate, a first interconnect structure, a first conductive pad, a first dielectric layer, and a first conductive connector, in which first semiconductor substrate includes a plurality of first semiconductor devices, the first interconnect structure is disposed over the first semiconductor substrate and electrically coupled to the first semiconductor devices, the first conductive pad is disposed over and electrically coupled to the first interconnect structure, the first dielectric layer covers the first conductive pad and the first interconnect structure, and the first dielectric layer includes a portion extending through the first conductive pad. The first conductive connector is disposed on and electrically coupled to the first interconnect structure, and the first conductive connector extends through the portion of the first dielectric layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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