DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priorities based on an application JP 2023-004623 filed in Japan Patent Office (JPO) on January 16, 2023 and an application JP 2023-193814 filed in Japan Patent Office (JPO) on November 14, 2023 and receipt of certified copies thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on January 8, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Objections
Claims 1, 18-21 and 25 objected to because of the following informalities:
In claim 1, lines 3-5, “a transistor portion which is provided on the semiconductor substrate; a diode portion which is provided in the semiconductor substrate side by side with the transistor portion in a first direction” should read --a transistor portion which is provided in the semiconductor substrate; a diode portion which is provided in the semiconductor substrate side by side with the transistor portion in a first direction-- (emphasis added) for clarity and term consistency. Support can be found at least in Figs. 1, 3A and 4 of Applicant’s original disclosure.
In claim 18, lines 3-5, “a transistor portion which is provided on the semiconductor substrate; a diode portion which is provided in the semiconductor substrate side by side with the transistor portion in a first direction” should read --a transistor portion which is provided in the semiconductor substrate; a diode portion which is provided in the semiconductor substrate side by side with the transistor portion in a first direction-- (emphasis added) for clarity and term consistency. Support can be found at least in Figs. Figs. 1, 3A and 4 of Applicant’s original disclosure.
In claim 19, lines 2-3, “the total value of the third lengths is shorter than a length of the transistor portion in the first direction” should read --the total value of the third lengths is smaller than a length of the transistor portion in the first direction-- (emphasis added) for clarity.
In claim 20, lines 3-5, “a transistor portion which is provided on the semiconductor substrate; a diode portion which is provided in the semiconductor substrate side by side with the transistor portion in a first direction” should read --a transistor portion which is provided in the semiconductor substrate; a diode portion which is provided in the semiconductor substrate side by side with the transistor portion in a first direction-- (emphasis added) for clarity and term consistency. Support can be found at least in Figs. Figs. 1, 3A and 4 of Applicant’s original disclosure.
In claim 21, lines 2-4, “a total value of third lengths, in the first direction, of first lifetime adjustment regions, each being identical to the first lifetime adjustment region, provided in the transistor portion is shorter than a length of the transistor portion in the first direction” should read --a total value of third lengths, in the first direction, of first lifetime adjustment regions, each being identical to the first lifetime adjustment region, provided in the transistor portion is smaller than a length of the transistor portion in the first direction—(emphasis added) for clarity.
In claim 25, lines 3-5, “a transistor portion which is provided on the semiconductor substrate; a diode portion which is provided in the semiconductor substrate side by side with the transistor portion in a first direction” should read --a transistor portion which is provided in the semiconductor substrate; a diode portion which is provided in the semiconductor substrate side by side with the transistor portion in a first direction-- (emphasis added) for clarity and term consistency. Support can be found at least in Figs. Figs. 1, 3A and 4 of Applicant’s original disclosure.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 29-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 29 recites the feature “a first width, in the first direction, of the first lifetime adjustment region of the diode portion is larger than a third width, in the first direction, of any one of first lifetime adjustment regions, each being identical to the first lifetime adjustment region, provided in the transistor portion” in lines 2-5. It is unclear what the above feature specifically refers to, thus, this renders the claim indefinite.
For example, according to the above feature of claim 29, each of the first lifetime adjustment regions of the transistor portion is identical to the first lifetime adjustment region of the diode portion. Thus, a third width, in the first direction, of any one of the first lifetime adjustment regions of the transistor portion could be identical to a first width, in the first direction, of the first lifetime adjustment region of the diode portion. Therefore, the above feature does not make sense. For the examination purpose, the above feature is interpreted to as --wherein a first width, in the first direction, of the first lifetime adjustment region of the diode portion and a third width, in the first direction, of any one of first lifetime adjustment regions provided in the transistor portion--.
Claim 30 recites the feature “the first width is larger than the third width of one of the first lifetime adjustment regions provided in the transistor portion that is closest to the diode portion” in lines 2-3. Regarding claim 30, the discussion with respect to claim 29 above similarly applies. For the examination purpose, the above feature is interpreted to as --the first width, and the third width of one of the first lifetime adjustment regions provided in the transistor portion that is closest to the diode portion --.
Claim 31 recites “a first width, in the first direction, of the first lifetime adjustment region of the diode portion is smaller than a third width, in the first direction, of any one of first lifetime adjustment regions, each being identical to the first lifetime adjustment region, provided in the transistor portion” in lines 2-5. It is unclear what the above feature specifically refers to, thus, this renders the claim indefinite.
For example, according to the above feature of claim 31, each of the first lifetime adjustment regions of the transistor portion is identical to the first lifetime adjustment region of the diode portion. Thus, a third width, in the first direction, of any one of the first lifetime adjustment regions of the transistor portion could be identical to a first width, in the first direction, of the first lifetime adjustment region of the diode portion. Therefore, the above feature does not make sense. For the examination purpose, the above feature is interpreted to as --a first width, in the first direction, of the first lifetime adjustment region of the diode portion, and a third width, in the first direction, of any one of first lifetime adjustment regions provided in the transistor portion--.
Claim 32 recites the feature “the first width is smaller than the third width of one of the first lifetime adjustment regions provided in the transistor portion that is closest to the diode portion” in line 2-3. Regarding claim 32, the discussion with respect to claim 31 similarly applies. For the examination purpose, the above feature is interpreted to as --the first width, and the third width of one of the first lifetime adjustment regions provided in the transistor portion that is closest to the diode portion--.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 10 and 18-23 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Naito US 2019/0326118.
Regarding claim 1, Naito teaches a semiconductor device (e.g., Figs. 12-14, [137]-[144]; also see Fig. 1 and Fig. 9, and the description thereof for additional details) which includes a semiconductor substrate (e.g., 10, Fig. 14) having an upper surface (e.g., 21, Fig. 14) and a lower surface (e.g., 23, Fig. 14), the semiconductor device comprising:
a transistor portion (e.g., 70, Fig. 14) which is provided on the semiconductor substrate;
a diode portion which (e.g., 80, Fig. 14) is provided in the semiconductor substrate side by side with the transistor portion in a first direction (e.g., Y-axis direction (negative side), Fig. 12, Fig. 14); and
a first lifetime adjustment region (e.g., 74 (74-1, 74-2, 74-3 and/or 74-4), Fig. 14, [142]) which is provided at a first depth (e.g., first depth of 74, Fig. 14) on an upper surface side of the semiconductor substrate, has a density of lattice defects (e.g., [104], [123]) that is a first defect density, and includes a region provided in the transistor portion (e.g., region of 74 in 70, Fig. 14), wherein
the transistor portion includes:
one or more emitter regions (e.g., 12, Fig. 14, Fig. 9, [75]) of a first conductivity type which are provided on the upper surface of the semiconductor substrate;
one or more contact regions (e.g., 15, Fig. 1, Fig. 14, [75]) of a second conductivity type which are provided on the upper surface of the semiconductor substrate; and
a collector region (e.g., 22, Fig. 14, Fig. 9, [89]) of the second conductivity type which is provided on the lower surface of the semiconductor substrate,
the diode portion includes a cathode region (e.g., 82, Fig. 14, Fig. 9, [81]) of the first conductivity type which is provided on the lower surface of the semiconductor substrate, and
a first length (e.g., distance C, Fig. 14, [141]) in the first direction by which the first lifetime adjustment region is provided in the diode portion is 0, or is smaller than a second length (e.g., distance D, Fig. 14, [143]) in the first direction by which the first lifetime adjustment region is not provided in the diode portion.
Regarding claim 2, Naito teaches the semiconductor device according to claim 1, wherein in a top view, a first area (e.g., first area of 74 having the distance C in 80, Fig. 12, Fig. 13) of the first lifetime adjustment region provided in the diode portion is 0, or is smaller than a second area (e.g., second area having the distance D in 80, Fig. 12, Fig. 13, Fig. 14) of a region in the diode portion where the first lifetime adjustment region is not provided.
Regarding claim 3, Naito teaches the semiconductor device according to claim 1, wherein the first length (e.g., distance C, Fig. 14) is 40% or less of a length (e.g., WF, Fig. 14) of the diode portion in the first direction (e.g., [141]).
Regarding claim 5, Naito teaches the semiconductor device according to claim 1, wherein the first length (e.g., distance C, Fig. 14) is smaller than a third length (e.g., third length of 74 in 70, Fig. 14), in the first direction, of the first lifetime adjustment region provided in the transistor portion.
Regarding claim 6, Naito teaches the semiconductor device according to claim 1, wherein in a top view, a first area (e.g., first area of 74 having the distance C in 80, Fig. 12, Fig. 13) of the first lifetime adjustment region provided in the diode portion is smaller than a third area (e.g., third area of 74 in 70, Fig. 12, Fig. 13) of the first lifetime adjustment region provided in the transistor portion.
Regarding claim 7, Naito teaches the semiconductor device according to claim 1, wherein the diode portion has a plurality of trench portions (e.g., 30, Fig. 14) provided from the upper surface to an inside of the semiconductor substrate and arranged side by side in the first direction (e.g., Fig. 14), the diode portion has a plurality of mesa portions (e.g., 64, Fig. 14), each of which is arranged between corresponding two of the plurality of trench portions in the first direction (e.g., Fig. 14), and the diode portion has, below at least two of the plurality of mesa portions arranged adjacent to each other in the first direction, a region (e.g., region having the distance D, Fig. 14) in which the first lifetime adjustment region is not provided (e.g., Fig. 14).
Regarding claim 10, Naito teaches the semiconductor device according to claim 1, wherein the transistor portion has a boundary region (e.g., 90, Fig. 14) adjacent to the diode portion in the first direction, the boundary region has at least one of the one or more contact regions (e.g., 15, Fig. 1), and the collector region (e.g., 22, Fig. 14), and does not have the one or more emitter regions (e.g., Fig. 14, Fig. 1), and the first lifetime adjustment region is provided in the boundary region (e.g., Fig. 14).
Regarding claim 18, Naito teaches a semiconductor device (e.g., Figs. 12-14, [137]-[144]; also see Fig. 1 and Fig. 9, and the description thereof for additional details) which includes a semiconductor substrate (e.g., 10, Fig. 14) having an upper surface (e.g., 21, Fig. 14) and a lower surface (e.g., 23, Fig. 14), the semiconductor device comprising:
a transistor portion (e.g., 70, Fig. 14) which is provided on the semiconductor substrate;
a diode portion which (e.g., 80, Fig. 14) which is provided in the semiconductor substrate side by side with the transistor portion in a first direction (e.g., Y-axis direction (negative side), Fig. 12, Fig. 14); and
a first lifetime adjustment region (e.g., 74 (74-1, 74-2, 74-3 and/or 74-4), Fig. 14, [142]) which is provided at a first depth (e.g., first depth of 74, Fig. 14) on an upper surface side of the semiconductor substrate and has a density of lattice defects (e.g., [104], [123]) that is a first defect density, wherein
the transistor portion includes:
one or more emitter regions (e.g., 12, Fig. 14, Fig. 9, [75]) of a first conductivity type which are provided on the upper surface of the semiconductor substrate;
one or more contact regions (e.g., 15, Fig. 1, Fig. 14, [75]) of a second conductivity type which are provided on the upper surface of the semiconductor substrate; and
a collector region (e.g., 22, Fig. 14, Fig. 9, [89]) of the second conductivity type which is provided on the lower surface of the semiconductor substrate,
the diode portion includes a cathode region (e.g., 82, Fig. 14, Fig. 9, [81]) of the first conductivity type which is provided on the lower surface of the semiconductor substrate, and
a first length (e.g., distance C, Fig. 14, [141], [139]) in the first direction by which the first lifetime adjustment region is provided in the diode portion is 0, or is smaller than a total value of third lengths (e.g., lengths of 74-1 and 74-2 in 70, in the first direction (discussed above), each of which is less than the distance B; Fig. 14, [141], [139]), in the first direction, of first lifetime adjustment regions, each being identical to the first lifetime adjustment region, provided in the transistor portion.
Regarding claim 19, Naito teaches the semiconductor device according to claim 18, wherein the total value of the third lengths (e.g., lengths of 74-1 and 74-2 in 70, in the first direction (discussed above), each of which is less than the distance B), Fig. 14, [141], [139]) is shorter than a length (e.g., WI of 70, Fig. 12, [139], [141]) of the transistor portion (in the first direction.
Regarding claim 20, Naito teaches a semiconductor device (e.g., Figs. 12-14, [137]-[144]; also see Fig. 1 and Fig. 9, and the description thereof for additional details) which includes a semiconductor substrate (e.g., 10, Fig. 14) having an upper surface (e.g., 21, Fig. 14) and a lower surface (e.g., 23, Fig. 14), the semiconductor device comprising:
a transistor portion (e.g., 70, Fig. 14) which is provided on the semiconductor substrate;
a diode portion which (e.g., 80, Fig. 14) which is provided in the semiconductor substrate side by side with the transistor portion in a first direction (e.g., Y-axis direction (negative side), Fig. 12, Fig. 14); and
a first lifetime adjustment region (e.g., 74 (74-1, 74-2, 74-3 and/or 74-4), Fig. 14, [142]) which is provided at a first depth (e.g., first depth of 74, Fig. 14) on an upper surface side of the semiconductor substrate, has a density of lattice defects (e.g., [104], [123]) that is a first defect density, and includes a region provided in the transistor portion (e.g., region of 74 in 70, Fig. 14), wherein
the transistor portion includes:
one or more emitter regions (e.g., 12, Fig. 14, Fig. 9, [75]) of a first conductivity type which are provided on the upper surface of the semiconductor substrate;
one or more contact regions (e.g., 15, Fig. 1, Fig. 14, [75]) of a second conductivity type which are provided on the upper surface of the semiconductor substrate; and
a collector region (e.g., 22, Fig. 14, Fig. 9, [89]) of the second conductivity type which is provided on the lower surface of the semiconductor substrate,
the diode portion includes a cathode region (e.g., 82, Fig. 14, Fig. 9, [81]) of the first conductivity type which is provided on the lower surface of the semiconductor substrate,
the diode portion has a plurality of trench portions (e.g., 30, Fig. 14) provided from the upper surface to an inside of the semiconductor substrate and arranged side by side in the first direction (e.g., Fig. 14),
the diode portion has a plurality of mesa portions (e.g., 64, Fig. 14), each of which is arranged between corresponding two of the plurality of trench portions in the first direction (e.g., Fig. 14), and
the diode portion has, below at least two of the plurality of mesa portions arranged adjacent to each other in the first direction, a region (e.g., region having the distance D, Fig. 14) in which the first lifetime adjustment region is not provided (e.g., Fig. 14).
Regarding claim 21, Naito teaches the semiconductor device according to claim 20, wherein a total value of third lengths (e.g., lengths of 74-1 and 74-2 in 70, in the first direction (discussed above), each of which is less than the distance B; Fig. 14, [141], [139]), in the first direction, of first lifetime adjustment regions, each being identical to the first lifetime adjustment region, provided in the transistor portion is shorter than a length (e.g., WI of 70, Fig. 12, [139], [141]) of the transistor portion in the first direction.
Regarding claim 22, Naito teaches the semiconductor device according to claim 1, wherein the first depth is positioned on the upper surface side with respect to an intermediate depth position of the semiconductor substrate in a depth direction (e.g., Fig. 14).
Regarding claim 23, Naito teaches the semiconductor device according to claim 1, wherein the first lifetime adjustment region includes a region (e.g., region of 74 below 15 in 90, Fig. 14) which is arranged below one of the one or more contact regions that is closest to the diode portion in the first direction.
Claims 25-27 and 29-32 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Shoji et al. US 2021/0151589.
Regarding claim 25, Shoji teaches a semiconductor device (e.g., Fig. 19, [199]; also see Figs. 4, 5 and 17, and the description thereof for additional details) which includes a semiconductor substrate (e.g., 10, Fig. 14) having an upper surface (e.g., 21, Fig. 19) and a lower surface (e.g., 23, Fig. 19), the semiconductor device comprising:
a transistor portion (e.g., 70, Fig. 19) which is provided on the semiconductor substrate;
a diode portion (e.g., 80, Fig. 19) which is provided in the semiconductor substrate side by side with the transistor portion in a first direction (e.g., X axis direction, Fig. 19); and
a first lifetime adjustment region (e.g., 72, Fig. 19, [193], [199]) which is, in both the transistor portion and the diode portion, provided at a first depth (e.g., first depth of 72, Fig. 19) on an upper surface side of the semiconductor substrate and has a density of lattice defects (e.g., [193]) that is a first defect density, wherein
the first lifetime adjustment region of the transistor portion and the first lifetime adjustment region of the diode portion are separated from each other (e.g., Fig. 19).
Regarding claim 26, Shoji teaches the semiconductor device according to claim 25, wherein the transistor portion includes: one or more emitter regions (e.g., 12, Fig. 19, [112]) of a first conductivity type which are provided on the upper surface of the semiconductor substrate; one or more contact regions (e.g., 15, Fig. 19, Fig. 4, [112]) of a second conductivity type which are provided on the upper surface of the semiconductor substrate; and a collector region (e.g., 22, Fig. 19, [125]) of the second conductivity type which is provided on the lower surface of the semiconductor substrate, and the first lifetime adjustment region (e.g., 72, Fig. 19) of the transistor portion includes a region (e.g., region of 72 below 15 in 70, Fig. 19, Fig. 4) below each of the one or more contact regions.
Regarding claim 27, Shoji teaches the semiconductor device according to claim 26, wherein the first lifetime adjustment region includes a region (e.g., region of 72 below 15 in 90 of 70, Fig. 19) which is arranged below one of the one or more contact regions that is closest to the diode portion in the first direction.
Regarding claim 29, Shoji teaches the semiconductor device according to claim 25, wherein a first width (e.g., first width of 72 in 80 in X axis direction, Fig. 19), in the first direction, of the first lifetime adjustment region of the diode portion is larger than a third width (e.g., third width of 72 in 70 in X axis direction, Fig. 19), in the first direction, of any one of first lifetime adjustment regions, each being identical to the first lifetime adjustment region, provided in the transistor portion (see 112 rejection above).
Regarding claim 30, Shoji teaches the semiconductor device according to claim 29, wherein the first width is larger than the third width (e.g., third width of 72 in 90 of 70 in X axis direction, Fig. 19) of one of the first lifetime adjustment regions provided in the transistor portion that is closest to the diode portion (see 112 rejection above).
Regarding claim 31, Shoji teaches the semiconductor device according to claim 25, wherein a first width (e.g., first width of 72 in 80 in X axis direction, Fig. 19), in the first direction, of the first lifetime adjustment region of the diode portion is smaller than a third width (e.g., third width of 72 in 70 in X axis direction, Fig. 19), in the first direction, of any one of first lifetime adjustment regions, each being identical to the first lifetime adjustment region, provided in the transistor portion (see 112 rejection above).
Regarding claim 32, Shoji teaches the semiconductor device according to claim 31, wherein the first width is smaller than the third width (e.g., third width of 72 in 90 of 70 in X axis direction, Fig. 19) of one of the first lifetime adjustment regions provided in the transistor portion that is closest to the diode portion (see 112 rejection above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 13 and 14 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Naito US 2019/0326118.
Regarding claim 4, Naito teaches the semiconductor device according to claim 1 as discussed above.
Naito does not explicitly teach wherein in a top view, a first area of the first lifetime adjustment region provided in the diode portion is 40% or less of an area of the diode portion.
Naito, however, recognizes wherein in a top view, a first area (e.g., first area of 74 having the distance C in 80, Fig. 12, Fig. 13) of the first lifetime adjustment region provided in the diode portion is smaller than an area of the diode portion (e.g., area of 80 having the width WF, Fig. 12, Fig. 14), which overlaps the claimed range. It would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to the device of Naito to have the claimed range, since it has been held that where the claimed range overlaps or lies inside ranges disclosed by the prior art, a prima facie case of obviousness exists. MPEP § 2144.05.
Regarding claim 13, Naito teaches the semiconductor device according to claim 1 as discussed above.
Naito does not explicitly teach wherein a length, in the first direction, of the first lifetime adjustment region provided in the transistor portion is twice or less of a thickness of the semiconductor substrate in a depth direction and is smaller than a length of the transistor portion in the first direction.
Naito, however, recognizes that the length of the lifetime adjustment region may be larger than the thickness of the semiconductor substrate, which leads to easily generating holes in the drift region to recombine with electrons, thereby suppressing switching loss of the transistor portions (e.g., [144]). In other words, the ratio relationship between the length of the first lifetime adjustment region and the thickness of the semiconductor substrate is a result-effective variable for varying the degree of suppressing switching loss for example. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to control and optimize the device of Naito to have the claimed ratio relationship through routine experimentation and optimization. MPEP 2144.05. Also, Applicant has not disclosed that the claimed ratio relationship is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical.
Regarding claim 14, Naito teaches the semiconductor device according to claim 1 as discussed above.
Naito does not explicitly teach wherein the first lifetime adjustment region is provided in a whole of the transistor portion in the first direction.
Naito, however, recognizes that the length of the lifetime adjustment region may be larger than the thickness of the semiconductor substrate, which leads to easily generating holes in the drift region to recombine with electrons, thereby suppressing switching loss of the transistor portions (e.g., [144]). In other words, the length of the first lifetime adjustment region and/or its ratio relationship with the thickness of the semiconductor substrate is a result-effective variable for varying the degree of suppressing switching loss for example. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to control and optimize the device of Naito to have the claimed length through routine experimentation and optimization. MPEP 2144.05. Also, Applicant has not disclosed that the claimed length is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical.
Allowable Subject Matter
Claims 8, 9, 11, 12, 15-17 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if amended to overcome the claim objection above.
Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if amended to overcome the claim objection above.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 April 17, 2026
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