DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on June 26, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Objections
Claims 25, 29 and 31 are objected to because of the following informalities:
In claim 25, lines 7-10, “a first lifetime adjustment region of the transistor portion and a first lifetime adjustment region of the diode portion, … has a density of lattice defects that is a first defect density” should read --a first lifetime adjustment region of the transistor portion and a first lifetime adjustment region of the diode portion, … have a density of lattice defects that is a first defect density-- (emphasis added).
In claim 29, lines 2-3, “the another lifetime adjustment region of the diode portion” should read --another lifetime adjustment region of the diode portion--.
In claim 31, lines 2-3, “the another lifetime adjustment region of the diode portion” should read --another lifetime adjustment region of the diode portion--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 13 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Yoshida US 2019/0096989.
Regarding claim 1, Yoshida teaches a semiconductor device (e.g., Figs. 13-14, [170]-[173]; also see Figs. 1-5, Fig. 6, Fig. 8 and Figs. 11-12, and the descriptions thereof for additional details) which includes a semiconductor substrate (e.g.,10, Fig. 14) having an upper surface (e.g., 21, Fig. 14) and a lower surface (e.g., 23, Fig. 14), the semiconductor comprising:
a transistor portion (e.g., 70 and 90, Fig. 14) which is provided in the semiconductor substrate;
a diode portion (e.g., 80, Fig. 14) which is provided in the semiconductor substrate side by side with the transistor portion in a first direction (e.g., X-axis direction, Fig. 14); and
a first lifetime adjustment region (e.g., 92(T), [173], [87], [121], [155]; see the annotated Figs. 13-14 below) which is provided at a first depth (e.g., first depth of 92(T), see the annotated Figs. 13-14 below) on an upper surface side of the semiconductor substrate, has a density of lattice defects (e.g., [87], [124]) that is a first defect density, and includes a region provided in the transistor portion (e.g., Fig. 14), wherein
the upper surface side is a region from a central position of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate (e.g., [87], [121], [155]), wherein
the transistor portion includes:
one or more emitter regions (e.g., 12 (N+), Figs. 13-14) of a first conductivity type which are provided on the upper surface of the semiconductor substrate;
one or more contact regions (e.g., 15 (P+), Figs. 13-14, [81]) of a second conductivity type which are provided on the upper surface of the semiconductor substrate; and
a collector region (e.g., 22 (P+), Fig. 14) of the second conductivity type which is provided on the lower surface of the semiconductor substrate,
the diode portion includes a cathode region (e.g., 82 (N+), Fig. 14) of the first conductivity type which is provided on the lower surface of the semiconductor substrate, and
a first length in the first direction by which the first lifetime adjustment region is provided in the diode portion is 0 (e.g., see the annotated Figs. 13-14 below), or is smaller than a second length in the first direction by which the first lifetime adjustment region is not provided in the diode portion.
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Annotated Fig. 13 of Yoshida
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Annotated Fig. 14 of Yoshida
Regarding claim 2, Yoshida teaches the semiconductor device according to claim 1, wherein in a top view, a first area of the first lifetime adjustment region provided in the diode portion is 0 (e.g., see the annotated Figs. 13-14 above), or is smaller than a second area of a region in the diode portion where the first lifetime adjustment region is not provided.
Regarding claim 3, Yoshida teaches the semiconductor device according to claim 1, wherein the first length is 40% or less of a length of the diode portion in the first direction (e.g., first length is 0; see the discussion to claim 1 above).
Regarding claim 4, Yoshida teaches the semiconductor device according to claim 1, wherein in a top view, a first area of the first lifetime adjustment region provided in the diode portion is 40% or less of an area of the diode portion (e.g., first area is 0; see the discussion to claim 2 above).
Regarding claim 5, Yoshida teaches the semiconductor device according to claim 1, wherein the first length (e.g., first length is 0; see the discussion to claim 1 above) is smaller than a third length, in the first direction, of the first lifetime adjustment region provided in the transistor portion (e.g., third length of 92(T); see the annotated Figs. 13-14 above).
Regarding claim 6, Yoshida teaches the semiconductor device according to claim 1, wherein in a top view, a first area of the first lifetime adjustment region provided in the diode portion (e.g., first area is 0; see the annotated Figs. 13-14 above) is smaller than a third area of the first lifetime adjustment region provided in the transistor portion (e.g., third area of 92(T); see the annotated Figs. 13-14 above).
Regarding claim 7, Yoshida teaches the semiconductor device according to claim 1, wherein the diode portion has a plurality of trench portions (e.g., 30, Fig. 14; Fig. 1, Fig. 2; Fig. 12; Fig. 14 shows the region similar to the region 130 of Fig. 1, therefore, the diode portion 80 includes a plurality of trench portions 30, each arranged between corresponding two of the plurality of mesa portions 94-2 (not labeled in Fig. 14; see Fig. 12)) provided from the upper surface to an inside of the semiconductor substrate and arranged side by side in the first direction, the diode portion has a plurality of mesa portions (e.g., 94-2; see the discussion above), each of which is arranged between corresponding two of the plurality of trench portions in the first direction, and the diode portion has, below at least two of the plurality of mesa portions arranged adjacent to each other in the first direction, a region in which the first lifetime adjustment region is not provided (e.g., a region of 94-2 (not labeled in Fig. 14; see Fig. 12) does not overlap 92; Fig. 14).
Regarding claim 13, Yoshida teaches the semiconductor device according to claim 1, wherein a length, in the first direction, of the first lifetime adjustment region provided in the transistor portion is twice or less of a thickness of the semiconductor substrate in a depth direction and is smaller than a length of the transistor portion in the first direction (e.g., see the annotated Figs. 13-14 above).
Claims 1, 10 and 11 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Yoshida US 2019/0096989 (an alternative interpretation used in rejection).
Regarding claim 1, Yoshida teaches a semiconductor device (e.g., Figs. 13-14, [170]-[173]; also see Figs. 1-5, Fig. 6, Fig. 8 and Figs. 11-12, and the descriptions thereof for additional details) which includes a semiconductor substrate (e.g.,10, Fig. 14) having an upper surface (e.g., 21, Fig. 14) and a lower surface (e.g., 23, Fig. 14), the semiconductor comprising:
a transistor portion (e.g., 70 and 90, Fig. 14) which is provided in the semiconductor substrate;
a diode portion (e.g., 80, Fig. 14) which is provided in the semiconductor substrate side by side with the transistor portion in a first direction (e.g., X-axis direction, Fig. 14); and
a first lifetime adjustment region (e.g., 92(B), [173], [87], [121], [155]; see the annotated Figs. 13-14 below) which is provided at a first depth (e.g., first depth of 92(T), see the annotated Figs. 13-14 below) on an upper surface side of the semiconductor substrate, has a density of lattice defects (e.g., [87], [124]) that is a first defect density, and includes a region provided in the transistor portion (e.g., Fig. 14), wherein
the upper surface side is a region from a central position of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate (e.g., [87], [121], [155]), wherein
the transistor portion includes:
one or more emitter regions (e.g., 12 (N+), Figs. 13-14) of a first conductivity type which are provided on the upper surface of the semiconductor substrate;
one or more contact regions (e.g., 15 (P+), Figs. 13-14, [81]) of a second conductivity type which are provided on the upper surface of the semiconductor substrate; and
a collector region (e.g., 22 (P+), Fig. 14) of the second conductivity type which is provided on the lower surface of the semiconductor substrate,
the diode portion includes a cathode region (e.g., 82 (N+), Fig. 14) of the first conductivity type which is provided on the lower surface of the semiconductor substrate, and
a first length in the first direction by which the first lifetime adjustment region is provided in the diode portion is 0 (e.g., see the annotated Figs. 13-14 below), or is smaller than a second length in the first direction by which the first lifetime adjustment region is not provided in the diode portion.
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Annotated Fig. 13 of Yoshida
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Annotated Fig. 14 of Yoshida
Regarding claim 10, Yoshida teaches the semiconductor device according to claim 1, wherein the transistor portion has a boundary region (e.g., 90, Figs. 13-14) adjacent to the diode portion in the first direction, the boundary region has at least one of the one or more contact regions (e.g., 15, Figs. 13-14), and the collector region (e.g., 22, Fig. 14), and does not have the one or more emitter regions, and the first lifetime adjustment region is provided in the boundary region (e.g., see the annotated Figs. 13-14 above).
Regarding claim 11, Yoshida teaches the semiconductor device according to claim 10, wherein the first lifetime adjustment region is not provided in the transistor portion other than the boundary region (e.g., see the annotated Figs. 13-14 above).
Claims 18 and 19 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Yoshida US 2019/0096989 (another alternative interpretation used in rejection).
Regarding claim 18, Yoshida teaches a semiconductor device substrate (e.g., Figs. 13-14, [170]-[173]; also see Figs. 1-5, Fig. 6, Fig. 8 and Figs. 11-12, and the descriptions thereof for additional details) which includes a semiconductor substrate (e.g.,10, Fig. 14) having an upper surface (e.g., 21, Fig. 14) and a lower surface (e.g., 23, Fig. 14), the semiconductor device comprising:
a transistor portion (e.g., 70 and 90, Fig. 14) which is provided in the semiconductor substrate;
a diode portion (e.g., 80, Fig. 14) which is provided in the semiconductor substrate side by side with the transistor portion in a first direction (e.g., X-axis direction, Fig. 14); and
a first lifetime adjustment region (e.g., 92, Fig. 14; [173], [87], [121], [155]) which is provided at a first depth (e.g., first depth of 92, Fig. 14) on an upper surface side of the semiconductor substrate and has a density of lattice defects (e.g., [87], [124]) that is a first defect density, wherein
the upper surface side is a region from a central position of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate (e.g., [87], [121], [155]), wherein
the transistor portion includes:
one or more emitter regions (e.g., 12 (N+), Figs. 13-14) of a first conductivity type which are provided on the upper surface of the semiconductor substrate;
one or more contact regions (e.g., 15 (P+), Figs. 13-14, [81]) of a second conductivity type which are provided on the upper surface of the semiconductor substrate; and
a collector region (e.g., 22 (P+), Fig. 14) of the second conductivity type which is provided on the lower surface of the semiconductor substrate,
the diode portion includes a cathode region (e.g., 82 (N+), Fig. 14) of the first conductivity type which is provided on the lower surface of the semiconductor substrate, and
a first length in the first direction by which the first lifetime adjustment region is provided in the diode portion (e.g., first length of 92 in 80, Fig. 14) is 0, or is smaller than a total value of third lengths, in the first direction, of first lifetime adjustment regions (e.g., third lengths of 92 in 70, Fig. 14), each being identical to the first lifetime adjustment region, provided in the transistor portion.
Regarding claim 19, Yoshida teaches the semiconductor device according to claim 18, wherein the total value of the third lengths is smaller than a length of the transistor portion in the first direction (e.g., Fig. 14).
Claims 20-24 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Yoshida US 2019/0096989 (still another alternative interpretation used in rejection).
Regarding claim 20, Yoshida teaches a semiconductor device (e.g., Figs. 13-14, [170]-[173]; also see Figs. 1-5, Fig. 6, Fig. 8 and Figs. 11-12, and the descriptions thereof for additional details) which includes a semiconductor substrate (e.g.,10, Fig. 14) having an upper surface (e.g., 21, Fig. 14) and a lower surface (e.g., 23, Fig. 14), the semiconductor device comprising:
a transistor portion (e.g., 70 and 90, Fig. 14) which is provided in the semiconductor substrate;
a diode portion (e.g., 80, Fig. 14) which is provided in the semiconductor substrate side by side with the transistor portion in a first direction (e.g., X-axis direction, Fig. 14); and
a first lifetime adjustment region (e.g., 92; [173], [87], [121], [155]; Fig. 14) which is provided at a first depth (e.g., first depth of 92; Fig. 14) on an upper surface side of the semiconductor substrate, has a density of lattice defects (e.g., [87], [124]) that is a first defect density, and includes a region provided in the transistor portion (e.g., Fig. 14), wherein
the upper surface side is a region from a central position of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate (e.g., [87], [121], [155]), wherein
the transistor portion includes:
one or more emitter regions (e.g., 12 (N+), Figs. 13-14) of a first conductivity type which are provided on the upper surface of the semiconductor substrate;
one or more contact regions (e.g., 15 (P+), Figs. 13-14, [81]) of a second conductivity type which are provided on the upper surface of the semiconductor substrate; and
a collector region (e.g., 22 (P+), Fig. 14) of the second conductivity type which is provided on the lower surface of the semiconductor substrate,
the diode portion includes a cathode region (e.g., 82 (N+), Fig. 14) of the first conductivity type which is provided on the lower surface of the semiconductor substrate,
the diode portion has a plurality of trench portions (e.g., 30, Fig. 14; Fig. 1, Fig. 2; Fig. 12; Fig. 14 shows the region similar to the region 130 of Fig. 1, therefore, the diode portion 80 includes a plurality of trench portions 30, each arranged between corresponding two of the plurality of mesa portions 94-2 (not labeled in Fig. 14; see Fig. 12)) provided from the upper surface to an inside of the semiconductor substrate and arranged side by side in the first direction,
the diode portion has a plurality of mesa portions (e.g., 94-2; see the discussion above), each of which is arranged between corresponding two of the plurality of trench portions in the first direction (see the discussion above), and
the diode portion has, below at least two of the plurality of mesa portions arranged adjacent to each other in the first direction, a region in which the first lifetime adjustment region is not provided (e.g., a region of 94-2 (not labeled in Fig. 14; see Fig. 12) does not overlap 92; Fig. 14).
Regarding claim 21, Yoshida teaches the semiconductor device according to claim 20, wherein a total value of third lengths, in the first direction, of first lifetime adjustment regions (e.g., 92, Fig. 14), each being identical to the first lifetime adjustment region, provided in the transistor portion is smaller than a length of the transistor portion in the first direction (e.g., Fig. 14).
Regarding claim 22, Yoshida teaches the semiconductor device according to claim 1, wherein the first depth is positioned on the upper surface side with respect to an intermediate depth position of the semiconductor substrate in a depth direction (e.g., [87], [121], [155]).
Regarding claim 23, Yoshida teaches the semiconductor device according to claim 1, wherein the first lifetime adjustment region (e.g., 92, Figs. 13-14) includes a region (e.g., a region between two broken lines defining the boundary of 92 in 15(1); see the annotated Fig. 13 below) which is arranged below one of the one or more contact regions (e.g., 15(1), see the annotated Fig. 13 below) that is closest to the diode portion in the first direction.
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Annotated Fig. 13 of Yoshida
Regarding claim 24, Yoshida teaches the semiconductor device according to claim 1, wherein the first lifetime adjustment region (e.g., 92, Figs. 13-14) of the transistor portion is not arranged in at least part of a region (e.g., a region between two 30 in 15(1); see the annotated Fig. 13 above) which is below one of the one or more contact regions (e.g., 15(1), see the annotated Fig. 13 above) that is closest to the diode portion.
Claims 25-28 and 33 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Yoshida US 2019/0096989 (still another alternative interpretation used in rejection).
Regarding claim 25, Yoshida teaches a semiconductor device (e.g., Figs. 13-14, [170]-[173]; Figs. 11-12, [164]-[169]; also see Figs. 1-5, Fig. 6 and Fig. 8, and the descriptions thereof for additional details) which includes a semiconductor substrate (e.g., 10, Fig. 14, [53]) having an upper surface (e.g., 21, Fig. 14) and a lower surface (e.g., 23, Fig. 14), the semiconductor device comprising:
a transistor portion (e.g., 70 and 90, Fig. 14) which is provided in the semiconductor substrate;
a diode portion (e.g., 80, Fig. 14) which is provided in the semiconductor substrate side by side with the transistor portion in a first direction (e.g., X-axis direction, Fig. 14); and
a first lifetime adjustment region (e.g., 92 in 70 and 90, [87], Fig. 14) of the transistor portion and a first lifetime adjustment region (e.g., 92 in 80, Fig. 14) of the diode portion, provided at a first depth (e.g., first depth of 92; Fig. 14) on an upper surface side of the semiconductor substrate and has a density of lattice defects (e.g., [87], [124]) that is a first defect density, wherein
the first lifetime adjustment region of the transistor portion is not provided in the diode portion (e.g., Fig. 14), and
the first lifetime adjustment region of the transistor portion and the first lifetime adjustment region of the diode portion are separate from each other (e.g., Fig. 14).
Regarding claim 26, Yoshida teaches the semiconductor device according to claim 25, wherein the transistor portion includes: one or more emitter regions (e.g., 12 (N+), Figs. 13-14) of a first conductivity type which are provided on the upper surface of the semiconductor substrate; one or more contact regions (e.g., 15 (P+), Figs. 13-14, [81]) of a second conductivity type which are provided on the upper surface of the semiconductor substrate; and a collector region (e.g., 22 (P+), Fig. 14) of the second conductivity type which is provided on the lower surface of the semiconductor substrate, and the first lifetime adjustment region of the transistor portion includes a region arranged below each of the one or more contact regions (e.g., 15, Figs. 13-14).
Regarding claim 27, Yoshida teaches the semiconductor device according to claim 26, wherein the first lifetime adjustment region (e.g., 92, Figs. 13-14) of the transistor region includes a region (e.g., a region between two broken lines defining the boundary of 92 in 15(1); see the annotated Fig. 13 below) which is arranged below one of the one or more contact regions (e.g., 15(1), see the annotated Fig. 13 below) that is closest to the diode portion in the first direction.
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Annotated Fig. 13 of Yoshida
Regarding claim 28, Yoshida teaches the semiconductor device according to claim 26, wherein the first lifetime adjustment region (e.g., 92, Figs. 13-14) of the transistor portion is not arranged in at least part of a region (e.g., a region between two 30 in 15(1); see the annotated Fig. 13 above) which is below one of the one or more contact regions that is closest to the diode portion (e.g., 15(1), see the annotated Fig. 13 above).
Regarding claim 33, Yoshida teaches the semiconductor device according to claim 25, wherein the upper surface side is a region from a central position of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate (e.g., [87], [121], [155]).
Response to Arguments
Applicant's arguments filed on July 21, 2026 have been fully considered but are moot in view of the new ground(s) of rejection as stated above.
Allowable Subject Matter
Claims 8, 9, 12 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 29-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if amended to overcome the claim objection above.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention. For example, Kouno US 2017/0084610 relates to a semiconductor device including a lifetime adjustment region which is provided at a depth in the semiconductor substrate and has a density of lattice defects.
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a) . Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a) .
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
If applicant should desire to file an amendment, entry of a proposed amendment after final rejection cannot be made as a matter of right unless it merely cancels claims or complies with a formal requirement made earlier. Amendments touching the merits of the application which otherwise might not be proper may be admitted upon a showing a good and sufficient reasons why they are necessary and why they were not presented earlier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 August 18, 2026
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