Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I in the reply filed on June 3, 2026, is acknowledged.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 3, 2026.
Drawings
The drawings are objected to because, in Figs. . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The abstract of the disclosure is objected to because there is an extra instance of "a" in line 2 ("a first bump structure a"). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities: in paragraph [.
Appropriate correction is required.
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Fig. 1 of Yu, reproduced with annotations added by the examiner.
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Fig. 3 of Yu, reproduced with annotations added by the examiner.
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Fig. 4 of Yu, reproduced with annotations added by the examiner.
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Figs. 1A and 1B of Huang, reproduced above with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et. al., Pub. No. US 2021/0288040, hereafter referred to as Yu, in view of Huang et. al., Pub. No. US 2022/0165675, hereafter referred to as Huang, and Sun et. al., Pub. No. US 2023/0384367, hereafter referred to as Sun.
Regarding claim 1, Yu teaches “A method comprising: forming an interconnect structure over a first substrate” (Yu [0017]; Fig. 1, reproduced above with annotations added by the examiner, interconnect structure 28), “the interconnect structure comprising a top metal layer including a first conductive line” (Yu [0019]: “Interconnect structure 28 may further include a plurality of dielectric layers (not shown) over the ILD and the contact plugs. Metal lines and vias (not shown) are formed in the dielectric layers (also referred to as Inter-Metal Dielectrics (IMDs)).”; Fig. 1, interconnect structure 28); “depositing a pad structure over the first conductive line” (Yu [0020]; Fig. 1, probe pads 36); “depositing a first bump structure to cover the pad structure” (Yu [0021]; Fig. 1, solder regions 38); and “performing a testing operation on at least one of the pad structure and the first bump structure” (Yu [0022]: “Further referring to FIG. 1, device dies 22 are probed, for example, by putting the pins of probe card 40 into contact with solder regions 38.”; Fig. 1, solder regions 38 and probe card 40).
Yu, however, does not teach “(performing a testing operation) to leave a probing mark on an upper surface of the at least one of the pad structure and the first bump structure; and in response to a testing result of the testing operation as complying with a testing performance, performing an operation to recover the upper surface through eliminating the probing mark.” More specifically, Yu does not explicitly teach that the testing operation leaves marks on the surfaces of the solder regions, and thus also does not teach any method of removing said marks.
Huang, on the other hand, does teach “(performing a testing operation) to leave a probing mark on an upper surface of the at least one of the pad structure and the first bump structure” (Huang [0016]: “After performing the wafer-level chip probing process, testing marks (e.g., indentation) resulted from the probe pins of the probe cards PC1 may occur on top surfaces of the solder material layers 140.”; Fig. 1B, reproduced above with annotations added by the examiner, probe cards PC1, solder material layers 140).
The teaching of Huang that the testing operation leaves a probing mark on the upper surfaces of the bump structures can be incorporated into the process of Yu as the testing operation of Yu leaving a similar probing mark on the bump structures.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application that the testing operation of Yu would leave probing marks on the bump structures as taught by Huang because it is well known that contact with an object with sufficient force will deform or damage it and it would be a simple combination of the two disclosures.
The combination of Yu and Huang just described, however, does not teach “and in response to a testing result of the testing operation as complying with a testing performance, performing an operation to recover the upper surface through eliminating the probing mark.”
Sun, on the other hand, teaches that damage done to a solder bump by a testing probe can be repaired by reflowing the solder (Sun [0039]: “Note that probing may take place on the test bumps 350. Since the test bumps 350 are formed from solder, this allows probe-on-solder contact. Since solder is malleable, probe with flat tip may be used, which reduces damage to the test bumps 350. Also, any damage to the test bumps 350 may be fixed or at least mitigated through solder reflow, which can reshape the test bumps 350.”; Figs. 3A and 3B, reproduced above with annotations added by the examiner, test bumps 350).
The reflowing of solder taught by Sun can be incorporated into the combined process of Yu and Huang as a step of repairing the marks left on the bump structures by the testing probes by reflowing the solder. The combined process just described teaches “and in response to a testing result of the testing operation as complying with a testing performance, performing an operation to recover the upper surface through eliminating the probing mark” (Sun [0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include a step of repairing the probing marks on the bump structures in the combined process of Wu and Huang by reflowing the solder as taught by Sun because it would eliminate the need to remove the solder by etching (see Yu [0023]: “…after the probing process, solder regions 38 are removed through etching in accordance with some embodiments.”) and it would be a simple combination of the disclosures.
Regarding claim 2, the combination of Yu, Huang, and Sun described in the discussion of claim 1 further teaches “The method of Claim 1, wherein the pad structure includes a plurality of conductive pads connected to the first conductive line” (Yu [0015]; Fig. 1, probe pads 36) “and exposed through the interconnect structure” (Yu Fig. 1; note that the probe pads 36 are connected to the interconnect structure 28 and are not completely buried underneath it).
Regarding claim 7, the combination of Yu, Huang, and Sun described in the discussion of claim 1 further teaches “The method of Claim 1, wherein the performing of the testing operation comprises causing a probing needle to contact the first bump structure” (Yu [0022]; Fig. 1, solder regions 38 and probe card 40) “and leave the probing mark on the upper surface of the first bump structure” (Huang [0016]).
Regarding claim 8, the combination of Yu, Huang, and Sun as applied to claim 1 further teaches “The method of Claim 7, wherein the performing of the operation to eliminate the probing mark comprises performing a reflow operation on the first bump structure to recover the upper surface of the first bump structure” (Sun [0039]).
Regarding claim 9, the combination of Yu, Huang, and Sun as applied to claim 1 further teaches “The method of Claim 8, wherein the operation to eliminate the probing mark further comprises performing a bonding operation to bond a second bump structure to a second substrate” (Yu [0020]: “On the other hand, bonding pads 32 are used for bonding to package component 122 (FIG. 4).” and [0021]; Fig. 1, solder regions 34; Fig. 4, reproduced above with annotations added by the examiner, bonding pads 32 and package component 122) “while keeping the first bump structure spaced apart from the second substrate” (Yu Fig. 1; note that the solder regions 38 disposed on the probe pads 36 are spaced apart from the solder regions 34 disposed on the bonding pads 32).
Regarding claim 10, the combination of Yu, Huang, and Sun described in the discussion of claim 1 teaches “The method of Claim 1”, but does not teach “wherein the pad structure comprises aluminum”. The combined device, however, does teach that the pad structure can be a metal (Yu [0021]: “The plated bond pads 32 and probe pads 36 may include copper, nickel, palladium, or composite layers thereof.”).
Huang, on the other hand, does teach “wherein the pad structure comprises aluminum” (Huang [0014]: “The topmost interconnect wirings may include conductive pads 122, and the conductive pads 122 may be aluminum pads…”; Figs. 1A, reproduced above with annotations added by the examiner, and 1B, conductive pads 122).
The aluminum conductive pads of Huang can be incorporated into the combined process of Yu, Huang, and Sun described in the discussion of claim 1 by making the bond and probe pads 32 and 36 of Yu out of aluminum.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to make the bond and probe pads of Yu out of aluminum as taught by Huang because aluminum can also serve as a conductive material for the pads and it would be a simple substitution of one element for another.
Regarding claim 11, the combination of Yu, Huang, and Sun described in the discussion of claim 1 further teaches “The method of Claim 1, wherein the first bump structure comprises a solder material” (Yu [0021]; Fig. 1, solder regions 38).
Regarding claim 12, the combination of Yu, Huang, and Sun described in the discussion of claim 1 further teaches “The method of Claim 1, wherein the first bump structure is in direct contact with the pad structure” (Yu Fig. 1; note that the solder regions 38 are in direct contact with the probe pads 36).
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Fig. 4C of Wu.
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Figs. 5A-5C of Wu, reproduced with annotations added by the examiner.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, Huang, and Sun as applied to claims 1-2 above, and further in view of Wu et. al., Pub. No. US 2015/0362526, hereafter referred to as Wu.
Regarding claim 3, the combination of Yu, Huang, and Sun as applied to claim 1 teaches “The method of Claim 2, wherein the plurality of conductive pads are spaced apart from each other” (Yu Fig. 1; note that the probe pads 38 are spaced apart from one another), but does not teach “and distributed in a ring shape.”
Wu, on the other hand, teaches bump pads that are distributed in a ring shape (Wu [0029]; Fig. 4C, reproduced above with annotations added by the examiner; note that the bump pads 461-466 are distributed in a ring shape in subfigures (b), (c), and (f)).
The ring-shaped arrangement of the bump pads can be incorporated into the combined process of Yu, Huang, and Sun as applied to claim 1 as a ring-shaped arrangement of the probe pads 38 of Yu.
It would have been obvious to one of ordinary skill in the art to use a ring-shaped arrangement of probe pads as suggested by Wu in the combined process of Yu, Huang, and Sun because doing so would save space on the substrate compared to a linear arrangement and it would have been a simple combination of elements of the disclosures.
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Fig. 4 of Park, reproduced with annotations added by the examiner.
Claims 1 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Yu and Park et. al., Pub. No. US 2023/0005853, hereafter referred to as Park.
Regarding claim 1, Wu teaches “A method comprising: forming an interconnect structure over a first substrate” (Wu [0034]; Figs. 5A-5C, reproduced above with annotations added by the examiner, reproduced above with annotations added by the examiner, substrate 505 and interconnects 523 and 524), “depositing a pad structure over the first conductive line” (Wu [0034]; Figs. 5A-5C, metal pad 530); “depositing a first bump structure to cover the pad structure” (Wu [0036]; Fig. 5C, microbumps 580); and “performing a testing operation on at least one of the pad structure and the first bump structure” (Wu [0035]: “FIG. 5A shows a probe 550 touching the test pad region 510.”; Fig. 5A, probe 550 and test pad region 510) “to leave a probing mark on an upper surface of the at least one of the pad structure and the first bump structure” (Wu [0035]: “The probing causes damage (see region 555) on the surface of the test pad region 510.”; Fig. 5B, region 555); but does not teach “the interconnect structure comprising a top metal layer including a first conductive line” and “and in response to a testing result of the testing operation as complying with a testing performance, performing an operation to recover the upper surface through eliminating the probing mark.”
Yu, on the other hand, does teach “the interconnect structure comprising a top metal layer including a first conductive line” (Yu [0019]; Fig. 1, interconnect structure 28).
The metallic interconnect structure of Yu can be incorporated into the device of Wu by making the interconnects of Wu out of metal.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to make the interconnects of Wu out of metal as taught by Yu because doing so would make the interconnects conductive and thus capable of serving as interconnects and it would be a simple substitution of one element for another.
However, the combination of Wu and Yu just described does not teach “and in response to a testing result of the testing operation as complying with a testing performance, performing an operation to recover the upper surface through eliminating the probing mark.”
Park, on the other hand, teaches the formation of a conductive layer on top of a test pad damaged by contact with a probing needle (Park [0037]: “In the process of allowing the probe to be in contact with the test pad 251, the probe may leave a mark, e.g., a scratch, on the surface of the test pad 251.”, [0040]: “FIGS. 4 and 5 are diagrams illustrating modified examples of the test pad 251 illustrated in FIG. 3.”, [0041], [0063]: “The bonding layer 1252 may be formed by depositing… a conductive material. For example… the conductive material may be one of copper, nickel, gold, silver, or alloys thereof.”; Fig. 4, reproduced above with annotations added by the examiner, test pad 1251 and bonding layer 1252).
The step of forming a conductive layer to repair damage due to a test probe taught by Park can be incorporated into the process of Wu as a similar step of forming a conductive layer on the test pad. The combined process of Wu, Yu, and Park just described teaches “and in response to a testing result of the testing operation as complying with a testing performance, performing an operation to recover the upper surface through eliminating the probing mark” (Park [0041] and [0063]; Fig. 4, test pad 1251 and bonding layer 1252; note that the forming of the bonding layer on the damaged test pad is being interpreted as a means for eliminating the probing mark).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include a step of forming a conductive layer as taught by Park on top of the test pad of Wu because doing so would provide an undamaged surface that further electrical contacts can be formed on and it would be a simple combination of the two disclosures.
Regarding claim 4, the combination of Wu, Yu, and Park described in the discussion of claim 1 further teaches “The method of Claim 1, wherein the performing of the testing operation comprises causing a probing needle to contact the pad structure” (Wu [0035]: “FIG. 5A shows a probe 550 touching the test pad region 510.”; Fig. 5A, probe 550 and test pad region 510) “and leave the probing mark on the upper surface of the pad structure” (Wu [0035]: “The probing causes damage (see region 555) on the surface of the test pad region 510.”; Fig. 5B, region 555).
Regarding claim 5, the combination of Wu, Yu, and Park as applied to claim 1 further teaches “The method of Claim 4, wherein the performing of the operation to eliminate the probing mark comprises forming a conductive plug structure to cover the probing mark” (Park [0041] and [0063]; Fig. 4, test pad 1251 and bonding layer 1252).
Regarding claim 6, the combination of Wu, Yu, and Park as applied to claim 1 further teaches “The method of Claim 5, wherein the conductive plug structure comprises a first conductive layer directly over the pad structure” (Park [0041] and [0063]; Fig. 4, test pad 1251 and bonding layer 1252), but does not teach “and the pad structure is formed of a material same as the first conductive layer.”
Yu, on the other hand, teaches that both the interconnect structure and the bond and probe pads may be made of copper (Yu [0019]: “In accordance with some embodiments of the present disclosure, interconnect structure 28 includes a plurality of metal layers, each including a plurality of metal lines at the same level. … The metal lines and vias may be formed of copper…” and [0021]: “The plated bond pads 32 and probe pads 36 may include copper…”; Fig. 1, interconnect structure 28 and probe pads 36).
The disclosure of copper as a material for both the interconnect structure and the probe pads of Yu can be incorporated into the combined process of Wu, Yu, and Park as applied to claim 1 by making both the interconnect and the metal pad of said combined process out of copper. The combined process just described teaches “and the pad structure is formed of a material same as the first conductive layer”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to make the interconnect and metal pad of the combined process of Wu, Yu, and Park as applied to claim 1 out of copper as taught by Yu because copper can serve as a suitable conductive material for the interconnects and a suitable metal for the metal pad and it would be a simple substitution of one material for another.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Huang.
Regarding claim 13, Yu teaches “A method comprising: forming a first interconnect structure over a first substrate” (Yu [0017]; Fig. 1, interconnect structure 28), “the first interconnect structure comprising a top metal layer including a first conductive line” (Yu [0015] and [0019]; Fig. 1, portion of interconnect structure 28 disposed under the probe pads 36) “and a second conductive line” (Yu [0015] and [0019]; Fig. 1, portion of interconnect structure 28 disposed under the bonding pads 32); “depositing a first conductive pad and a second conductive pad over the first conductive line and the second conductive line, respectively” (Yu [0015]; Fig. 1, bonding pads 32 and probe pads 36), “wherein the first conductive pad is configured as a signal pad” (Yu [0020]: “On the other hand, bonding pads 32 are used for bonding to package component 122 (FIG. 4). Accordingly, with bonding pads 32 having a reduced size and a reduced pitch, more bonding pads 32 can be allocated, and hence more signal paths can be established between device die 22 and package component 122.”), “and the second conductive pad is configured as a testing pad” (Yu [0020]: “In accordance with some embodiments, probe pads 36 are used for probing (testing the function of) integrated circuit devices 26.”); “providing a first conductive bump and a second conductive bump to cover the first conductive pad and the second conductive pad, respectively” (Yu [0021]; Fig. 1, note that the solder regions 34 and 38 are formed on top of the bonding pads 32 and probe pads 36, respectively); “performing a testing operation on the second conductive pad or the second conductive bump” (Yu [0022]; Fig. 1, probe cards 40, solder regions 38 on top of the probe pads 36); “and in response to a testing result of the testing operation as complying with a testing performance, bonding the first substrate to a second substrate through joining the first conductive bump to a third conductive pad of the second substrate” (Yu [0020]: “On the other hand, bonding pads 32 are used for bonding to package component 122 (FIG. 4).”, [0025]: “Device dies 122 are probed, for example, using probe card 140, so that defective device dies 122 are found, and known-good-dies are determined. The probing is performed on each of device dies 122.”, and [0026]: “Next, referring to FIG. 4, the known-good-dies 122 are bonded to the known-good-dies 22 in wafer 20.”; Fig. 1, wafer 20, device die 22, and solder regions 34; Fig. 3, reproduced above with annotations added by the examiner, probe card 140 and device dies 122; Fig. 4, bonding pads 32 and device die 122), “wherein the second conductive bump is left spaced apart from the second substrate after the bonding” (Yu Fig. 1; note that the solder regions 38 disposed on the probe pads 36 are spaced apart from the solder regions 34 disposed on the bonding pads 32).
Yu, however, does not teach “(performing a testing operation) to leave a probing mark on a surface of the respective second conductive pad or the second conductive bump” by not explicitly teaching that the testing procedure leaves marks on the solder regions 38.
Huang, on the other hand, does teach “(performing a testing operation) to leave a probing mark on a surface of the respective second conductive pad or the second conductive bump” (Huang [0016]; Fig. 1B, probe cards PC1, solder material layers 140).
The teaching of Huang that the testing operation leaves a probing mark on the upper surfaces of the bump structures can be incorporated into the process of Yu as the testing operation of Yu leaving a similar probing mark on the bump structures.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application that the testing operation of Yu would leave probing marks on the bump structures as taught by Huang because it is well known that contact with an object with sufficient force will deform or damage it and it would be a simple combination of the two disclosures.
Regarding claim 14, the combination of Yu and Huang described in the discussion of claim 13 teaches “The method of Claim 13, wherein… the testing operation is performed on the second conductive bump such that the probing mark is left on an upper surface of the second conductive bump”(Huang [0016]; Fig. 1B, probe cards PC1, solder material layers 140), but does not teach “the first conductive pad and the second conductive pad are formed of an aluminum-based material”.
Huang, on the other hand, teaches conductive pads that are made from aluminum (Huang [0014]; Fig. 1A, conductive pads 122).
The conductive pads made of aluminum of Huang can be incorporated into the combined process of Yu and Huang described in the discussion of claim 13 by making the bonding and probe pads of said combined process out of aluminum.
It would have been obvious to one of ordinary skill in the art to make the bonding and probe pads of the combined process of Yu and Huang described in the discussion of claim 13 out of aluminum because aluminum can serve as a conductive material and it would be a simple substitution of one material for another.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yu and Huang as applied to claims 13-14 above, and further in view of Sun.
Regarding claim 15, the combination of Yu and Huang as applied to claim 13 teaches “The method of Claim 14”, but does not teach “further comprising performing a reflow operation on the first conductive bump and the second conductive bump subsequent to the testing operation.”
Sun, on the other hand, teaches that damage done to a solder bump by a testing probe can be repaired by reflowing the solder (Sun [0039]).
The reflowing of solder taught by Sun can be incorporated into the combined process of Yu and Huang as a step of reflowing the solder making up the solder bumps disposed over the bonding and testing pads. The combined process just described teaches “further comprising performing a reflow operation on the first conductive bump and the second conductive bump subsequent to the testing operation” (Sun [0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include a step of reflowing the solder bumps on both the bonding pads and the probe pads the combined process of Wu and Huang by reflowing the solder as taught by Sun because it would assist in bonding the second substrate onto the bonding pads and eliminate the need to etch away the solder on the probe pads and it would be a simple combination of the disclosures.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yu and Huang as applied to claims 13-14 above, and further in view of Wu.
Regarding claim 16, the combination of Yu and Huang described in the discussion of claim 13 teaches “The method of Claim 13, wherein the first conductive pad and the second conductive pad are formed of copper” (Yu [0021]; Fig. 1, bonding pads 32 and probe pads 36), but does not teach “and the testing operation is performed on the second conductive pad such that the probing mark is left on an upper surface of the second conductive pad.”
Wu, on the other hand, teaches a process in which the probing needle directly contacts the conductive pad (Wu [0035]; Fig. 5A, probe 550 and metal pad 530).
The step of having the probing needle contact the conductive pad taught by Wu can be incorporated into the combined process of Yu and Huang by having the probing needles contact the conductive pads instead of the bump structures.
It would have been obvious to one of ordinary skill in the art to have the probing needles of the combined process of Yu and Huang directly contact the conductive pads as taught by Wu because doing so would create more direct electrical contact between the probing needles and the circuitry being tested and it would have been a simple substitution of one step for another.
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, Huang, and Wu as applied to claim 16 above, and further in view of Park.
Regarding claim 17, the combination of Yu, Huang, and Wu described in the discussion of claim 16 further teaches “The method of Claim 16”, but does not teach “further comprising depositing a first conductive plug stack and a second conductive plug stack on the first conductive pad and the second conductive pad, respectively, to eliminate the probing mark on the second conductive pad.”
Park, on the other hand, teaches the formation of a conductive layer on top of a test pad damaged by contact with a probing needle (Park [0037]; Fig. 4, test pad 1251 and bonding layer 1252).
The step of forming a conductive layer to repair damage due to a test probe taught by Park can be incorporated into the combined process of Yu, Huang, and Wu described in the discussion of claim 16 as a similar step of forming a conductive layer on the bonding and probe pads. The combined process of Yu, Huang, Wu, and Park just described teaches “and in response to a testing result of the testing operation as complying with a testing performance, performing an operation to recover the upper surface through eliminating the probing mark” (Park [0041] and [0063]; Fig. 4, test pad 1251 and bonding layer 1252; note that the forming of the bonding layer on the damaged test pad is being interpreted as a means for eliminating the probing mark).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include a step of forming a conductive layer as taught by Park on top of the bonding and probe pads of the combined process of Yu, Huang, and Wu described in the discussion of claim 16 because doing so would provide an undamaged surface for forming further electrical contacts and it would be a simple combination of the two disclosures.
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Wu.
Regarding claim 21, Yu teaches “A method comprising: forming a first interconnect structure over a first substrate” (Yu [0017]; Fig. 1, interconnect structure 28), “the first interconnect structure comprising a top metal layer including a first conductive line” (Yu [0019]); “forming a first pad structure over the first conductive line” (Yu [0015]; Fig. 1, probe pads 36), “the first pad structure comprising a plurality of first conductive pads connected to the first conductive line” (Yu Fig. 1; note that there are multiple probe pads 36 and that they are connected to the interconnect structure 28), “the first conductive pads configured as testing pads” (Yu [0020]) “and formed of a material different from the first conductive line” (Yu [0019]: “The metal lines and vias may be formed of copper or copper alloys, and they can also be formed of other metals.” and [0021]: “The… probe pads 36 may include… nickel, palladium, or composite layers thereof.”; note that this allows for the probe pads and the metal lines to be formed of different metals); “and forming a first bump structure covering the surface of the first pad structure” (Yu [0021]; solder regions 38), but does not teach “performing a testing operation on at least one of the first conductive pads to leave a probing mark on a surface of the at least one of the first conductive pads”. Yu, however, does teach performing a testing operation on the first bump structure (Yu [0022]; Fig. 1, probe cards 40 and solder regions 38).
Wu, on the other hand, does teach “performing a testing operation on at least one of the first conductive pads to leave a probing mark on a surface of the at least one of the first conductive pads” (Wu [0035]; Fig. 5A, probe 550, metal pad 530, and region 555).
The step of performing a testing operation on a conductive pad and leaving a mark on it can be incorporated into the process of Yu by performing the testing operation on the probe pads instead of the solder bumps.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have performed the testing operation of Yu on the conductive pads as taught by Wu instead of the solder bumps because doing so would create more direct electrical contact between the probing needles and the circuitry being tested and it would have been a simple substitution of one step for another.
Regarding claim 22, the combination of Yu and Wu further teaches “The method of Claim 21, wherein the first bump structure comprises a plurality of conductive bumps formed of a solder material” (Yu [0021]; solder regions 38).
Regarding claim 23, the combination of Yu and Wu further teaches “The method of Claim 21, further comprising performing a bonding operation to bond a second bump structure to a second substrate” (Yu [0020]; Fig. 4, bonding pads 32, solder regions 35, and package component 122) “while keeping the first bump structure spaced apart from the second substrate” (Fig. 4; note that the solder regions 38 are spaced apart from the solder regions 35).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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