DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/5/2024, 12/5/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang (US 2022/0189966).
Regarding claim 1, Jang discloses, in at least figures 2-3 and 5-6 and related text, a semiconductor device, comprising:
a substrate (100, [53]);
active patterns (ACT, [40]) on the substrate (100, [53]) and spaced apart from each other to define active pattern rows (rows of ACTs in D1 direction, figures) in a first direction (D1 direction, figures) parallel to an upper surface of the substrate (100, [53]), the active pattern rows (rows of ACTs in D1 direction, figures) being spaced apart from each other in a second direction (D2 direction, figures) perpendicular to the first direction (D1 direction, figures), and the active patterns (ACT, [40]) extending in a third direction (D3 direction, figures) oblique with respect to the first direction (D1 direction, figures) and aligned in the third direction (D3 direction, figures);
gate structures (110, [52]) in recesses of the active patterns (ACT, [40]), each of the gate structures extending in the first direction (D1 direction, figures);
first contact plugs (120, BC, [48], [73]) electrically connected to opposite edge portions of each of the active patterns (ACT, [40]), respectively, the first contact plugs (120, BC, [48], [73]) being spaced apart from each other in each of the first (D1 direction, figures) and second (D2 direction, figures) directions and aligned in each of the first (D1 direction, figures) and second (D2 direction, figures) directions;
first insulation spacers (150/170, [78], [81]) surrounding sidewalls of the first contact plugs (120, [48], [73]), the first insulation spacers (150/170, [78], [81]) filling spaces between the first contact plugs (120, BC, [48], [73]) in the second direction (D2 direction, figures);
a bit line structure (140ST, [52]) filling an opening extending in the second direction (D2 direction, figures) between the first insulation spacers (150/170, [78], [81]), the bit line structure (140ST, [52]) contacting central portions of the active patterns (ACT, [40]); and
a capacitor (190, [122]) electrically connected to each of the first contact plugs (120, BC, [48], [73]).
Regarding claim 2, Jang discloses the semiconductor device as claimed in claim 1 as described above.
Jang further discloses, in at least figures 2-3 and 5-6 and related text, the active patterns (ACT, [40]) in each of the active pattern rows (rows of ACTs in D1 direction, figures) are aligned in the first direction (D1 direction, figures).
Regarding claim 3, Jang discloses the semiconductor device as claimed in claim 1 as described above.
Jang further discloses, in at least figures 2-3 and 5-6 and related text, the first contact plugs (120, BC, [48], [73]) arranged in the second direction (D2 direction, figures) contact edges of different active patterns (ACT, [40]), respectively, and
one of the first contact plugs (120, BC, [48], [73]) contacting an upper edge of a corresponding one of the active patterns (ACT, [40]) and another of the first contact plugs (120, BC, [48], [73]) contacting a lower edge of a corresponding one of the active patterns (ACT, [40]) are alternately and repeatedly arranged in the second direction (D2 direction, figures).
Regarding claim 4, Jang discloses the semiconductor device as claimed in claim 1 as described above.
Jang further discloses, in at least figures 2-3 and 5-6 and related text, a width of an upper surface of each of the first contact plugs (120, BC, [48], [73]) in the second direction (D2 direction, figures) is greater than a width of an upper surface of each of the first contact plugs (120, BC, [48], [73]) in the first direction (D1 direction, figures).
Regarding claim 9, Jang discloses the semiconductor device as claimed in claim 1 as described above.
Jang further discloses, in at least figures 2-3 and 5-6 and related text, an isolation layer (105, [57]) in an isolation trench between the active patterns (ACT, [40]);
a first buffer layer (131, [74]) on the active patterns (ACT, [40]) and the isolation layer (105, [57]);
a second buffer layer (132, [74]) on the first buffer layer (131, [74]); and
a sacrificial mold layer pattern (154, [78]) passing through the first buffer layer (131, [74]) and the second buffer layer (131, [74]), the sacrificial mold layer pattern (154, [78]) contacting the isolation layer (105, [57]).
Regarding claim 10, Jang discloses the semiconductor device as claimed in claim 9 as described above.
Jang further discloses, in at least figures 2-3 and 5-6 and related text, the first contact plug (120, BC, [48], [73]) passes through the first buffer layer (131, [74]), the second buffer layer (132, [74]), and the sacrificial mold layer pattern (154, [78]), and
a width of the first contact plug (120, BC, [48], [73]) positioned higher than the second buffer layer (132, [74]) and a width of the first contact plug (120, BC, [48], [73]) positioned lower than the second buffer layer (132, [74]) are different from each other (figures).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 2022/0189966) in view of Moon (US 2022/0173107).
Regarding claim 5, Jang discloses the semiconductor device as claimed in claim 1 as described above.
Jang does not explicitly disclose a distance between adjacent ones of the first contact plugs in the first direction is greater than a distance between adjacent one of the first contact plugs in the second direction.
Moon teaches, in at least figures 1-2 and related text, the device comprising a distance between adjacent ones of the first contact plugs (BC, [24]) in the first direction (X2 direction, figures) is greater than a distance between adjacent one of the first contact plugs (BC, [24]) in the second direction (X2 direction, figures), for the purpose of providing a semiconductor memory device with improved structural stability ([84]).
Jang and Moon are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang with the specified features of Moon because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Jang to have the distance between adjacent ones of the first contact plugs in the first direction being greater than a distance between adjacent one of the first contact plugs in the second direction, as taught by Moon, for the purpose of providing a semiconductor memory device with improved structural stability ([84], Moon).
Regarding claim 12, Jang discloses the semiconductor device as claimed in claim 1 as described above.
Jang does not explicitly disclose two of the gate structures are spaced apart from each other and are arranged on a corresponding one of the active patterns.
Moon teaches, in at least figures 1-2 and related text, the device comprising two of the gate structures (107/WL, [17]) are spaced apart from each other and are arranged on a corresponding one of the active patterns (ACT, [16]), for the purpose of providing a semiconductor memory device with improved structural stability ([84]).
Jang and Moon are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang with the specified features of Moon because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Jang to have the two of the gate structures being spaced apart from each other and are arranged on a corresponding one of the active patterns, as taught by Moon, for the purpose of providing a semiconductor memory device with improved structural stability ([84], Moon).
Regarding claim 13, Jang in view of Moon discloses the semiconductor device as claimed in claim 1 as described above.
Jang further discloses, in at least figures 2-3 and 5-6 and related text, a dummy gate structure (dummy word line, [44], [59]) between the active pattern rows (rows of ACTs in D1 direction, figures).
Claim(s) 6-7 and 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 2022/0189966) in view of Sakoh (US 2008/0197392).
Regarding claim 6, Jang discloses the semiconductor device as claimed in claim 1 as described above.
Jang does not explicitly disclose the bit line structure includes first portions having a first width and second portions having a second width greater than the first width, the first portions and the second portions being alternately and repeatedly arranged in the second direction.
Sakoh teaches, in at least figures 1-2 and related text, the device comprising the bit line structure (10, [25]) includes first portions (narrow portion of 10, figures) having a first width and second portions (wide portion of 10, figures) having a second width greater than the first width, the first portions (narrow portion of 10, figures) and the second portions (wide portion of 10, figures) being alternately and repeatedly arranged in the second direction (horizontal direction, figures), for the purpose of providing bit lines arranged with higher density ([10]).
Jang and Sakoh are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang with the specified features of Sakoh because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Jang to have the bit line structure including first portions having a first width and second portions having a second width greater than the first width, the first portions and the second portions being alternately and repeatedly arranged in the second direction, as taught by Sakoh, for the purpose of providing bit lines arranged with higher density ([10], Sakoh).
Regarding claim 7, Jang in view of Sakoh discloses the semiconductor device as claimed in claim 6 as described above.
Jang does not explicitly disclose lower surfaces of the second portions of the bit line structure contact the central portions of the active patterns.
Sakoh teaches, in at least figures 1-2 and related text, the device comprising lower surfaces of the second portions of the bit line structure (10, [25]) contact the central portions of the active patterns (56, [28]), for the purpose of ensuring a necessary level of margin for alignment of the bit lines and capacitor contacts with higher density ([11]).
Jang and Sakoh are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang with the specified features of Sakoh because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Jang to have the lower surfaces of the second portions of the bit line structure contact the central portions of the active patterns, as taught by Sakoh, for the purpose of ensuring a necessary level of margin for alignment of the bit lines and capacitor contacts with higher density ([11], Sakoh).
Regarding claim 14, Jang discloses, in at least figures 2-3 and 5-6 and related text, a semiconductor device, comprising:
a substrate (100, [53]);
active patterns (ACT, [40]) on the substrate (100, [53]) and spaced apart from each other to define active pattern rows (rows of ACTs in D1 direction, figures) in a first direction (D1 direction, figures) parallel to an upper surface of the substrate (100, [53]), the active pattern rows (rows of ACTs in D1 direction, figures) being spaced apart from each other in a second direction (D2 direction, figures) perpendicular to the first direction (D1 direction, figures), and central portions of ones of the active patterns (ACT, [40]) included in different ones of the active pattern rows (rows of ACTs in D1 direction, figures) being aligned in the second direction (D2 direction, figures);
gate structures (110, [52]) in recesses of the active patterns (ACT, [40]), each of the gate structures extending in the first direction (D1 direction, figures);
first contact plugs (120, BC, [48], [73]) electrically connected to opposite edge portions of each of the active patterns (ACT, [40]), respectively, the first contact plugs (120, BC, [48], [73]) being spaced apart from each other in each of the first (D1 direction, figures) and second (D2 direction, figures) directions and aligned in each of the first (D1 direction, figures) and second (D2 direction, figures) directions;
first insulation spacers (150/170, [78], [81]) surrounding sidewalls of the first contact plugs (120, [48], [73]), the first insulation spacers (150/170, [78], [81]) filling spaces between adjacent ones of the first contact plugs (120, BC, [48], [73]) in the second direction (D2 direction, figures);
a bit line structure (140ST, [52]) filling an opening extending in the second direction (D2 direction, figures) between the first insulation spacers (150/170, [78], [81]), the bit line structure (140ST, [52]) contacting central portions of the active patterns (ACT, [40]);
a landing pad pattern (160, [52]) on an upper surface of each of the first contact plugs (120, BC, [48], [73]); and
a capacitor (190, [122]) electrically connected to each of the first contact plugs (120, BC, [48], [73]).
Jang does not explicitly disclose the bit line structure including first portions having a first width and second portions having a second width greater than the first width, the first portions and the second portions being alternately and repeatedly arranged in the second direction.
Sakoh teaches, in at least figures 1-3 and related text, the device comprising the bit line structure (10, [25]) including first portions (narrow portion of 10, figures) having a first width and second portions (wide portion of 10, figures) having a second width greater than the first width, the first portions (narrow portion of 10, figures) and the second portions (wide portion of 10, figures) being alternately and repeatedly arranged in the second direction (horizontal direction, figures), for the purpose of providing bit lines arranged with higher density ([10]).
Jang and Sakoh are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang with the specified features of Sakoh because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Jang to have the bit line structure including first portions having a first width and second portions having a second width greater than the first width, the first portions and the second portions being alternately and repeatedly arranged in the second direction, as taught by Sakoh, for the purpose of providing bit lines arranged with higher density ([10], Sakoh).
Regarding claim 15, Jang in view of Sakoh discloses the semiconductor device as claimed in claim 14 as described above.
Jang further discloses, in at least figures 2-3 and 5-6 and related text, ones of the second portions of the bit line structure (140ST, [52]) that face the first insulation spacer (150/170, [78], [81]) fill a space between adjacent ones of the first contact plugs (120, BC, [48], [73]) in the second direction (D2 direction, figures).
Regarding claim 16, Jang in view of Sakoh discloses the semiconductor device as claimed in claim 14 as described above.
Jang further discloses, in at least figures 2-3 and 5-6 and related text, the first insulation spacers (150/170, [78], [81]) include at least one insulation material.
Regarding claim 17, Jang in view of Sakoh discloses the semiconductor device as claimed in claim 14 as described above.
Jang further discloses, in at least figures 2-3 and 5-6 and related text, a spacing between ones of the gate structures (110, [52]) that are on neighboring ones of the active patterns (ACT, [40]) in a same one of the active pattern rows (rows of ACTs in D1 direction, figures) are different from a spacing between ones of the gate structures (110, [52]) that are on neighboring ones of the active patterns (ACT, [40]) in different neighboring ones of the active pattern rows (rows of ACTs in D1 direction, figures).
Regarding claim 18, Jang discloses, in at least figures 2-3 and 5-6 and related text, active patterns (ACT, [40]) on a substrate (100, [53]);
first contact plugs (120, BC, [48], [73]) electrically connected to at least portions of opposite edge portions of each of the active patterns (ACT, [40]), respectively, the first contact plugs (120, BC, [48], [73]) being spaced apart from each other in each of a first direction (D1 direction, figures) and a second direction (D2 direction, figures) and aligned in each of the first direction (D1 direction, figures) and the second direction (D2 direction, figures);
first insulation spacers (150/170, [78], [81]) surrounding sidewalls of the first contact plugs (120, BC, [48], [73]), the first insulation spacers (150/170, [78], [81]) filling spaces between the first contact plugs (120, BC, [48], [73]) in the second direction (D2 direction, figures);
a bit line structure (140ST, [52]) filling an opening extending in the second direction (D2 direction, figures) between the first insulation spacers (150/170, [78], [81]); and
a capacitor (190, [122]) electrically connected to each of the first contact plugs (120, BC, [48], [73]).
Jang does not explicitly disclose the bit line structure including first portions having a first width and second portions having a second width greater than the first width, the first portions and the second portions being alternately and repeatedly arranged in the second direction, and the second portions of the bit line structure contacting central portions of the active patterns.
Sakoh teaches, in at least figures 1-3 and related text, the device comprising the bit line structure (10, [25]) including first portions (narrow portion of 10, figures) having a first width and second portions (wide portion of 10, figures) having a second width greater than the first width, the first portions (narrow portion of 10, figures) and the second portions (wide portion of 10, figures) being alternately and repeatedly arranged in the second direction (horizontal direction, figures), and the second portions (wide portion of 10, figures) of the bit line structure (10, [25]) contacting central portions of the active patterns (56, [28]), for the purpose of ensuring a necessary level of margin for alignment of the bit lines and capacitor contacts with higher density ([11]).
Jang and Sakoh are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang with the specified features of Sakoh because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Jang to have the bit line structure including first portions having a first width and second portions having a second width greater than the first width, the first portions and the second portions being alternately and repeatedly arranged in the second direction, and the second portions of the bit line structure contacting central portions of the active patterns, as taught by Sakoh, for the purpose of ensuring a necessary level of margin for alignment of the bit lines and capacitor contacts with higher density ([11]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 2022/0189966) in view of Kim (US 2016/0056159).
Regarding claim 11, Jang discloses the semiconductor device as claimed in claim 1 as described above.
Jang does not explicitly disclose a silicon pattern and a metal silicide pattern between each of the first contact plugs and a corresponding one of the active patterns.
Kim teaches, in at least figure 2 and related text, the device comprising a silicon pattern and a metal silicide pattern between each of the first contact plugs (BC, [81]) and a corresponding one of the active patterns (110A, [81]) ([81], figure), for the purpose of reducing contact resistance of contact plug.
Jang and Kim are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Jang to have the silicon pattern and a metal silicide pattern between each of the first contact plugs and a corresponding one of the active patterns, as taught by Kim, for the purpose of reducing contact resistance of contact plug.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 2022/0189966) in view of Sakoh (US 2008/0197392), and further in view of Lee (US 2016/0035731).
Regarding claim 19, Jang in view of Sakoh discloses the semiconductor device as claimed in claim 18 as described above.
Jang further discloses, in at least figures 2-3 and 5-6 and related text, the bit line structure (140ST, [52]) includes a bit line pattern (140, [65]) and a capping layer pattern (144, [65]) stacked on the bit line pattern (140, [65]).
Jang in view of Sakoh does not explicitly disclose an uppermost surface of the bit line structure is coplanar with uppermost surfaces of the first contact plugs.
Lee teaches, in at least figure 1 and related text, the device comprising an uppermost surface of the bit line structure (146, [56]) is coplanar with uppermost surfaces of the first contact plugs (151, [101]), for the purpose of providing semiconductor device including a wiring structure having a very small size ([147]).
Jang, Sakoh, and Lee are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang in view of Sakoh with the specified features of Lee because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Jang in view of Sakoh to have the uppermost surface of the bit line structure being coplanar with uppermost surfaces of the first contact plugs, as taught by Lee, for the purpose of providing semiconductor device including a wiring structure having a very small size ([147], Lee).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 6, and 8 that recite "each of the second portions of the bit line structure includes a portion having a gradually increasing width, a portion having a widest width, and a portion having a gradually decreasing width" in combination with other elements of the base claims 1, 6, and 8.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 18 and 20 that recite "each of the second portions of the bit line structure includes a portion having a gradually increasing width, a portion having a widest width, and a portion having a gradually decreasing width" in combination with other elements of the base claims 18 and 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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