DETAILED ACTION
This Action is responsive to the Amendment filed on 06/12/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8-14 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 8 recites the limitation "the at least one dummy die" (emphasis added) in line 3. There is insufficient antecedent basis for this limitation in the claim.
Under the principles of compact prosecution, the Examiner will interpret the claimed limitation “the at least one dummy die” as at least one dummy die.
Claims 9-14 are rejected under 35 U.S.C. 112(b) as being indefinite due to the claims’ dependency to Claim 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 8, 10, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2023/0378134), in view of Yu (US 2024/0413136), in view of Lin (US 2007/0284726).
Regarding claim 1, Lee (see, e.g., FIG. 9) discloses a semiconductor stack structure comprising:
a plurality of semiconductor dies 53, 55, 57, 59 vertically stacked on each other (Para 0052); and
at least one dummy die 56, 565_1 to 565_4, 561_1 to 561_4 positioned between the plurality of semiconductor dies 53, 55, 57, 59, wherein the at least one dummy die 56, 565_1 to 565_4, 561_1 to 561_4 includes:
a dummy die base 56 (Para 0056);
a first interconnection structure 561_1 to 561_4 positioned on a first side e.g., bottom side of 56 of the dummy die base 56 and including a plurality of first bonding pads 561_1 to 561_4, wherein the plurality of first bonding pads 561_1 to 561_4 are positioned at substantially regular intervals (Para 0056); and
a second interconnection structure 565_1 to 565_4 positioned on a second side e.g., top side of 56 of the dummy die base 56 and including a plurality of second bonding 565_1 to 565_4, wherein the plurality of second bonding pads 565_1 to 565_4 are positioned at substantially regular intervals (Para 0056),
Although Lee shows substantial features of the claimed invention, Lee fails to expressly teach a first silicon insulating layer at least partially surrounding the plurality of first bonding pads; and a second silicon insulating layer at least partially surrounding the plurality of second bonding pads.
Yu (see, e.g., FIG. 2) teaches a first silicon insulating layer 332 at least partially surrounding the plurality of first bonding pads 331 (Para 0007, Para 0048, Para 0053, Para 0054); and a second silicon insulating layer 322 at least partially surrounding the plurality of second bonding pads 321 (Para 0007, Para 0048, Para 0052, Para 0054). Lin, on the other hand, teaches that passivation layer 108 is used to protect the underlying devices from moisture and other contaminants (Para 0026).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first silicon insulating layer at least partially surrounding the plurality of first bonding pads; and the second silicon insulating layer at least partially surrounding the plurality of second bonding pads as described by Yu/Lin to the device of Lee for the purpose of protecting the underlying devices from moisture and other contaminants (Para 0026).
Regarding Claim 3, Lee (see, e.g., FIG. 9) teaches the semiconductor stack structure of claim 1, the at least one dummy die 56 further includes plurality of through silicon vias 563_1 to 563_4, and each of the plurality of through silicon vias 563_1 to 563_4 electrically connects each of the plurality of second bonding pads 565_1 to 565_4 to a corresponding first bonding pad 561_1 to 561_4 of the plurality of first bonding pads 561_1 to 561_4 (Para 0056).
Regarding claim 8, Lee (see, e.g., FIG. 9) discloses a semiconductor stack structure comprising:
a plurality of semiconductor dies 53, 55, 57 vertically stacked (Para 0052); and
the at least one dummy die 56, 565_1 to 565_4, 561_1 to 561_4 positioned between the plurality of semiconductor dies 53, 55, 57, wherein the at least one dummy die 56, 565_1 to 565_4, 561_1 to 561_4 includes:
a dummy die base 56 (Para 0052, Para 0056);
a first interconnection structure 565_1 to 565_4 positioned on a first side e.g., top side of 56 of the dummy die base 56, wherein the first interconnection structure 565_1 to 565_4 includes a plurality of first bonding pads 565_1 to 565_4 positioned at substantially regular intervals (Para 0056); and
a second interconnection structure 561_1 to 561_4 positioned on a second side e.g., bottom side of 56 of the dummy die base 56, wherein the second connection structure 561_1 to 561_4 includes a plurality of second bonding pads 561_1 to 561_4 positioned at substantially regular intervals (Para 0056),
wherein each semiconductor die 53, 55, 57 of the plurality of semiconductor dies 53, 55, 57 include:
a semiconductor die base 53, 55, 57 (Para 0052);
a third interconnection structure 531_1 to 531_4; 555_1 to 555_4; 571_1 to 571_4 positioned on a first side e.g., top side of 53, 55, 57 of the semiconductor die base 53, 55, 57 and positioned in a front side direction e.g., top side direction of 53, 55, 57 of each semiconductor die 53, 55, 57 of the plurality of semiconductor dies 53, 55, 57, wherein the third interconnection structure 531_1 to 531_4; 555_1 to 555_4; 571_1 to 571_4 includes a plurality of third bonding pads 531_1 to 531_4; 555_1 to 555_4; 571_1 to 571_4 (Para 0054, Para 0055, Para 0057); and
a fourth interconnection structure 535_1 to 535_4; 551_1 to 551_4; 575_1 to 575_4 positioned on a second side e.g., bottom side of 53, 55, 57 of the semiconductor die base 53, 55, 57 and positioned in a back side direction e.g., bottom side direction of 53, 55, 57 of each semiconductor die 53, 55, 57 of the plurality of semiconductor dies 53, 55, 57, wherein the fourth interconnection structure 535_1 to 535_4; 551_1 to 551_4; 575_1 to 575_4 includes a plurality of fourth bonding pads 535_1 to 535_4; 551_1 to 551_4; 575_1 to 575_4 (Para 0053-Para 0055, Para 0057).
Although Lee shows substantial features of the claimed invention, Lee fails to expressly teach a first silicon insulating layer at least partially surrounding the plurality of first bonding pads; and a second silicon insulating layer at least partially surrounding the plurality of second bonding pads; a third silicon insulating layer at least partially surrounding the plurality of third bonding pads; and a fourth silicon insulating layer at least partially surrounding the plurality of fourth bonding pads.
Yu (see, e.g., FIG. 9) teaches a first silicon insulating layer 322 at least partially surrounding the plurality of first bonding pads 321 (Para 0007, Para 0048, Para 0052, Para 0054; see also FIG. 2); and a second silicon insulating layer 332 at least partially surrounding the plurality of second bonding pads 331 (Para 0007, Para 0048, Para 0053, Para 0054; see also FIG. 2); a third silicon insulating layer 422 at least partially surrounding the plurality of third bonding pads 421 (Para 0087); and a fourth silicon insulating layer 432 at least partially surrounding the plurality of fourth bonding pads 431 (Para 0087). Lin, on the other hand, teaches that passivation layer 108 is used to protect the underlying devices from moisture and other contaminants (Para 0026).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first silicon insulating layer at least partially surrounding the plurality of first bonding pads; and the second silicon insulating layer at least partially surrounding the plurality of second bonding pads; the third silicon insulating layer at least partially surrounding the plurality of third bonding pads; and the fourth silicon insulating layer at least partially surrounding the plurality of fourth bonding pads as described by Yu/Lin to the device of Lee for the purpose of protecting the underlying devices from moisture and other contaminants (Para 0026).
Regarding claim 10, Lee (see, e.g., FIG. 9) teaches the semiconductor stack structure of claim 8, wherein each of the plurality of first bonding pads 565_1 to 565_4 of the at least one dummy die 56 is directly bonded to a corresponding second bonding pad among a plurality of second bonding pads of a neighboring dummy die or a corresponding fourth bonding pad 575_1 to 575_4 among a plurality of fourth bonding pads 575_1 to 575_4 of a neighboring semiconductor die 57.
Regarding claim 12, the combination of Lee (see, e.g., FIG. 9) / Yu (see, e.g., FIG. 9) teaches the semiconductor stack structure of claim 8, wherein the first silicon insulating layer 322 (as taught by Yu) of the at least one dummy die 56 (as taught by Lee) is directly bonded to a second silicon insulating layer of a neighboring dummy die, or a fourth silicon insulating layer 432 (as taught by Yu) of a neighboring semiconductor die 57 (as taught by Lee).
Regarding claim 14, Lee (see, e.g., FIG. 9) teaches the semiconductor stack structure of claim 8, wherein each semiconductor die 53, 55, 57 of the plurality of semiconductor dies 53, 55, 57 further includes a plurality of through silicon vias 573_1 to 573_4; 553_1 to 553_4; 533_1 to 533_4, and each of the plurality of through silicon vias 573_1 to 573_4; 553_1 to 553_4; 533_1 to 533_4 electrically connects each fourth bonding pad 535_1 to 535_4; 551_1 to 551_4; 575_1 to 575_4 of the plurality of fourth bonding pads 535_1 to 535_4; 551_1 to 551_4; 575_1 to 575_4 to a corresponding third bonding pad 531_1 to 531_4; 555_1 to 555_4; 571_1 to 571_4 of the plurality of third bonding pads 531_1 to 531_4; 555_1 to 555_4; 571_1 to 571_4 (Para 0054, Para 0055, Para 0057).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2023/0378134), in view of Yu (US 2024/0413136), in view of Lin (US 2007/0284726), and further in view of Yang (US 2005/0046039).
Regarding claim 5, although Lee/Yu/Lin show substantial features of the claimed invention, Lee/Yu/Lin fail to expressly teach the semiconductor stack structure of claim 1, wherein a difference between a maximum thickness and a minimum thickness of the at least one dummy die in a vertical direction is about 50 Å or less. Yang (see, e.g., FIG. 3), on the other hand, teaches that dummy die 130 has a thickness of 200 µm (Para 0013). Therefore, the difference between the maximum thickness and the minimum thickness is zero. However, differences in thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thickness difference is critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph) of the difference between a maximum thickness and a minimum thickness of the at least one dummy die in a vertical direction is about 50 Å or less, it would have been obvious to one of ordinary skill in the art to modify the difference between a maximum thickness and a minimum thickness of the dummy die in the vertical direction to be about 50 Å or less in the device of Lee through routine experimentation.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed difference between the maximum thickness and the minimum thickness of the at least one dummy die in a vertical direction to be about 50 Å or less or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2023/0378134), in view of Yu (US 2024/0413136), in view of Lin (US 2007/0284726), and further in view of Wan (US 2021/0118756).
Regarding claim 6, although Lee/Yu/Lin show substantial features of the claimed invention, Lee/Yu/Lin fail to expressly teach the semiconductor stack structure of claim 1, wherein a number of stacked layers of the plurality of semiconductor dies and the at least one dummy die is 12. Lee, on the other hand, does teach that the number of stacked layers of the plurality of semiconductor dies and the at least one dummy die is 5. Wan (see, e.g., FIG. 1) teaches that a stack of dies 111 refers to two or more dies (Para 0016, Para 0023). However, differences in the number of dies will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such number of dies difference is critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph) of the number of dies, it would have been obvious to one of ordinary skill in the art to modify the number of dies in the device of Lee through routine experimentation.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed number of dies or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2023/0378134), in view of Yu (US 2024/0413136), in view of Lin (US 2007/0284726), and further in view of Kang (US 2022/0344252).
Regarding claim 9, although Lee/Yu/Lin show substantial features of the claimed invention, Lee/Yu/Lin fail to expressly teach the semiconductor stack structure of claim 8, wherein surface roughnesses of each of the first interconnection structure and the second interconnection structure are about 10 Å or less. Kang (see, e.g., FIG. 1A), on the other hand, teaches that the surface roughness Ra of the surfaces Sr of the interconnection structures 114 are about 0.2 or less (Para 0028). However, differences in the surface roughness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such surface roughness differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph) of the surface roughness of each of the first interconnection structure and the second interconnection structure are about 10 Å or less, it would have been obvious to one of ordinary skill in the art to modify the surface roughness of the first interconnection structure and the second interconnection structure to be about 10 Å or less in the device of Lee through routine experimentation.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed surface roughness of the first interconnection structure and the second interconnection structure being about 10 Å or less or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 15-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0151388), in view of Lee (US 2023/0378134), in view of Yu (US 2024/0413136).
Regarding claim 15, Choi (see, e.g., FIG. 1B) discloses a semiconductor package comprising:
an interposer 20 (Para 0026);
at least one semiconductor stack structure 41a, 41c disposed on the interposer 20 (Para 0028);
a semiconductor structure 31 disposed on the interposer 20 (Para 0027); and
a molding material 80 positioned on the interposer 20 and covering the at least one semiconductor stack structure 41a, 41c and the semiconductor structure 31 (Para 0037),
wherein the at least one semiconductor stacked structure 41a, 41c includes:
a plurality of first semiconductor dies e.g., plurality of memory chips vertically stacked on each other (Para 0009, Para 0028),
Although Choi shows substantial features of the claimed invention, Choi fails to expressly teach at least one dummy die positioned between the plurality of first semiconductor dies, wherein the at least one dummy die includes: a dummy die base; a first interconnection structure positioned on a first side of the dummy die base and including a plurality of first bonding pads, wherein the plurality of first bonding pads are positioned at substantially regular intervals, and a first silicon insulating layer at least partially surrounding the plurality of first bonding pads; and a second interconnection structure positioned on a second side of the dummy die base and including a plurality of second bonding, wherein the plurality of second bonding pads are positioned at substantially regular intervals, and a second silicon insulating layer at least partially surrounding the plurality of second bonding pads.
Lee (see, e.g., FIG. 9) teaches at least one dummy die 56, 565_1 to 565_4, 561_1 to 561_4 positioned between the plurality of first semiconductor dies 53, 55, 57, wherein the at least one dummy die 56, 565_1 to 565_4, 561_1 to 561_4 includes: a dummy die base 56 (Para 0056); a first interconnection structure 561_1 to 561_4 positioned on a first side e.g., bottom side of 56 of the dummy die base 56 and including a plurality of first bonding pads 561_1 to 561_4, wherein the plurality of first bonding pads 561_1 to 561_4 are positioned at substantially regular intervals (Para 0056); and a second interconnection structure 565_1 to 565_4 positioned on a second side e.g., top side of 56 of the dummy die base 56 and including a plurality of second bonding 565_1 to 565_4, wherein the plurality of second bonding pads 565_1 to 565_4 are positioned at substantially regular intervals for the purpose of providing a plurality of chips that may transmit data to one another in addition to control signals including commands and addresses through respective through vias (Para 0002, Para 0056).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory stack of Choi to be a plurality of semiconductor dies including at least one dummy die positioned between the plurality of first semiconductor dies as described by Lee for the purpose of providing a plurality of chips that may transmit data to one another in addition to control signals including commands and addresses through respective through vias (Para 0002).
Yu (see, e.g., FIG. 2) teaches a first silicon insulating layer 332 at least partially surrounding the plurality of first bonding pads 331 (Para 0007, Para 0048, Para 0053, Para 0054); and a second silicon insulating layer 322 at least partially surrounding the plurality of second bonding pads 321 (Para 0007, Para 0048, Para 0052, Para 0054). Lin, on the other hand, teaches that passivation layer 108 is used to protect the underlying devices from moisture and other contaminants (Para 0026).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first silicon insulating layer at least partially surrounding the plurality of first bonding pads; and the second silicon insulating layer at least partially surrounding the plurality of second bonding pads as described by Yu/Lin to the device of Lee for the purpose of protecting the underlying devices from moisture and other contaminants (Para 0026).
Regarding claim 16, the combination of Choi (see, e.g., FIG. 1B) / Lee (see, e.g., FIG. 9) teaches semiconductor package of claim 15, wherein the semiconductor structure 31 (as taught by Choi) is positioned side by side with the at least one semiconductor stack structure 41a, 41c (as taught by Choi, and modified by Lee).
Regarding claim 20, Choi (see, e.g., FIG. 1B) teaches the semiconductor package of claim 15, wherein the molding material 80 includes an epoxy molding compound (EMC) (Para 0042).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0151388), in view of Lee (US 2023/0378134), in view of Yu (US 2024/0413136), and further in view of Tsao (US 2024/0243098).
Regarding claim 18, although Choi/Lee/Yu show substantial features of the claimed invention, Choi/Lee/Yu fail to expressly teach semiconductor package of claim 15, wherein the at least one semiconductor stack structure includes a high bandwidth memory (HBM).
Tsao (see, e.g., FIG. 2) teaches the semiconductor stack structure 102 includes a high bandwidth memory (HBM) for the purpose of utilizing memory chips with low power consumption and ultra-wide communication lanes (Para 0035).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the at least one semiconductor stack structure of memory dies of Choi for the semiconductor stack structure that includes a high bandwidth memory (HBM) as described by Tsao for the purpose of utilizing memory chips with low power consumption and ultra-wide communication lanes (Para 0035).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0151388), in view of Lee (US 2023/0378134), in view of Yu (US 2024/0413136), and further in view of Noh (US 2023/0029151).
Regarding claim 19, although Choi/Lee/Yu show substantial features of the claimed invention, Choi/Lee/Yu fail to expressly teach semiconductor package of claim 15, wherein the semiconductor structure includes a central processing unit (CPU) or a graphic processing unit (GPU). Choi does, on the other hand, teach that the semiconductor structure 31 is an application specific integrated circuit (ASIC) (Para 0027).
Noh (see, e.g., FIG. 12), on the other hand, teaches that the semiconductor structure 310 may be central processing unit (CPU), graphic processing unit (GPU), or an application specific IC (ASIC) (Para 0152).
Therefore, it would have been obvious at the time of filing the invention to one or ordinary skill in the art to use either an application specific integrated circuit (ASIC), a central processing unit (CPU), or a graphic processing unit (GPU) in the device of Choi because these were recognized in the semiconductor art for their use logic dies, as taught by Noh, and selecting between known equivalents would be within the level of ordinary skill in the art.
Response to Arguments
Applicant’s arguments with respect to claims 1, 8, and 15 have been considered but are moot because of the new ground of rejection.
Allowable Subject Matter
Claims 2, 4, 7, 11, 13, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Prosecution Insights