DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “Heterojunction Bipolar Transistor Device With Metallic Sub-Collector and Base Electrode Fingers”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8, 10-17, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2022/0216303A1; hereinafter, “Yu”) in view of Li et al. (US 8,830,092 B1; hereinafter, “Li”).
Regarding claim 1:
Yu discloses a heterojunction bipolar transistor (HBT) device, comprising:
a substrate 106 (Fig. 10B and [0029]);
a
a collector layer 108 (Fig. 10B and [0032]) formed over the
a base layer 110 (Fig. 10B and [0033]) formed over the collector layer 108;
an emitter layer 112 formed over the base layer 110;
a base electrode 119 (Figs. 10B, 12A, 12B and [0075]) formed over the base layer 110 and comprising a plurality of base fingers (Figs. 12A-12B and [0082]); and
a plurality of emitter strips 114 (Figs. 10B, 12A, 12B and [0035]) formed over the emitter layer 112 and arranged alternately with the plurality of base fingers (Figs. 12A-12B);
Yu does not disclose the sub-collector 104B is metallic.
Li teaches incorporating a metallic sub-collector 40 (Fig. 5 and Col. 4, line 5) into a HBT can significantly improve device performance by reducing collector electrical resistance and providing an efficient path for heat dissipation (e.g., see Col. 5, lines 26-40).
It would have been obvious to one of ordinary skill in the art to modify Yu by incorporating a metallic sub-collector, as taught by Li, because the modification could significantly improve device performance.
Regarding claims 2-8 and 10-16:
re claim 2, Yu discloses the heterojunction bipolar transistor device as claimed in claim 1, further comprising: a single base mesa 118 (Fig. 10B and [0075]) comprising the collector layer 108 and the base layer 110, wherein the plurality of emitter strips 112/114 (Figs. 10B, 12A, 12B) are disposed over the single base mesa;
re claim 3, Yu discloses the heterojunction bipolar transistor device as claimed in claim 1, further comprising: a metal layer 116 (Fig. 10B and [0036]) formed over and electrically connected to the plurality of emitter strips 112/114;
re claim 4, Li discloses a conductive bump 50 (Fig. 5 and Col. 4, line 36) formed over and electrically connected to an emitter 66; accordingly, Yu (in view of Li) renders obvious a conductive bump formed over and electrically connected to the plurality of emitter strips;
re claim 5, Li discloses a second conductive bump 76 (Fig. 5 and Col. 4, line 45) formed over and electrically connected to the metallic sub-collector layer 40 in an area outside the collector layer;
re claim 6, Li discloses a collector contact 78 (Fig. 5 and Col. 4, lines 46) formed between the metallic sub-collector layer 40 and the second conductive bump 76;
re claim 7, Li discloses the emitter 66 (Fig. 5) arranged in a first direction (e.g., x-direction on a plane in a top view), and the first conductive bump 50 and the second conductive bump 79 are arranged in a second direction (e.g., y-direction on the plane in the top view) different from the first direction in a top view (i.e., the emitter and conductive bumps have two dimensions in the top view; accordingly, the emitter is considered to be arranged in the x-direction and the conductive bumps are considered to be arranged in the y-direction); accordingly, Yu (in view of Li) renders obvious the plurality of emitter strips arranged in a first direction, and the first and second conductive bumps arranged in a second, different direction;
re claim 8, Li discloses the emitter 65 is arranged in a direction (e.g., x-direction), and the first conductive bump and the second conductive bump are arranged in the direction (e.g., x-direction) in a top view (i.e., the emitter and conductive bumps have two dimensions in the top view; accordingly, the emitter and the conductive bumps are considered to be arranged in the x-direction); accordingly, Yu (in view of Li) renders obvious the plurality of emitter strips and the conductive bumps being arranged in a same direction;
re claim 10, Yu discloses a dielectric layer 120 (Figs. 1D, 10B and [0042]) formed over the substrate and covering sidewalls of the collector layer 108, the base layer 110, the emitter layer 112, and the
re claim 11, Yu discloses wherein the dielectric layer 20 (Figs. 1D and 10B) further covers a sidewall and a top surface of the base electrode 119;
re claim 12, Yu discloses the plurality of emitter strips 114/112 (Figs. 10B and 12A-12B) and the plurality of base fingers 119 are arranged along a width direction of the base layer (i.e., in a two dimensional view, a width and length are chosen as desired; accordingly, the arrangement shown in Figs. 12A-12 are considered to be along a width direction of the base layer);
re claim 13, Yu (in view of Li) discloses each of the emitter strips 114/112 (in Yu) overlaps the metallic sub-collector layer (semiconductor “104B” in Yu, and metallic “40” in Li);
re claim 14, Yu (in view of Li) discloses shortest distances from each of the emitter strips 112/114 to the metallic sub-collector layer are substantially same (i.e., the emitter strips are separated from the sub-collector layer by the same two layers, 108/110 in Yu, Fig. 10B);
re claim 15, Yu (in view of Li) discloses a backside via 125 (Fig. 9A and [0044]) formed in the substrate 106; and a backside metal layer 124/104A (Fig. 9B and [0046]) extending from a top surface of the substrate to a bottom surface of the substrate along a sidewall of the backside via and connecting to a metal layer 104A [0028] formed of the same material as the metallic sub-collector layer 104B [0030] (i.e., when Yu’s semiconductor sub-collector is replaced by Li’s metallic sub-collector, this claim is deemed obvious); and
re claim 16, Li discloses a metal layer 76/50/70 (Fig. 5) electrically connected to the emitter strip 66 and vertically overlapping a backside via 72 (accordingly, Yu modified as taught by Li renders the current claim obvious).
Therefore, Yu (in view of Li) renders claims 2-8 and 10-16 obvious.
Regarding claim 17:
Yu discloses a heterojunction bipolar transistor (HBT) device, comprising:
a substrate 102 (Fig. 10B and [0027]);
a collector mesa 108/104B formed on the substrate and comprising a
a base mesa 110 [0033] formed on the collector mesa;
a plurality of emitter mesas 112 (Figs. 10B, 12A-12B and [0035]) formed on the base mesa; and
a base electrode 119 (Fig. 10B, 12A-12B and [0041]) formed on the base mesa and comprising a plurality of base fingers (Figs. 12A-12B arranged alternately with the plurality of emitter mesas 112.
Yu does not disclose the sub-collector 104B is metallic.
Li teaches incorporating a metallic sub-collector 40 (Fig. 5 and Col. 4, line 5) into a HBT can significantly improve device performance by reducing collector electrical resistance and providing an efficient path for heat dissipation (e.g., see Col. 5, lines 26-40).
It would have been obvious to one of ordinary skill in the art to modify Yu by incorporating a metallic sub-collector, as taught by Li, because the modification could significantly improve device performance.
Regarding claims 19 and 20:
re claim 19, Yu discloses a collector contact 124 (Fig. 10B and [0045]) formed over the
re claim 20, Yu discloses the plurality of emitter mesas 12 overlap the base mesa 110 (Fig. 10B and 12A-12B) and the
Therefore, Yu (in view of Li) renders claims 19-20 obvious.
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (in view of Li) as applied to claim 1 above, and further in view of Kurokawa et al. (US 2013/0026541 A1; hereinafter, “Kurokawa”).
Regarding claims 9 and 18:
Yu (in view of Li) does not disclose a passive component.
Kurokawa teaches (in Figs. 5 and 10) a passive component (e.g., C7) formed over a substrate 3s [0110] in an area outside a collector layer 25ci, wherein the passive component C7 comprises a bottom metal layer 12a [0112] formed of the same material (e.g., gold, Au, [0112) as Li’s metallic sub-collector layer 40 (see Li, Fig. 5 and Col. 4, lines 12-13). Kurokawa discloses the integration of the passive device(s) prevents electrostatic breakdown [0002, 0006].
It would have been obvious to one of ordinary skill in the art to modify Yu (in view of Li) by incorporating a passive component, as taught by Kurokawa, because the modification could provide electrostatic-breakdown prevention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892