Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170324025 A1) in view of Iwayama (US 20120056253 A1) further in view of Lung (US 20190355903 A1).
RE: Independent Claim 1, Lee discloses a semiconductor device, comprising:
a lower dielectric layer on a substrate (Lee, Fig. 3 and ¶ [0024], dielectric layer 114 on substrate 100);
a plurality of data storage patterns (Lee, Fig. 3 and ¶ [0027] data storage structures 150 each including bottom electrode 120, data storage section 130 and top electrode 140) on the lower dielectric layer (Lee, Fig. 3 and ¶ [0027], 150 may be provided on the dielectric layer 114) and spaced apart from each other in a first direction and a second direction that are parallel to a top surface of the substrate, wherein the first and second directions intersect each other (Lee, in Fig. 1 and ¶ [0027], teaches that the structures 150 are two-dimensionally arranged along the first direction D1 and the second direction D2 that crosses the direction D1);
a cell dielectric layer on the lower dielectric layer and on the data storage patterns (Lee, ¶[0048], mold layer 118 may include an oxide, a nitride, and/or an oxynitride, i.e. dielectric layer, and 118 is on the lower dielectric layer 114 and covers data storage structure 150); and
a plurality of upper conductive lines … spaced apart from each other in the second direction, wherein the upper conductive lines extend in the first direction (Lee teaches, in ¶ [0030], second conductive lines 182, a plurality of which extends substantially in first direction D1, are spaced apart in second direction D2).
Lee is silent regarding
a plurality of upper conductive contacts respectively on the data storage patterns and spaced apart from each other in the first direction and the second direction; that the upper conductive lines are on the upper conductive contacts; wherein each of the upper conductive lines is electrically connected to respective ones of the upper conductive contacts; and wherein the respective ones of the upper conductive contacts are spaced apart from each other in the first direction.
However, Iwayama teaches
a plurality of upper conductive contacts respectively on the data storage patterns and spaced apart from each other in the first direction and the second direction; that the upper conductive lines are on the upper conductive contacts; wherein each of the upper conductive lines is electrically connected to respective ones of the upper conductive contacts; and wherein the respective ones of the upper conductive contacts are spaced apart from each other in the first direction (Iwayama teaches, in Figs. 1-2, MTJ element is connected between the lower electrode LE and the upper electrode UE, and that the upper electrode UE is connected to the bit line BL2 via contact plugs PLG4 and PLG5. Iwayama also teaches that a silicon nitride film 70 and a silicon oxide film 80 are provided on the upper electrode UE, and that interlayer dielectric film ILD2 covers those layers. Thus, Iwayama teaches a distinct plug-type contact structure above the MTJ stack and an upper conductive line (BL2) electrically connected to that contact structure (UE). In view of the two-dimensional arrangement of data storage structures 150 in Lee, applying the plug-contact architecture of Lee yields a plurality of upper conductive contacts respectively on corresponding data storage patterns and spaced apart in the first and second directions.
Lee is further silent regarding
a plurality of voids in the cell dielectric layer and between ones of the data storage patterns.
However, Lung teaches
a plurality of voids in the cell dielectric layer and between ones of the data storage patterns (Lung, Fig. 11A, teaches a memory cell level including an array of memory pillars disposed in cross-points between first and second access lines, with memory pillars lined by dielectric liners 1102, and airgaps or voids 1104 formed between the memory pillars. Lung also expressly teaches that a memory cell level includes voids surrounding the memory pillars in the array. Accordingly, Lung teaches voids in dielectric material between adjacent storage structures in a dense memory array).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor memory device of Lee to include the plug-type upper-contact / upper-line structure taught by Iwayama, in order to electrically connect the upper portion of each storage structure to an overlying bit line through a distinct contact-plug interconnect structure. It would further have been obvious to modify the dielectric surrounding the storage structures of Lee in view of Lung, because Lung teaches dielectric liners and air gaps or voids between the neighboring memory pillars in a very high-density memory architecture, in order to provide dielectric/void isolation between adjacent storage structures while supporting dense memory integration.
RE: Independent Claim 12, Lee discloses a semiconductor device, comprising:
a lower dielectric layer on a substrate (Lee, Fig. 3 and ¶ [0024], dielectric layer 114 on substrate 100);
a plurality of data storage patterns (Lee, Fig. 3 and ¶ [0027] data storage structures 150 each including bottom electrode 120, data storage section 130 and top electrode 140) on the lower dielectric layer (Lee, Fig. 3 and ¶ [0027], 150 may be provided on the dielectric layer 114) and spaced apart from each other in a first direction parallel to a top surface of the substrate (Lee, in Fig. 1 and ¶ [0027], teaches that the structures 150 are two-dimensionally arranged along the first direction D1);
a cell dielectric layer on the lower dielectric layer and on the data storage patterns (Lee, ¶ [0048], mold layer 118 may include an oxide, a nitride, and/or an oxynitride, i.e. dielectric layer, and 118 is on the lower dielectric layer 114 and covers data storage structure 150);
an upper conductive line…extends in the first direction (Lee teaches, in ¶ [0030], second conductive lines 182, a plurality of which extends substantially in first direction D1).
Lee is silent regarding
a plurality of upper conductive contacts respectively on the data storage patterns and spaced apart from each other in the first direction; that the upper conductive line that is on the upper conductive contacts; wherein the upper conductive contacts extend into an upper portion of the cell dielectric layer and are respectively electrically connected to the data storage patterns, and wherein the upper conductive line is electrically connected to the upper conductive contacts.
However, Iwayama teaches a plurality of upper conductive contacts respectively on the data storage patterns and spaced apart from each other in the first direction; that the upper conductive line that is on the upper conductive contacts; wherein the upper conductive contacts extend into an upper portion of the cell dielectric layer and are respectively electrically connected to the data storage patterns, and wherein the upper conductive line is electrically connected to the upper conductive contacts (Iwayama teaches, in Figs. 1-2, MTJ element is connected between the lower electrode LE and the upper electrode UE, and that the upper electrode UE is connected to the bit line BL2 via contact plugs PLG4 and PLG5. Iwayama also teaches that a silicon nitride film 70 and a silicon oxide film 80 are provided on the upper electrode UE, and that interlayer dielectric film ILD2 covers those layers. Thus, Iwayama teaches a distinct plug-type contact structure above the MTJ stack and an upper conductive line (BL2) electrically connected to that contact structure (UE). In view of the two-dimensional arrangement of data storage structures 150 in Lee, applying the plug-contact architecture of Lee yields a plurality of upper conductive contacts respectively on corresponding data storage patterns and spaced apart in the first direction).
Lee is further silent regarding
a plurality of voids in the cell dielectric layer and between ones of the data storage patterns.
However, Lung teaches
a plurality of voids in the cell dielectric layer and between ones of the data storage patterns (Lung, Fig. 11A, teaches a memory cell level including an array of memory pillars disposed in cross-points between first and second access lines, with memory pillars lined by dielectric liners 1102, and airgaps or voids 1104 formed between the memory pillars. Lung also expressly teaches that a memory cell level includes voids surrounding the memory pillars in the array. Accordingly, Lung teaches voids in dielectric material between adjacent storage structures in a dense memory array).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor memory device of Lee to include the plug-type upper-contact / upper-line structure taught by Iwayama, in order to electrically connect the upper portion of each storage structure to an overlying bit line through a distinct contact-plug interconnect structure. It would further have been obvious to modify the dielectric surrounding the storage structures of Lee in view of Lung, because Lung teaches dielectric liners and air gaps or voids between the neighboring memory pillars in a very high-density memory architecture, in order to provide dielectric/void isolation between adjacent storage structures while supporting dense memory integration.
RE: Independent Claim 20, Lee discloses a semiconductor device, comprising:
a lower dielectric layer on a substrate (Lee, Fig. 3 and ¶ [0024], dielectric layer 114 on substrate 100);
a plurality of data storage patterns (Lee, Fig. 3 and ¶ [0027] data storage structures 150 each including bottom electrode 120, data storage section 130 and top electrode 140) on the lower dielectric layer (Lee, Fig. 3 and ¶ [0027], 150 may be provided on the dielectric layer 114) and spaced apart from each other in a first direction parallel to a top surface of the substrate (Lee, in Fig. 1 and ¶ [0027], teaches that the structures 150 are two-dimensionally arranged along the first direction D1);
a cell dielectric layer on the lower dielectric layer and on the data storage patterns (Lee, ¶ [0048], mold layer 118 may include an oxide, a nitride, and/or an oxynitride, i.e. dielectric layer, and 118 is on the lower dielectric layer 114 and covers data storage structure 150);
an upper conductive line…extends in the first direction (Lee teaches, in ¶ [0030], second conductive lines 182, a plurality of which extends substantially in first direction D1).
Lee is silent regarding
a plurality of upper conductive contacts respectively on the data storage patterns and spaced apart from each other in the first direction; that the upper conductive line that is on the upper conductive contacts; wherein the upper conductive line is electrically connected to the upper conductive contacts.
However, Iwayama teaches
a plurality of upper conductive contacts respectively on the data storage patterns and spaced apart from each other in the first direction; that the upper conductive line that is on the upper conductive contacts; wherein the upper conductive line is electrically connected to the upper conductive contacts (Iwayama teaches, in Figs. 1-2, MTJ element is connected between the lower electrode LE and the upper electrode UE, and that the upper electrode UE is connected to the bit line BL2 via contact plugs PLG4 and PLG5. Iwayama also teaches that a silicon nitride film 70 and a silicon oxide film 80 are provided on the upper electrode UE, and that interlayer dielectric film ILD2 covers those layers. Thus, Iwayama teaches a distinct plug-type contact structure above the MTJ stack and an upper conductive line (BL2) electrically connected to that contact structure (UE). In view of the two-dimensional arrangement of data storage structures 150 in Lee, applying the plug-contact architecture of Lee yields a plurality of upper conductive contacts respectively on corresponding data storage patterns and spaced apart in the first direction).
Lee is further silent regarding
a plurality of voids in the cell dielectric layer; and
wherein the plurality of voids are free of overlap with the upper conductive contacts in a second direction perpendicular to the top surface of the substrate.
However, Lung teaches
a plurality of voids in the cell dielectric layer (Lung, Fig. 11A, teaches a memory cell level including an array of memory pillars disposed in cross-points between first and second access lines, with memory pillars lined by dielectric liners 1102, and airgaps or voids 1104 formed between the memory pillars. Lung also expressly teaches that a memory cell level includes voids surrounding the memory pillars in the array. Accordingly, Lung teaches voids in dielectric material between adjacent storage structures in a dense memory array).
Regarding the limitation “wherein the plurality of voids are free of overlap with the upper conductive contacts in a second direction perpendicular to the top surface of the substrate”, Lung teaches voids 1104 between adjacent memory pillars 121, 122, 123, while Iwayama teaches the contact structure PLG4/PLG5 on the top side of the storage stack at upper electrode UE. Thus, the combination teaches voids laterally between neighboring storage structures and upper conductive contacts on the storage structures, such that the voids are free of overlap with the upper conductive contacts in the vertical (second) direction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor memory device of Lee to include the plug-type upper-contact / upper-line structure taught by Iwayama, in order to electrically connect the upper portion of each storage structure to an overlying bit line through a distinct contact-plug interconnect structure. It would further have been obvious to modify the dielectric surrounding the storage structures of Lee in view of Lung, because Lung teaches dielectric liners and air gaps or voids between the neighboring memory pillars in a very high-density memory architecture, in order to provide dielectric/void isolation between adjacent storage structures while supporting dense memory integration.
Claims 2-11, 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170324025 A1) in view of Iwayama (US 20120056253 A1) further in view of Lung (US 20190355903 A1) and further in view of Han (US 20180350875 A1).
RE: Claim 2, Lee, Iwayama and Lung disclose all the limitations of claim 1 on which this claim depends. Lee, Iwayama and Lung are silent regarding
further comprising an upper dielectric layer on the cell dielectric layer, wherein the plurality of voids are between the upper dielectric layer and the lower dielectric layer.
However, Han teaches
further comprising an upper dielectric layer on the cell dielectric layer, wherein the plurality of voids are between the upper dielectric layer and the lower dielectric layer (Han teaches, in Fig. 2 and ¶ [0036], upper insulating layer 150 disposed on cap insulating layer 140 in the cell region CR. Han further describes the cell-region dielectric stack as including second lower insulating layer 130, cap insulating layer 140, and upper insulating layer 150, sequentially stacked. Lung teaches the voids between neighboring memory pillars, and Han teaches the stacked dielectric arrangement above and below the MTJ region).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the claim 1 device to further include an upper dielectric layer on the cell dielectric layer as taught by Han in order to provide the cell region with a stacked interlayer dielectric structure having desired dielectric characteristics, as expressly suggested by Han’s teaching that the cell region and peripheral region may have different interlayer dielectric structures and that the upper insulating layer may be used to provide desired characteristics, including reduced parasitic capacitance (Han, ¶ [0036]). In the resulting combined structure, the voids taught by Lung would remain in the dielectric region between neighboring storage structures, while the added upper dielectric layer overlies that cell-dielectric region and the inherited lower dielectric layer underlies it; thus, the plurality of voids would be between the upper dielectric layer and the lower dielectric layer, as claimed.
RE: Claim 3, Lee, Iwayama, Lung and Han disclose all the limitations of claim 2 on which this claim depends.
Han further teaches
wherein the upper conductive contacts extend into the upper dielectric layer (Han teaches, in Fig. 2 and ¶ [0034] first top contact 152 disposed on the cell region CR, where the first top contact 152 penetrates the first portion 150_1 of the upper insulating layer 150) and an upper portion of the cell dielectric layer and are respectively electrically connected to the data storage patterns (Han teaches, in Fig. 2 and ¶ [0030], that the cap insulating layer 140 remains in the gap between adjacent MTJ patterns and lies directly below the upper insulating layer 150 in the cell-region dielectric stack; the first top contact 152 extends downward in that stacked dielectric environment to reach the conductive mask pattern on the storage stack. This read is strengthened by Iwayama, which teaches plug contacts PLG4/PLG5 extending through overlying dielectric material to the upper electrode UE. Han further teaches that first top contact 152 is electrically connected to the corresponding conductive mask pattern CMP on the MTJ pattern, and Iwayama teaches the same basic concept through upper electrode UE connected upward via PLG4/PLG5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of claim 2 to provide upper conductive contacts that extend into the added upper dielectric layer and into an upper portion of the cell dielectric layer, because Han teaches first top contact 152 penetrating the first portion 150_1 of upper insulating layer 150 and electrically connecting to the corresponding conductive mask pattern CMP on the MTJ stack, and Iwayama teaches plug-type contact PLG4/PLG5 connecting the upper electrode UE to the upper interconnect level, in order to electrically connect the storage pattern stack to an overlying interconnect through a defined vertical contact structure extending through the upper dielectric region.
RE: Claim 4, Lee, Iwayama, Lung and Han disclose all the limitations of claim 3 on which this claim depends.
Lee and Iwayama further teach
wherein each of the data storage patterns comprises a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are stacked in a third direction on the lower dielectric layer, wherein the third direction is perpendicular to the top surface of the substrate (Lee teaches, in Fig. 3 and ¶ [0027] that each data storage structure 150 includes bottom electrode 120, data storage section 130, and top electrode 140, and, in ¶ [0042], that the data storage section 130 includes an MTJ stack on the bottom electrode 120. As shown in Fig. 3, bottom electrode 120, data storage structure section 130 and top electrode 140 are stacked in perpendicular direction to the substrate surface in the cited cross-sectional structure), wherein the top electrode is between the magnetic tunnel junction pattern and each of the upper conductive contacts, and wherein each of the upper conductive contacts is in contact with the top electrode (Lee teaches, in Fig. 3, the first part of this limitation by expressly disclosing top electrode 140 above the MTJ-containing data storage section 130. Iwayama teaches, in Figs. 2-4 and ¶ [0026], the remaining contact relationship by disclosing an MTJ element formed on lower electrode material 101, and upper electrode UE above the MTJ, and a contact plug PLG4 that penetrates overlying dielectric layers and is electrically connected to upper electrode UE. Thus, the combination teaches a structure in which the top electrode is between the MTJ pattern and the upper conductive contact, and the upper conductive contact is in contact with the top electrode).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the top-electrode/contact arrangement of Iwayama with the stacked MTJ data-storage structure of Lee, in order to provide a defined electrical connection from the overlying contact structure to the top electrode of each MTJ storage stack. Iwayama expressly teaches that the upper electrode UE is connected upward through contact plug PLG4 toward the upper interconnect level, which would have suggested forming the contact on the top electrode of the storage stack taught by Lee.
RE: Claim 5, Lee, Iwayama, Lung and Han disclose all the limitations of claim 3 on which this claim depends.
Han further teaches
wherein top surfaces of the upper conductive contacts are free of the upper dielectric layer thereon (Han teaches, in Fig. 2 and ¶ [0034], first top contact 152 is formed in the first portion 150_1 of the upper insulating layer 150, and that an upper line 160 is formed on the upper insulating layer 150 and is electrically connected to the first contact 152. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention from this disclosed structure that the top surface of first top contact 152 is free of the upper insulating layer thereon at the electrical-connection region; otherwise, the upper line 160 could not be electrically connected to the first top contact 152 as taught).
RE: Claim 6, Lee, Iwayama, Lung and Han disclose all the limitations of claim 5 on which this claim depends.
Iwayama and Han further teach
further comprising an interlayer dielectric layer on the upper dielectric layer (Iwayama teaches after formation of the MTJ / upper-electrode structure and contact plug PLG4, interlayer dielectric film ILD3 is disposed and flattened, and that by repeating deposition of the interlayer dielectric film and formation of the contact plug, the final multilayer interconnect structure is obtained. Applied to the inherited upper insulating layer 150 of Han, this teaches an interlayer dielectric layer on the upper dielectric layer in the upper dielectric layer), wherein the interlayer dielectric layer overlaps a top surface of the upper dielectric layer and extends onto the top surfaces of the upper conductive contacts (Han teaches, in Fig. 2, the upper dielectric layer (upper insulating layer 150) and upper conductive contacts 152 penetrating the upper insulating layer, and upper line 160 electrically connected to the first top contact. Iwayama teaches, in Fig. 1, subsequent ILD3 deposition above the contacted upper-electrode structure in a repeated interconnect build-up. Thus, the combination teaches depositing the interlayer dielectric over the top surface of the upper dielectric layer and over the topography including the top surfaces of the upper conductive contacts).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of claim 5 to further include an interlayer dielectric layer on the upper dielectric layer as taught by Iwayama, in order to build an upper interconnect dielectric level over the contacted MTJ region for subsequent plug/line formation in a multilayer wiring structure. It would have been further obvious to form that interlayer dielectric over the upper insulating layer 150 / first top contact 152 topography taught by Han, such that the interlayer dielectric overlaps the top surface of the upper dielectric and extend onto the top surfaces of the upper conductive contacts, because Iwayama expressly teaches repeated dielectric deposition and plug formation above the contacted upper-electrode structure, while Han expressly teaches a top contact in the upper dielectric region with an upper line electrically landing on it.
RE: Claim 7, Lee, Iwayama, Lung and Han disclose all the limitations of claim 6 on which this claim depends.
Lee and Iwayama further teach
further comprising a plurality of upper vias in the interlayer dielectric layer and respectively on the upper conductive contacts (Iwayama teaches, in Fig. 1 and ¶¶ [0012] - [0014], successive contact plugs PLG4 and PLG5 between the upper electrode UE and bit line BL2, with the plugs surrounded by interlayer dielectric films ILD1-ILD5. This teaches an upper-via-type plug in an interlayer dielectric on an underlying contact structure), wherein the upper vias extend into the interlayer dielectric layer and are respectively electrically connected to the upper conductive contacts (Iwayama teaches, in Fig. 1 and ¶ [0012], ¶ [0024], that PLG4 penetrates ILD2 to the storage-stack top side, and that the upper electrode is connected upward to BL2 via PLG4 and PLG5, while successive interlayer dielectric films and successive plug formations are repeated in the multilayer wiring buildup. That teaches a via extending into an interlayer dielectric and electrically connected to the underlying contact structure), wherein the upper conductive lines are on the interlayer dielectric layer and are electrically connected to the respective ones of the upper conductive contacts through respective ones of the upper vias (Iwayama teaches bit lines BL2 connected to the storage-stack top side through PLG4 and PLG5, which teaches an upper conductive line electrically connected to an underlying contact structure through an upper-via plug arrangement in the overlying dielectric stack), and wherein the respective ones of the upper vias are spaced apart from each other in the first direction (Lee, in Fig. 1 and ¶ [0027], teaches that the corresponding storage structures are arranged along first direction D1, and Iwayama teaches, in ¶ [0013], that bit lines BL1 and BL2 extend in a column direction and are shifted in the row direction, and that UE is connected to Bl2 through PLG4 and PLG5. This, in the combined array structure, the corresponding upper vias are provided as a plurality spaced apart along the first direction).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of claim 6 to further include upper vias in the interlayer dielectric layer respectively on the upper conductive contacts, because Iwayama teaches a stacked plug arrangement in which an upper interconnect level is reached through successive contact plugs in successive interlayer dielectric levels, specifically PLG4/PLG5 between the storage-stack top side and BL2, in order to electrically connect the upper conductive line to the underlying contact structure through an upper-via level in a multilayer interconnect stack. Applying that teaching to the claim 6 device, which already includes an upper dielectric layer, upper conductive contacts, and an interlayer dielectric layer, would have yielded upper vias extending into the interlayer dielectric and electrically connecting the upper conductive line to the underlying upper conductive contact.
RE: Claim 8, Lee, Iwayama and Lung disclose all the limitations of claim 1 on which this claim depends.
Lee, Iwayama and Lung are silent regarding
wherein the lower dielectric layer has a recessed top surface that is recessed toward the substrate between the ones of the data storage patterns, wherein each of the plurality of voids overlaps the recessed top surface of the lower dielectric layer in a third direction, and wherein the third direction is perpendicular to the top surface of the substrate.
However, Han teaches
wherein the lower dielectric layer has a recessed top surface that is recessed toward the substrate between the ones of the data storage patterns (Han teaches, in Fig. 2 and ¶ [0027], second lower insulating layer 130 with concave portions 130a recessed toward substrate 100 between the adjacent MTJ patterns), wherein each of the plurality of voids overlaps the recessed top surface of the lower dielectric layer in a third direction, and wherein the third direction is perpendicular to the top surface of the substrate (Lung teaches, in fig. 11A, voids 1104 between neighboring memory pillars 1102 (as explained in claim 1 rejection above), and Han teaches the recessed concave portions 130a in the lower dielectric beneath the gap region between adjacent MTJ patterns; thus, the combination teaches voids overlapping the recessed top surface of the lower dielectric layer vertically, i.e., perpendicular to the top of substrate surface).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of claim 1 to provide the lower dielectric layer with the recesses top-surface profile taught by Han, in order to form a controlled recessed dielectric region, between adjacent LTJ storage structures while accommodating dielectric material in the gap region and improve cell-region electrical characteristics, as taught by the concave-portion/cap-insulator structure of Han. Applying that recessed lower-dielectric profile to the claim 1 device, which already includes voids between adjacent storage structures, would have yielded a structure in which the voids overlap the recessed top surface of the lower dielectric layer in the vertical direction.
RE: Claim 9, Lee, Iwayama, Lung and Han disclose all the limitations of claim 8 on which this claim depends.
Lee and Han further teach
further comprising a plurality of lower electrode contacts in the lower dielectric layer and respectively on bottom surfaces of the data storage patterns (Lee teaches, in Fig. 3 and ¶¶ [0026] -[0027], cell contact plugs 116 penetrate the second interlayer dielectric layer 114 and are electrically connected to the corresponding data storage structures 150 through the bottom of electrodes 120 ), wherein the lower electrode contacts extend into the lower dielectric layer and are respectively electrically connected to the data storage patterns (Lee teaches that the cell contact plugs 116 penetrate the second interlayer dielectric layer 114 and are electrically connected to the corresponding data storage structures 150 through the bottom electrodes 120), and wherein the recessed top surface of the lower dielectric layer is at a height in the third direction that is lower than a height of top surfaces of the lower electrode contacts in the third direction, with the top surface of the substrate providing a base reference plane (Lee teaches, in ¶ [0026], that the cell contact plugs 116 have top surfaces substantially coplanar with the top surface of second interlayer dielectric layer 114, and Han teaches, in Fig. 2 and ¶ [0025], the concave portions 130a recessed downward in the top surface of the lower dielectric between adjacent MTJ patterns; therefore, the combination teaches the recessed lower-dielectric surface being lower than the top surfaces of the lower electrode contacts).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of claim 8 combination to include the lower-electrode-contact arrangement taught by Lee, in order to preserve reliable electrical connection to each storage stack thorough cell contact plugs 116 while using the concave lower-dielectric profile of Han to shape the inter-pattern dielectric region.
RE: Claim 10, Lee, Iwayama and Lung disclose all the limitations of claim 1 on which this claim depends.
Lee, Iwayama and Lung are silent regarding
wherein the substrate comprises a cell region and a peripheral region, wherein the lower dielectric layer is on the cell region and extends onto the peripheral region, wherein the data storage patterns, the cell dielectric layer, the plurality of voids, the upper conductive contacts, and the upper conductive lines are on the cell region, wherein a first portion of the lower dielectric layer on the cell region has a recessed top surface that is recessed toward the substrate between the ones of the data storage patterns, wherein a second portion of the lower dielectric layer on the peripheral region has a top surface at a height in a third direction that is lower than a height of the recessed top surface of the first portion of the lower dielectric layer in the third direction, with the top surface of the substrate providing a base reference plane, and wherein the third direction is perpendicular to the top surface of the substrate.
However, Han teaches
wherein the substrate comprises a cell region and a peripheral region (Han teaches a substrate 100 including cell region CR and peripheral region PR),
wherein the lower dielectric layer is on the cell region and extends onto the peripheral region (Han teaches, in Fig. 2, first lower insulating layer 110 on both cell region CR and peripheral region PR),
wherein a first portion of the lower dielectric layer on the cell region has a recessed top surface that is recessed toward the substrate between the ones of the data storage patterns (Han teaches, in Fig. 1 and ¶ [0046], this most directly with first portion 130_1 of second lower insulating layer 130 on the cell region, whose top surface includes concave portions 130a recessed towards substrate 100 between adjacent magnetic tunnel junction pattern MTJ. The cap dielectric filling that recessed region is top cap insulating layer 140, specifically first portion 140_1 in the cell region),
wherein a second portion of the lower dielectric layer on the peripheral region has a top surface at a height in a third direction that is lower than a height of the recessed top surface of the first portion of the lower dielectric layer in the third direction, with the top surface of the substrate providing a base reference plane (Han teaches, in Fig. 4 and ¶ [0047], that second portion 130_2 has a top surface lower than that of first portion 130_1. Han also teaches, in Fig. 4, top surface of 130_2 is lower than the top surface of the recessed concave portion 130a of first portion 130_1, in vertical direction with reference to the top surface of the substrate 100), and
wherein the third direction is perpendicular to the top surface of the substrate (Han, Fig. 4, vertical direction normal to substrate 100 in the cross-sectional structure).
Regarding the limitation “wherein the data storage patterns, the cell dielectric layer, the plurality of voids, the upper conductive contacts, and the upper conductive lines are on the cell region”, Lee, in Fig. 1-3, teaches data storage structure 150, mold layer 118 second conductive lines 182 on cell region CR. Further, Lung, in Figs. 1 and 11A and also ¶ [0022], teaches memory pillars 121, 122, 123 and voids/ airgaps between neighboring pillars, with dielectric liner 208 around the pillars, thus in the cell region. For the upper-contact in the current set, Iwayama teaches the storage-side upper connection through upper electrode UE, contact plugs PLG4 and PLG5, and bit line BL2 are all in memory cell (MC), thus are on the cell region).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of claim 1 in view of Han to provide a substrate having a cell region and a peripheral region and to form the lower dielectric with a cell region portion having a recessed top surface between adjacent storage patterns and a peripheral-region portion at a lower level, because Han teaches exactly such a cell/peripheral-region dielectric arrangement for MTJ memory structures, in order to provide different interlayer-dielectric structures in the cell region and the peripheral region and thereby obtain desired electrical characteristics, such as reduced parasitic capacitance.
RE: Claim 11, Lee, Iwayama, Lung and Han disclose all the limitations of claim 10 on which this claim depends.
Lung and Han further teach
further comprising a peripheral dielectric layer on the lower dielectric layer and on the peripheral region, wherein the cell dielectric layer comprises a dielectric material having a dielectric constant that is greater than a dielectric constant of the peripheral dielectric layer (Han teaches cell region CR and peripheral region PR, teaches dielectric structures in those regions, and teaches that upper insulating layer 150 may be low-k to reduce parasitic capacitance. That gives the peripheral low-k/ reduced parasitic capacitance characteristics of peripheral dielectric layer. Lung teaches, in ¶ [0034], that the dielectric liner 208 in the memory structure can be a high dielectric constant material. That gives the higher-k dielectric in the cell/memory structure side. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select the dielectric constants of the cell-region dielectric and the peripheral-region dielectric as different materials, with cell dielectric having a higher dielectric constant and the peripheral dielectric having a lower dielectric constant, because Han and Lung recognize dielectric constant as affecting electrical behavior in these regions: Han teaches using a low-k dielectric structure in the peripheral region to reduce parasitic capacitance, while lung teaches using a high-k dielectric liner in the memory/cell structure. A person of ordinary skill in the art would therefore have treated dielectric constant as a result effecting variable and would have optimized/selectively chosen higher-k dielectric for the cell region and lower-k dielectric for the peripheral region in order to balance cell region dielectric performance with reduced peripheral region parasitic capacitance.
RE: Claim 13, Lee, Iwayama and Lung disclose all the limitations of claim 12 on which this claim depends. Lee, Iwayama and Lung are silent regarding
further comprising an upper dielectric layer on the cell dielectric layer, wherein the plurality of voids are between the upper dielectric layer and the lower dielectric layer.
However, Han teaches
further comprising an upper dielectric layer on the cell dielectric layer, wherein the plurality of voids are between the upper dielectric layer and the lower dielectric layer (Han teaches, in Fig. 2 and ¶ [0036], upper insulating layer 150 disposed on cap insulating layer 140 in the cell region CR. Han further describes the cell-region dielectric stack as including second lower insulating layer 130, cap insulating layer 140, and upper insulating layer 150, sequentially stacked. Lung teaches the voids between neighboring memory pillars, and Han teaches the stacked dielectric arrangement above and below the MTJ region).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the claim 12 device to further include an upper dielectric layer on the cell dielectric layer as taught by Han in order to provide the cell region with a stacked interlayer dielectric structure having desired dielectric characteristics, as expressly suggested by Han’s teaching that the cell region and peripheral region may have different interlayer dielectric structures and that the upper insulating layer may be used to provide desired characteristics, including reduced parasitic capacitance (Han, ¶ [0036]). In the resulting combined structure, the voids taught by Lung would remain in the dielectric region between neighboring storage structures, while the added upper dielectric layer overlies that cell-dielectric region and the inherited lower dielectric layer underlies it; thus, the plurality of voids would be between the upper dielectric layer and the lower dielectric layer, as claimed.
RE: Claim 14, Lee, Iwayama, Lung and Han disclose all the limitations of claim 13 on which this claim depends.
Han further teaches
wherein the upper conductive contacts extend into the upper dielectric layer (Han teaches, in Fig. 2 and ¶ [0034] first top contact 152 disposed on the cell region CR, where the first top contact 152 penetrates the first portion 150_1 of the upper insulating layer 150) and the upper portion of the cell dielectric layer and are respectively electrically connected to the data storage patterns (Han teaches, in Fig. 2 and ¶ [0030], that the cap insulating layer 140 remains in the gap between adjacent MTJ patterns and lies directly below the upper insulating layer 150 in the cell-region dielectric stack; the first top contact 152 extends downward in that stacked dielectric environment to reach the conductive mask pattern on the storage stack. This read is strengthened by Iwayama, which teaches plug contacts PLG4/PLG5 extending through overlying dielectric material to the upper electrode UE. Han further teaches that first top contact 152 is electrically connected to the corresponding conductive mask pattern CMP on the MTJ pattern, and Iwayama teaches the same basic concept through upper electrode UE connected upward via PLG4/PLG5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of claim 13 to provide upper conductive contacts that extend into the added upper dielectric layer and into an upper portion of the cell dielectric layer, because Han teaches first top contact 152 penetrating the first portion 150_1 of upper insulating layer 150 and electrically connecting to the corresponding conductive mask pattern CMP on the MTJ stack, and Iwayama teaches plug-type contact PLG4/PLG5 connecting the upper electrode UE to the upper interconnect level, in order to electrically connect the storage pattern stack to an overlying interconnect through a defined vertical contact structure extending through the upper dielectric region.
RE: Claim 15, Lee, Iwayama, Lung and Han disclose all the limitations of claim 14 on which this claim depends.
Lee and Iwayama further teach
wherein each of the data storage patterns comprises a magnetic tunnel junction pattern; and, a top electrode is between the magnetic tunnel junction pattern and each of the upper conductive contacts, and wherein each of the upper conductive contacts is in contact with the top electrode ((Lee teaches, in Fig. 3 and ¶ [0027] that each data storage structure 150 data storage section 130, and top electrode 140. Lee further teaches, in Fig. 3, the first part of this limitation by expressly disclosing top electrode 140 above the MTJ-containing data storage section 130. Iwayama teaches, in Figs. 2-4 and ¶ [0026], the remaining contact relationship by disclosing an MTJ element formed on lower electrode material 101, and upper electrode UE above the MTJ, and a contact plug PLG4 that penetrates overlying dielectric layers and is electrically connected to upper electrode UE. Thus, the combination teaches a structure in which the top electrode is between the MTJ pattern and the upper conductive contact, and the upper conductive contact is in contact with the top electrode).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the top-electrode/contact arrangement of Iwayama with the stacked MTJ data-storage structure of Lee, in order to provide a defined electrical connection from the overlying contact structure to the top electrode of each MTJ storage stack. Iwayama expressly teaches that the upper electrode UE is connected upward through contact plug PLG4 toward the upper interconnect level, which would have suggested forming the contact on the top electrode of the storage stack taught by Lee.
RE: Claim 16, Lee, Iwayama, Lung and Han disclose all the limitations of claim 14 on which this claim depends.
Lee and Han further teach
further comprising a plurality of lower electrode contacts in the lower dielectric layer and respectively on bottom surfaces of the data storage patterns (Lee teaches, in Fig. 3 and ¶¶ [0026] -[0027], cell contact plugs 116 penetrate the second interlayer dielectric layer 114 and are electrically connected to the corresponding data storage structures 150 through the bottom of electrodes 120 ), wherein the lower electrode contacts extend into the lower dielectric layer and are respectively electrically connected to the data storage patterns (Lee teaches that the cell contact plugs 116 penetrate the second interlayer dielectric layer 114 and are electrically connected to the corresponding data storage structures 150 through the bottom electrodes 120),
wherein the lower dielectric layer has a recessed top surface that is recessed toward the substrate between the ones of the data storage patterns (Han teaches, in Fig. 2 and ¶ [0027], second lower insulating layer 130 with concave portions 130a recessed toward substrate 100 between the adjacent MTJ patterns),
wherein the recessed top surface of the lower dielectric layer is at a height in a second direction that is lower than a height of top surfaces of the lower electrode contacts in the second direction, with the top surface of the substrate providing a base reference plane, and wherein the second direction is perpendicular to the top surface of the substrate (Lee teaches, in ¶ [0026], that the cell contact plugs 116 have top surfaces substantially coplanar with the top surface of second interlayer dielectric layer 114, and Han teaches, in Fig. 2 and ¶ [0025], the concave portions 130a recessed downward in the top surface of the lower dielectric between adjacent MTJ patterns; therefore, the combination teaches the recessed lower-dielectric surface being lower than the top surfaces of the lower electrode contacts in the direction perpendicular to the top of substrate surface);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of claim 14 combination to include the lower-electrode-contact arrangement taught by Lee, in order to preserve reliable electrical connection to each storage stack thorough cell contact plugs 116 while using the concave lower-dielectric profile of Han to shape the inter-pattern dielectric region.
RE: Claim 17, Lee, Iwayama, Lung and Han disclose all the limitations of claim 16 on which this claim depends.
Lung and Han further teach
wherein each of the plurality of voids overlaps the recessed top surface of the lower dielectric layer in the second direction (Lung teaches, in fig. 11A, voids 1104 between neighboring memory pillars 1102 (as explained in claim 12 rejection above), and Han teaches the recessed concave portions 130a in the lower dielectric beneath the gap region between adjacent MTJ patterns; thus, the combination teaches voids overlapping the recessed top surface of the lower dielectric layer vertically, i.e., perpendicular to the top of substrate surface).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to align the between-structure voids 1104 of Lung with the between-structure recessed dielectric profile of Han, in order to provide a controlled inter-pattern gap region in which the void/airgap isolation is positioned above the recessed lower-dielectric surface between adjacent storage structures, thereby supporting dense-memory isolation in the gap region. In the resulting combined structure, because concave portions 130a are located between adjacent MTJP and voids 1104 are likewise located between adjacent memory pillars, each void would overlap the recessed top surface of the lower dielectric layer in the vertical, i.e., second direction.
RE: Claim 18, Lee, Iwayama, and Lung disclose all the limitations of claim 12 on which this claim depends.
Lee, Iwayama, and Lung are silent regarding
wherein the substrate comprises a cell region and a peripheral region, wherein the lower dielectric layer is on the cell region and extends onto the peripheral region, wherein the data storage patterns, the cell dielectric layer, the plurality of voids, the upper conductive contacts, and the upper conductive line are on the lower dielectric layer and on the cell region, wherein the semiconductor device further comprises a peripheral dielectric layer on the lower dielectric layer and on the peripheral region, and wherein the cell dielectric layer comprises a dielectric material having a dielectric constant that is greater than a dielectric constant of the peripheral dielectric layer.
However, Han teaches
wherein the substrate comprises a cell region and a peripheral region (Han teaches a substrate 100 including cell region CR and peripheral region PR),
wherein the lower dielectric layer is on the cell region and extends onto the peripheral region (Han teaches, in Fig. 2, first lower insulating layer 110 on both cell region CR and peripheral region PR),
Regarding the limitation “wherein the data storage patterns, the cell dielectric layer, the plurality of voids, the upper conductive contacts, and the upper conductive line are on the lower dielectric layer and on the cell region”, Lee, in Fig. 1-3, teaches data storage structure 150, mold layer 118 second conductive lines 182 on cell region CR. Further, Lung, in Figs. 1 and 11A and also ¶ [0022], teaches memory pillars 121, 122, 123 and voids/ airgaps between neighboring pillars, with dielectric liner 208 around the pillars, thus in the cell region. For the upper-contact in the current set, Iwayama teaches the storage-side upper connection through upper electrode UE, contact plugs PLG4 and PLG5, and bit line BL2 are all in memory cell (MC), thus are on the cell region. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of claim 12 in view of Han to provide a substrate having a cell region and a peripheral region and to form the lower dielectric with a cell region portion having a recessed top surface between adjacent storage patterns and a peripheral-region portion at a lower level, because Han teaches exactly such a cell/peripheral-region dielectric arrangement for MTJ memory structures, in order to provide different interlayer-dielectric structures in the cell region and the peripheral region and thereby obtain desired electrical characteristics, such as reduced parasitic capacitance.
Regarding the limitation “wherein the semiconductor device further comprises a peripheral dielectric layer on the lower dielectric layer and on the peripheral region, and wherein the cell dielectric layer comprises a dielectric material having a dielectric constant that is greater than a dielectric constant of the peripheral dielectric layer”, Han teaches cell region CR and peripheral region PR, teaches dielectric structures in those regions, and teaches that upper insulating layer 150 may be low-k to reduce parasitic capacitance. That gives the peripheral low-k/ reduced parasitic capacitance characteristics of peripheral dielectric layer. Lung teaches, in ¶ [0034], that the dielectric liner 208 in the memory structure can be a high dielectric constant material. That gives the higher-k dielectric in the cell/memory structure side. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select the dielectric constants of the cell-region dielectric and the peripheral-region dielectric as different materials, with cell dielectric having a higher dielectric constant and the peripheral dielectric having a lower dielectric constant, because Han and Lung recognize dielectric constant as affecting electrical behavior in these regions: Han teaches using a low-k dielectric structure in the peripheral region to reduce parasitic capacitance, while lung teaches using a high-k dielectric liner in the memory/cell structure. A person of ordinary skill in the art would therefore have treated dielectric constant as a result effecting variable and would have optimized/selectively chosen higher-k dielectric for the cell region and lower-k dielectric for the peripheral region in order to balance cell region dielectric performance with reduced peripheral region parasitic capacitance.
RE: Claim 19, Lee, Iwayama, Lung and Han disclose all the limitations of claim 16 on which this claim depends.
Han further teaches
wherein a first portion of the lower dielectric layer on the cell region has a recessed top surface that is recessed toward the substrate between the ones of the data storage patterns (Han teaches, in Fig. 1 and ¶ [0046], this most directly with first portion 130_1 of second lower insulating layer 130 on the cell region, whose top surface includes concave portions 130a recessed towards substrate 100 between adjacent magnetic tunnel junction pattern MTJ. The cap dielectric filling that recessed region is top cap insulating layer 140, specifically first portion 140_1 in the cell region),
wherein a second portion of the lower dielectric layer on the peripheral region has a top surface at a height in a second direction that is lower than a height of the recessed top surface of the first portion of the lower dielectric layer in the second direction, with the top surface of the substrate providing a base reference plane (Han teaches, in Fig. 4 and ¶ [0047], that second portion 130_2 has a top surface lower than that of first portion 130_1. Han also teaches, in Fig. 4, top surface of 130_2 is lower than the top surface of the recessed concave portion 130a of first portion 130_1, in vertical direction with reference to the top surface of the substrate 100),
wherein the second direction is perpendicular to the top surface of the substrate (Han, Fig. 4, vertical direction normal to substrate 100 in the cross-sectional structure), and
wherein the peripheral dielectric layer is in contact with the top surface of the second portion of the lower dielectric layer (Han teaches the second portion of the cap insulating layer on the peripheral region is removed, leaving the second portion of the lower insulating layer exposed, and then an upper insulating layer 150 is formed over the surface of the substrate, with a second portion 150_2 in the peripheral region. In the embodiment where the second portion 130_2 of the lower insulating layer remains, this teaching supports the peripheral region dielectric being formed on and contacting the top surface of that second portion).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of claim 18 to adopt the cell/peripheral-region lower-dielectric topography taught by Han, in order to provide different dielectric topography structures in the cell region and the peripheral-region dielectric structure for desired electrical characteristics, such as reduced parasitic capacitance.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
Seto (US 20160072047 A1) and Jeon (US 20130126996 A1) disclose semiconductor device with magnetic memory stack structure.
Conclusion
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/BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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