Prosecution Insights
Last updated: October 22, 2026
Application No. 18/405,361

SEMICONDUCTOR MEMORY DEVICE

Non-Final OA §102
Filed
Jan 05, 2024
Priority
Feb 15, 2023 — RE 10-2023-0020375
Examiner
WARREN, MATTHEW E
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
895 granted / 1020 resolved
+19.7% vs TC avg
Minimal +5% lift
Without
With
+5.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
15 currently pending
Career history
1038
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
52.1%
+12.1% vs TC avg
§102
35.3%
-4.7% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1020 resolved cases

Office Action

§102
DETAILED ACTION This Office Action is in response to the Election filed on July 31, 2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Species A, claims 1-9 in the reply filed on July 31, 2026 is acknowledged. The traversal is on the ground(s) that there is no serious search burden. This is not found persuasive because the species have been identified by the separate and distinct embodiments, in this case the drawing figures. The distinct embodiments require a different field of search and/or search queries. The requirement is still deemed proper and is therefore made FINAL. Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, and 7-9 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim et al. (US 9,837,155 B1). In re claim 1, Kim et al. shows (figs. 17, 18F) a semiconductor memory device, comprising: a substrate; a semiconductor pattern (110) on the substrate, wherein the semiconductor pattern includes, a source region (112) having a first conductivity type (n), a drain region (110) having a second conductivity type (p), and an intrinsic region (i, 114) between the source region and the drain region; first and second gate electrodes (WL1, WL2) on the intrinsic region; a ferroelectric pattern (122c, 132c; col. 25, [col. 25, lines 1-9], hafnium oxide is a ferroelectric) between the intrinsic region and the first and second gate electrodes; and a gate dielectric pattern (122a, 132b) between the ferroelectric pattern and the intrinsic region. In re claim 2, Kim et al. shows (figs. 17, 18F) a dielectric pillar (209) on the substrate, wherein the semiconductor pattern surrounds a sidewall of the dielectric pillar. In re claims 7 and 8, Kim et al. shows (figs. 17, 18F) wherein each of the first and second gate electrodes surrounds the semiconductor pattern and is perpendicular to a top surface of the substrate. The ferroelectric pattern surrounds the semiconductor pattern. In re claim 9, Kim et al. discloses (col. 25, lines 1-9) the ferroelectric pattern includes at least one of HfO₂, HfSiO₂, HfAIO₂, HfSiON, HfZnO, HfZrO₂, ZrO₂, ZrSiO₂, HfZrSiO₂, ZrSiON, LaAlO, HfDyO2, or HfScO2. Allowable Subject Matter Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yoo et al. (US 10,475,814 B2), Song (US Pub. 2024/0220148 A1), and Kim (US 11,943,925 B2). Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KRETELIA GRAHAM can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jan 05, 2024
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772457
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
3y 3m to grant Granted Oct 20, 2026
Patent 12762388
Ferroelectric Memory Device And Electronic Device Including The Same
3y 11m to grant Granted Oct 13, 2026
Patent 12764967
BACK-END ACTIVE DEVICE AND LOGIC GATE
2y 7m to grant Granted Oct 13, 2026
Patent 12757374
MEMORY DEVICE INCLUDING CAPACITOR CONTACTS HAVING DIFFERENT MATERIALS AND METHOD FOR PREPARING THE SAME
2y 8m to grant Granted Oct 06, 2026
Patent 12751025
INSULATING-GATE BIPOLAR TRANSISTORS INCLUDING A REVERSE CONDUCTING DIODE
3y 1m to grant Granted Sep 29, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.0%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1020 resolved cases by this examiner. Grant probability derived from career allowance rate.

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