Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of species I, Figs. 1-3, and 5-6 in the reply filed on 07/26/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, and 8-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent Application Publication by Kwak (US 20220139916 A1).
Regarding claim 1, Kwak discloses a semiconductor device, comprising:
a lower structure (LS);
a plurality of horizontal conductive layers (ACT) oriented in a direction parallel to a surface of the lower structure (Para. 29, “The active layer ACT may be oriented parallel to the plane of the substrate LS”);
a plurality of reservoir capacitors (CAP) commonly coupled to first-side ends of the horizontal conductive layers (Para. 34, “the capacitor CAP may be electrically connected to a second edge portion of the active layer ACT”), wherein each of the plurality of the reservoir capacitors is vertically stacked over the lower structure, and includes a cylindrical storage node (Fig. 3, where the reservoir capacitors CAP are stacked over lower structure LS, Claim 4, where each of the reservoir capacitors includes a cylindrical storage node); and
a vertical conductive line (WL) commonly coupled to second-side ends opposite to first-side ends of the horizontal conductive layers (Each of the horizontal conductive structure ACT is planar with a square hole in the middle. The inside of the square hole can be understood to be second-side ends of the horizontal conductive structure, and in Para. 30, the gate dielectric layer couples the vertical conductive line WL to the horizontal conductive structure ACT at the second-side end), extending in a direction perpendicular or substantially perpendicular to the surface of the lower structure (Para. 23, “word line WL may be vertically oriented along the first direction D1 perpendicular to an upper surface of the substrate LS”), and including a plurality of electrode portions (SD1/2), each electrode portion being symmetrical with the cylindrical storage node of a corresponding reservoir capacitor (Examiner note that symmetrical could be interpreted in many ways. Using Broadest reasonable interpretation, symmetrical can be see as the electrodes are symmetrical in height, See Fig. 3, where the height of the electrodes SD1/2 is symmetrical in height to the cylindrical storage nodes of adjacent reservoir capacitors).
Regarding claim 2, Kwak discloses the semiconductor device of claim 1, and further wherein each of the reservoir capacitors includes:
cylindrical storage nodes (SN) respectively coupled to the first-side ends of the horizontal conductive layers (Para. 36, “The storage node SN may be electrically connected to the second source/drain region SD2”);
a dielectric layer (DE) covering the storage nodes (Fig. 2, Where dielectric layer DE covers the storage nodes CAP/SN); and
a plate node (PL) over the dielectric layer (Fig. 2, Where the plate node PL appears to be over the dielectric layer DL).
Regarding claim 3, Kwak discloses the semiconductor device of claim 2, wherein the plate node is oriented vertically in the direction perpendicular or substantially perpendicular to the surface of the lower structure (Fig. 2, where plate node PL, appears to be oriented in the vertical direction [D1 in reference] which is perpendicular to the lower structure LS).
Regarding claim 4, Kwak discloses the semiconductor device of claim 1, wherein the horizontal conductive layers include a semiconductor material, a doped semiconductor material, an oxide semiconductor material, or a metal-based material (Para. 34, where the horizontal conductive layers ACT can be at least “oxide semiconductor material”).
Regarding claim 5, Kwak discloses the semiconductor device of claim 1, wherein the horizontal conductive layers include a doped silicon material that is doped with an N-type impurity (Para. 34, “The first source/drain region SD1 and the second source/drain region SD2 may be doped with an N-type impurity or a P-type impurity”, Where the SD1 and SD2 regions are part of the horizontal conductive layers).
Regarding claim 6, Kwak discloses the semiconductor device of claim 1, wherein the horizontal conductive layers include a metal material (Para. 34, where the electrodes from the horizontal conductive layers may be doped with indium).
Regarding claim 8, Kwak discloses the semiconductor device of claim 1, and further comprising:
first contact nodes (SD1) disposed between the horizontal conductive layers and the electrode portions of the vertical conductive line (Fig. 4); and
second contact nodes (SD2) disposed between the horizontal conductive layers and the reservoir capacitors (Fig. 4).
Regarding claim 9, Kwak discloses the semiconductor device of claim 8, and further wherein the first contact nodes and the second contact nodes include polysilicon doped with an N-type impurity (Para. 34).
Regarding claim 10, Kwak discloses the semiconductor device of claim 1, wherein the vertical conductive line includes
a pillar portion oriented perpendicularly in a direction perpendicular or substantially perpendicular to the surface of the lower structure (The majority of the vertical conductive line is vertical, except the extension portions);
extension portions (GD) extending horizontally from the pillar portion (Figs 2 and 3, where the extension portions GD could be considered part of the vertical conductive line and extend horizontally from the pillar); and
cylindrical electrode portions covering at least a portion of each of the extension portions (Seeing as how the electrode portions SD1/SD2 are against and matching the reservoir capacitor which is also cylindrical)
Regarding claim 11, Kwak discloses the semiconductor device of claim 10, wherein the cylindrical electrode portions are arranged to be bilaterally symmetrical based on the pillar portion (Figs. 2 and 3).
Regarding claim 12, Kwak discloses the semiconductor device of claim 1, and further wherein the lower structure includes a control circuit for controlling the reservoir capacitors (Para. 25, “The substrate LS may include a peripheral circuit region (not shown). For example, the peripheral circuit region may include a plurality of control circuits for controlling the memory cell array MCA”).
Regarding claim 13, Kwak discloses the semiconductor device of claim 1, further comprising:
a memory cell array (MCA) disposed over the lower structure and disposed horizontally from the reservoir capacitors (Figs. 3 and 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable as obvious by Kwak in view of United States Patent Application Publication by Gomes et al. (US 20220375916 A1; Gomez).
Regarding claim 7, Kwak fails to disclose wherein the wherein the horizontal conductive layers include tungsten.
In [0038], however, Gomes discloses a Nanoribbon 304 which can be seen as the horizontal channel layer, that can be made to include tungsten.
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known horizontal channel layer material such as Tungsten, as shown by Gomes [0038], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose Tungsten over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
United States Patent Application Publication by Kim (US 20220122977 A1)
United States Patent Application Publication by Lee et al. (US 20190164985 A1; Lee)
United States Patent Application Publication by Choi et al. (US 20220068859 A1; Choi)
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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