DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 15, and 20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,9-16, and 20 of copending Application No. 18/669876 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claims 1, 15, and 20, Appl. ’876 [Claims 1,9-16,20] discloses the limitations of the claims.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7, 10-15, and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. (U.U. Pub. 2022/0392941) [Hereafter “Kwon”].
Regarding claim 1, Kwon [Figs.2,7-12] discloses an image sensor, comprising:
a first semiconductor chip [110] including
a first semiconductor substrate [111] having a pixel unit [PX] in which a plurality of pixels are arranged,
a first wiring structure [115] on the first semiconductor substrate and having a first wiring layer [112], and
a first bonding pad [116] exposed to one surface of the first wiring structure and connected to the first wiring layer;
a second semiconductor chip [120] including
a second semiconductor substrate [121] having a first surface on which at least a portion of a plurality of transistors of a pixel signal generator circuit [128] are located and a second surface opposite to the first surface,
a second wiring structure [125] on the first surface of the second semiconductor substrate, the second wiring structure having one surface in contact with the one surface of the first wiring structure, the second wiring structure having a second wiring layer [122,123],
a second upper bonding pad [126] exposed to the one surface of the second wiring structure and bonded to the first bonding pad [116], and
a via structure [127,227] connected to the second wiring layer [123] and extending to the second surface of the second semiconductor substrate [Figs.2,9-10];
a bonding layer including
a bonding insulating layer [270] on the second surface of the second semiconductor substrate, and
a second lower bonding pad [227a’’] buried in the bonding insulating layer and exposed to one surface of the bonding insulating layer, the second lower bonding pad connected to the via structure [227a’] [Figs.9-10]; and
a third semiconductor chip [130] including
a third semiconductor substrate [131] having one surface on which logic devices [138] are located,
a third wiring structure [135] on the one surface of the third semiconductor substrate, the third wiring structure having a third wiring layer [132], the third wiring structure having one surface in contact with the one surface of the bonding insulating layer [270], and
a third bonding pad [136,236] connected to the third wiring layer [132] and exposed to the one surface of the third wiring structure, the third bonding pad bonded to the second lower bonding pad [227a’’].
Regarding claims 2-4, Kwon [Figs.2,7-12] discloses an image sensor
wherein the second semiconductor substrate has a thickness of 2 µm to 5 µm [Para.98];
wherein the via structure [227a] includes a via plug [227a’] connecting the second wiring layer [223], to the second lower bonding pad [227a’’], and an insulating liner [271] [Para.101] surrounding a side surface of the via plug;
wherein the via plug includes tungsten (W) or copper (Cu) [Para.51].
Regarding claims 6-7, Kwon [Figs.2,7-12] discloses an image sensor
wherein the second semiconductor substrate [221] has one or more inner surfaces defining a recessed portion [Figs.9-10] on the second surface, and the via structure [227a] penetrates the second semiconductor substrate at the recessed portion, and
wherein the bonding insulating layer [270] is on the second surface of the second semiconductor substrate and extends to a surface of the recessed portion [Figs.9-10];
wherein the second lower bonding pad [227a’’] is in the recessed portion and has a surface substantially coplanar with the one surface of the bonding insulating layer [270].
Regarding claims 10-14, Kwon [Figs.2,7-12] discloses an image sensor
wherein the first wiring structure [115] includes a first bonding insulating film [180]in which the first bonding pad [116] is buried and having one surface substantially coplanar with an exposed region of the first bonding pad,
wherein the second wiring structure [125] includes a second bonding insulating film [180] in which the second upper bonding pad [126] is buried and has one surface substantially coplanar with an exposed region of the second upper bonding pad, and
wherein the one surface of the first bonding insulating film is bonded to the one surface of the second bonding insulating film [Figs.2,8];
wherein an exposed region of the second lower bonding pad [227a’’] has a surface substantially coplanar with the one surface of the bonding insulating layer [270],
wherein the third wiring structure [235] includes a third bonding insulating film [280] in which the third bonding pad [236] is buried and having one surface substantially coplanar with an exposed region of the third bonding pad, and
wherein the one surface of the bonding insulating layer is bonded to the one surface of the third bonding insulating film [Figs.2,9-10];
wherein the second semiconductor chip [120] includes a capacitor structure [129] in the second wiring structure [125] and connected to the first wiring layer;
wherein a transfer transistor of the pixel signal generator circuit is on the first semiconductor substrate [Paras.28,39], and
wherein the portion of the plurality of transistors of the pixel signal generator circuit that are on the second semiconductor substrate include transistors other than the transfer transistor among the plurality of transistors of the pixel signal generator circuit [Para.28];
wherein a separate portion of the plurality of transistors of the pixel signal generator circuit includes a transfer transistor, a reset transistor, and a driver transistor, which are on the first semiconductor substrate [Para.28].
Regarding claim 15, Kwon [Figs.2,7-12] discloses an image sensor, comprising:
a first semiconductor chip [Discussed above in the treatment of claim 1] including
a first semiconductor substrate having a first region [200a] in which a plurality of pixels are arranged and a second region [200b-d] around the first region,
a first wiring structure on a lower surface of the first semiconductor substrate and having a first wiring layer, and
a first bonding pad exposed to the lower surface of the first wiring structure and connected to the first wiring layer;
a second semiconductor chip [Discussed above in the treatment of claim 1] including
a second semiconductor substrate having an upper surface on which transistors of a pixel signal generator circuit are located and a lower surface having a recessed portion [via structure region 227] in a region overlapping the second region,
a second wiring structure on the upper surface of the second semiconductor substrate, the second wiring structure in contact with the first wiring structure, the second wiring structure having a second wiring layer,
a second upper bonding pad exposed to an upper surface of the second wiring structure and bonded to the first bonding pad, and
a via structure connected to the second wiring layer and penetrating through the recessed portion of the second semiconductor substrate;
a bonding layer [Discussed above in the treatment of claim 1] including
a bonding insulating layer on the lower surface of the second semiconductor substrate and extending to the recessed portion, and
a second lower bonding pad buried in the bonding insulating layer, the second lower bonding pad exposed to a lower surface of the bonding insulating layer, the second lower bonding pad connected to the via structure in the recessed portion; and
a third semiconductor chip [Discussed above in the treatment of claim 1] including
a third semiconductor substrate having an upper surface on which logic devices are located,
a third wiring structure on the upper surface of the third semiconductor substrate, the third wiring structure in contact with the bonding insulating layer, the third wiring structure having a third wiring layer, and
a third bonding pad exposed to an upper surface of the third wiring structure, the third bonding pad bonded to the second lower bonding pad, the third bonding pad connected to the third wiring layer [Discussed above in the treatment of claim 1].
Regarding claims 18-19, Kwon [Figs.2,7-12] discloses an image sensor
wherein the second lower bonding pad has a surface substantially planar with a lower surface of the bonding insulating layer,
wherein the third wiring structure includes a bonding insulating film in which the third bonding pad is buried and having an upper surface substantially coplanar with an exposed region of the third bonding pad, and
wherein the lower surface of the bonding insulating layer is bonded to the upper surface of the bonding insulating film [Figs.2,9-10];
wherein the first bonding pad and the second upper bonding pad are arranged in regions overlapping the first region and the second region of the first semiconductor substrate, and
wherein the third bonding pad and the second lower bonding pad are arranged in regions overlapping the second region of the first semiconductor substrate [Figs.7-10].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 8-9, 16-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (U.U. Pub. 2022/0392941) in view of Fuji et al. (U.S. Pub. 2020/0020733) [Hereafter “Fuji”].
Regarding claim 20, Kwon [Figs.2,7-12] discloses an image sensor, comprising:
a first semiconductor chip [110] [Discussed above] including
a first semiconductor substrate having a first region [200a] in which a plurality of pixels are arranged and a second region [200b-d] around the first region,
a first wiring structure on a lower surface of the first semiconductor substrate and having a first wiring layer, and
a first bonding pad exposed to a lower surface of the first wiring structure and connected to the first wiring layer;
a second semiconductor chip [120] [Discussed above] including
a second semiconductor substrate having an upper surface on which transistors of a pixel signal generator circuit are located,
a second wiring structure [125] on the upper surface of the second semiconductor substrate, the second wiring structure in contact with the first wiring structure [122], the second wiring structure having a second wiring layer [123],
a second upper bonding pad exposed to an upper surface of the second wiring structure and bonded to the first bonding pad, and
a via structure [227] connected to the second wiring layer, the via structure penetrating through a region of the second semiconductor substrate overlapping the second region of the first semiconductor substrate, the via structure having a protruding portion protruding from a lower surface of the second semiconductor substrate [221];
a bonding layer including
a bonding insulating layer [270], and
a second lower bonding pad buried in the bonding insulating layer, the second lower bonding pad exposed to a lower surface of the bonding insulating layer, the second lower bonding pad connected to the via structure; and
a third semiconductor chip [130 [Discussed above] including
a third semiconductor substrate having an upper surface on which logic devices are located,
a third wiring structure on the upper surface of the third semiconductor substrate, the third wiring structure in contact with the bonding insulating layer, the third wiring structure having a third wiring layer, and
a third bonding pad exposed to an upper surface of the third wiring structure, the third bonding pad bonded to the second lower bonding pad, the third bonding pad connected to the third wiring layer.
Kwon fails to explicitly disclose
an etching stop layer on the lower surface of the second semiconductor substrate and surrounding an exposed portion of the via structure,
a bonding insulating layer on the etching stop layer, and
a second lower bonding pad buried in the bonding insulating layer, the second lower bonding pad exposed to a lower surface of the bonding insulating layer, the second lower bonding pad connected to the via structure.
However, Fuji [Figs.1,9D] discloses an image sensor comprising
an etching stop layer [251] [Para.139] on a lower surface of the second semiconductor substrate [121] and surrounding an exposed portion of the via structure [203,204],
a bonding insulating layer [123] on the etching stop layer, and
a second lower bonding pad [181] buried in the bonding insulating layer, the second lower bonding pad exposed to a lower surface of the bonding insulating layer, the second lower bonding pad connected to the via structure.
It would have been obvious to provide the etching stop layer as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 5, Kwon fails to explicitly disclose the limitations of the claims. However, Fuji [Figs.1,9D] discloses
wherein the via structure [204] has a width decreasing from the second wiring layer toward the second lower bonding pad [181].
It would have been obvious to provide a tapered via as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 8-9, Kwon fails to explicitly disclose the limitations of the claims. However, Fuji [Figs.1,9D] discloses
wherein the second surface of the second semiconductor substrate has a planar surface, and the via structure penetrates through the second semiconductor substrate and has a protruding portion protruding from the second surface of the second semiconductor substrate, and
wherein the bonding layer further includes an etching stop layer between the second semiconductor substrate and the bonding insulating layer and surrounding the protruding portion of the via structure [Discussed above in the treatment of claim 20];
wherein the second lower bonding pad is connected to the protruding portion of the via structure on the etching stop layer and has a surface substantially coplanar with the one surface of the bonding insulating layer [Discussed above in the treatment of claim 20].
It would have been obvious to provide the etching stop layer as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 16-17, Kwon fails to explicitly disclose the limitations of the claims. However, Fuji [Figs.1,9D] discloses
wherein the via structure includes a via plug [204] connecting the second wiring layer to the second lower bonding pad [181], and an insulating liner [251-253] surrounding a side surface of the via plug, and
wherein the via plug has a width decreasing from the second wiring layer toward the second lower bonding pad [Fig.9D];
wherein the via plug and the second lower bonding pad include different metals [Para.86 discloses wiring may comprise copper and pads may comprise aluminum].
It would have been obvious to provide the tapered via shape, the insulating liner, and the different metal material as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention.
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/BAC H AU/Primary Examiner, Art Unit 2898