DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the gate electrode comprising the graphene layer and the metal layer, as recited in Claim 6, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6 and 9 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “the gate electrode comprises the graphene layer and the metal layer, and in the gate electrode, the graphene layer and the metal layer are arranged in parallel in the vertical direction with respect to the surface of the substrate.” The Examiner is uncertain whether the limitation is intended to mean that the same graphene layer and metal layer comprise the gate electrode as comprise the source electrode and the drain electrode, which is the antecedent basis from claim 1, for the following reasons:
(1) The Examine finds no Drawing which includes the limitation (or at least, no Drawing from which it is clear to the Examiner how the limitation may be implemented, there being an intervening layer between the gate electrode and the source and drain electrodes in in views shown).
(2) The specification does not clarify the uncertainty: Paragraph [0013] recites “the gate electrode may include the graphene layer and the metal layer. In the gate electrode, the graphene layer and the metal layer may be arranged in parallel in the vertical direction with respect to the surface of the substrate.” The only other mention of the gate electrode comprising a graphene layer and a metal layer that the Examiner finds is in paragraph [0068], which indicates that an embodiment is not shown wherein “the gate electrode 80 may include a graphene layer 40 and a metal layer 50”, the wording of which does not include the antecedent requirement that a graphene layer and metal layer be the same layers in each of the gate electrode, source and drain electrodes. It is unclear whether the two paragraphs [0013] and [0068] refer to the same embodiment, the former referring to the graphene layer and the metal layer, and the latter referring to a graphene layer and a metal layer.
For these reasons, the scope of the claim is indefinite, and the claim has not been Examined for prior art.
Claim 9 recites “wherein the metal layer comprises at least one of Rd and Pd”; however, Rd is not a known symbol for an element, and no unabbreviated form has been provided in the disclosure. Because of this, the scope of the claim in indefinite. The Examiner expects that Rhodium (Rh) or Ruthenium (Ru) was most likely intended. For the purposes of examination, “Rd” will be interpreted as Rhodium (Rh).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin; Shih-Yen et al. (US 2023/0088634; hereinafter Lin).
Regarding claim 1, Lin discloses a transistor structure comprising (reference, in particular, Fig 15; entire document):
a substrate (100; Fig 15; ¶ [0024-25]);
a source electrode and a drain electrode (135 and 110,120 to the left and right respectively (110 SD region) of 110CH; Fig 15; ¶ [0037,0042]) spaced apart from each other on the substrate;
a channel layer (110CH region of 2D materials 110 and 120; Fig 15; ¶ [0026-45]) connected to the source electrode and the drain electrode;
a gate insulating layer (140; Fig 15; ¶ [0075]) on the channel layer; and
a gate electrode (150; Fig 15; ¶ [0075]) on the gate insulating layer,
wherein
the channel layer includes a two-dimensional semiconductor material (¶ [0037]), the source electrode and the drain electrode each include a graphene layer (110; ¶ [0031]) and a metal layer (metal layer 130 is patterned into 135; ¶ [0041-42]),
the graphene layer is formed by as-growing on the substrate (formed by epitaxial graphene growth; ¶ [0031]), and
the graphene layer and the metal layer are side by side in a vertical direction with respect to a surface of the substrate (135 is above 110; that is, side by side in vertical direction starting from the surface of substrate 100).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Seol; Minsu et al. (US 2021/0305378; hereinafter Seol) in view of Lin; Shih-Yen et al. (US 2023/0088634; hereinafter Lin).
Regarding claim 1, Seol discloses a transistor structure comprising (in particular, Fig 5; entire document):
a substrate (100; Fig 5; ¶ [0040-41,0044-45]);
a source electrode and a drain electrode (120,150 and 130,160 respectively; Fig 5; ¶ [0040-41,0044-45]) spaced apart from each other on the substrate;
a channel layer (110; Fig 5; ¶ [0040-41,0044-45]) connected to the source electrode and the drain electrode;
a gate insulating layer on the channel layer (140; Fig 5; ¶ [0040-41,0044-45]); and
a gate electrode (170; Fig 5; ¶ [0040-41,0044-45]) on the gate insulating layer,
wherein
the channel layer includes a two-dimensional semiconductor material (¶ [0041]),
the source electrode and the drain electrode each include a graphene layer (120 and 130 {Fig 5} are metallic 2D material layers {the same 20 of Fig 1; ¶ [0041,0035]}, and the metallic 2D material may be or include graphene {¶ [0035]} ) and a second layer (150,160; Fig 5),
the graphene layer is formed by as-growing on the substrate (120,130 may be formed by being directly grown on the substrate 100; ¶ [0061]), and
the graphene layer and the second layer are side by side in a vertical direction with respect to a surface of the substrate (150 and 160 are directly on 120 and 130 respectively, in a vertical stack; Fig 100).
Seol does not disclose that the second layer is a metal layer.
In the same field of endeavor, Lin discloses a source electrode and a drain electrode (135 and 110,120 to the left and right respectively (110 SD region) of 110CH; Fig 15; ¶ [0037,0042]), wherein the source electrode and the drain electrode each include a graphene layer (110; ¶ [0031]) and a metal layer (metal layer 130 is patterned into 135; ¶ [0041-42]). Accordingly, it would have been obvious to a person having ordinary skill in the art to use a metal layer, such as disclosed by Lin, for the second layer of Seol. One would have been motivated do to this, with a reasonable expectation of success, because a metal layer is commonly used as an electrode in the art, because Seol is silent as to the material of the second layer, and because Lin has disclosed the metal layer in the similar source/drain electrode application in the similar structure.
Regarding claim 2, Seol in view of Lin discloses the transistor structure of claim 1, wherein in at least one of the source electrode and the drain electrode, the graphene layer (Seol; 120,130; Fig 5) and the metal layer (Seol; 150,160; Fig 6) are sequentially stacked on the substrate and the graphene layer is between the substrate and the channel layer (Seol; as applied to claim 1, and shown in Fig 5).
Regarding claim 9, Seol in view of Lin discloses the transistor structure of claim 1, wherein the metal layer comprises at least one of Rhodium (Rd) and Pd. (Lin; layer 130 may be rhodium (Rh); ¶ [0041]).
Regarding claim 10, Seol in view of Lin discloses the transistor structure of claim 1, wherein the channel layer comprises a transition metal dichalcogenide (TMD). (Seol; The first 2D material layer 110 may be the same material as a 2D material used as the wiring 10 {¶ [0041]}, and the wiring 10 is or may include a TMD; ¶ [0035]))
Regarding claim 11, Seol in view of Lin discloses the transistor structure of claim 10, wherein the TMD comprises a metal element and a chalcogen element, the metal element includes at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb (Seol; ¶ [0041), and the chalcogen element includes at least one of S, Se, and Te(Seol; ¶ [0041).
Regarding claim 12, Seol in view of Lin discloses the transistor structure of claim 1, but does not disclose (Seol) the material of the gate electrode. However, Lin discloses a gate electrode which comprises at least one of tungsten (W), molybdenum (Mo), ruthenium (Ru), polysilicon, TiN, or a combination thereof (Lin; 150; Fig. 5; ¶ [0048]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have used one of the materials disclosed by Lin in the transistor structure of claim 1. One would have been motivated to do this because Seol is silent as to the material, because Lin has disclosed the materials as suitable for the similar structure, and because the materials are well-known for use as electrodes, including gate electrodes in the art. One would have had a reasonable expectation of success because of the similar structures of Seol and Lin, and because the materials are well-known in the art.
Regarding claim 13, Seol in view of Lin discloses the transistor structure of claim 12, wherein claim 12 is satisfied by one of the other materials besides a metallic two-dimensional material, and is still satisfied by one of tungsten (W), molybdenum (Mo), ruthenium (Ru), polysilicon, TiN, when the metallic two-dimensional material comprises at least one of graphene, TaS2, TaSe2, NbS2, NbSe2, PdTe2, PtTe2, NbTe2, TiSe2, VSe2, AuSe, and MoTe2.
Regarding claim 14, Seol discloses a semiconductor device (500; Fig 5; ¶ [0044-45, 0040-41]), comprising:
a transistor structure (500; Fig 5; ¶ [0044-45, 0040-41]); and
a plurality of capacitors (Fig 5; comprising at least, gate {170} to substrate {100}, gate to source {120/150} and gate to drain {130/160}, each having insulating layer 140 therebetween) in the transistor structure,
wherein the transistor structure includes:
a substrate (100; Fig 5; ¶ [0040-41,0044-45]);
a source electrode and a drain electrode (120,150 and 130,160 respectively; Fig 5; ¶ [0040-41,0044-45]) spaced apart from each other on the substrate;
a channel layer (110; Fig 5; ¶ [0040-41,0044-45]) connected to the source electrode and the drain electrode;
a gate insulating layer on the channel layer (140; Fig 5; ¶ [0040-41,0044-45]); and
a gate electrode (170; Fig 5; ¶ [0040-41,0044-45]) on the gate insulating layer,
wherein
the channel layer includes a two-dimensional semiconductor material (¶ [0041]),
the source electrode and the drain electrode each include a graphene layer (120 and 130 {Fig 5} are metallic 2D material layers {the same 20 of Fig 1; ¶ [0041,0035]}, and the metallic 2D material may be or include graphene {¶ [0035]} ) and a second layer (150,160; Fig 5),
the graphene layer is formed by as-growing on the substrate (120,130 may be formed by being directly grown on the substrate 100; ¶ [0061]), and
the graphene layer and the second layer are arranged side by side in a vertical direction with respect to a surface of the substrate (150 and 160 are directly on 120 and 130 respectively, in a vertical stack; Fig 100).
Seol does not disclose that the second layer is a metal layer.
In the same field of endeavor, Lin discloses a source electrode and a drain electrode (135 and 110,120 to the left and right respectively (110 SD region) of 110CH; Fig 15; ¶ [0037,0042]), wherein the source electrode and the drain electrode each include a graphene layer (110; ¶ [0031]) and a metal layer (metal layer 130 is patterned into 135; ¶ [0041-42]). Accordingly, it would have been obvious to a person having ordinary skill in the art to use a metal layer, such as disclosed by Lin, for the second layer of Seol. One would have been motivated do to this, with a reasonable expectation of success, because a metal layer is commonly used as an electrode in the art, because Seol is silent as to the material of the second layer, and because Lin has disclosed the metal layer in the similar source/drain electrode application in the similar structure.
Regarding claim 15, Seol in view of Lin discloses the transistor structure of claim 14, wherein the graphene layer (Seol; 120,130; Fig 5) is between the substrate (Seol; 100; Fig 5) and the metal layer (Seol; 150,160; Fig 5; as applied to claim 14).
Claims 3 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Seol; Minsu et al. (US 2021/0305378; hereinafter Seol) in view of Lin (Lin; Shih-Yen et al. (US 2023/0088634; hereinafter Lin), and further in view of Shin; Hyeonjin et al. (US 2021/0355582; hereinafter Shin) and Zou; Yuan et al. (US 9159938; hereinafter Zou).
Regarding claim 3, Seol in view of Lin discloses the transistor structure of claim 1, but does not disclose wherein a thickness of the source electrode and a thickness of the drain electrode are less than about 5 nm.
However, as applied to claim 1, the source electrode and drain electrode comprise the 2D material layers 120 and 130, which may be a monolayer (Seol; Fig 5; ¶ [0041]; {Lin; mono-layer; ¶ [0026]}), and a metal layer (Lin, 135, as applied to claim 1). As is known in the art, a monolayer of graphene may have a thickness of only a few angstroms (see Shin; ¶ [0041]). The metal layer may also be a very thin layer. For example, in the same field of endeavor, Zhou discloses a transistor structure wherein a metal source electrode and drain electrode have a thickness as low as 0.5 nm, and in an exemplary embodiment the thickness is about 5 nm (Col 4, lines 16-35). Accordingly, it would have been obvious to a person having ordinary skill in the art to form the transistor structure of claim 1 having the thickness of the source electrode and the thickness of the drain electrode less than about 5 nm. One may be motivated to do this in order to make the overall thickness of the transistor structure very thin, in accordance with on-going industry miniaturization (Lin; devices with ultra-thin bodies; ¶ [0026]). One would have had a reasonable expectation of success because of the similar disclosed thickness ranges for 2D materials, and for source/drain electrodes as disclosed by Zhou, which overlap the claimed range and therefore constitute a prima facie case of obviousness. See MPEP 2144.05.I.
Regarding claim 16, Seol in view of Lin discloses the semiconductor device of claim 14, but does not disclose wherein a thickness of the source electrode and a thickness of the drain electrode are less than about 5 nm.
However, as applied to claim 14, the source electrode and drain electrode comprise the 2D material layers 120 and 130, which may be a monolayer (Seol; Fig 5; ¶ [0041]; {Lin; mono-layer; ¶ [0026]}), and a metal layer (Lin, 135, as applied to claim 1). As is known in the art, a monolayer of graphene may have a thickness of only a few angstroms (see Shin; ¶ [0041]). The metal layer may also be a very thin layer. For example, in the same field of endeavor, Zhou discloses a transistor structure wherein a metal source electrode and drain electrode have a thickness as low as 0.5 nm, and in an exemplary embodiment the thickness is about 5 nm (Col 4, lines 16-35). Accordingly, it would have been obvious to a person having ordinary skill in the art to form the transistor structure of claim 1 having the thickness of the source electrode and the thickness of the drain electrode less than about 5 nm. One may be motivated to do this in order to make the overall thickness of the transistor structure very thin, in accordance with on-going industry miniaturization (Lin; devices with ultra-thin bodies; ¶ [0026]). One would have had a reasonable expectation of success because of the similar disclosed thickness ranges for 2D materials, and for source/drain electrodes as disclosed by Zhou, which overlap the claimed range and therefore constitute a prima facie case of obviousness. See MPEP 2144.05.I.
Claims 4-5 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Seol; Minsu et al. (US 2021/0305378; hereinafter Seol) in view of Lin (Lin; Shih-Yen et al. (US 2023/0088634; hereinafter Lin), and further in view of Woo; Yun-sung et al. (US 2009/0294759; hereinafter Woo).
Regarding claim 4, Seol in view of Lin discloses the transistor structure of claim 1, but does not disclose wherein at least one of the source electrode and the drain electrode include a nitride layer on one surface of the graphene layer between the one surface of the graphene layer and the surface of the substrate.
In the same field of endeavor Woo discloses a transistor structure (for example Fig 6A; ¶ [0058]) comprising source and drain electrodes (S1 and D1; Figs 6A,6B; ¶ [0058-59]) comprising a graphene layer (GP1; Fig 6A; ¶ [0058-59, 0044-49]) and a nitride layer (UL3 {Fig 6A; ¶ [0046-49]}, comprising hexagonal boron nitride {h-BN; ¶ [0046-47]}) on one surface of the graphene layer between the one surface of the graphene layer and the surface of a substrate (SUB1; Fig 6A; ¶ [0058]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have included a nitride layer according to claim 4 in the transistor structure of Seol in view of Lin. One may have been motivated to do this in order to facilitate lattice matching of the graphene layer to a particular substrate material (Woo; ¶ [0006,0047-49]). One would have had a reasonable expectation of success because of the similar graphene material used in the similar structures of Woo and Seol.
Regarding claim 5, Seol in view of Lin and further in view of Wee discloses the transistor structure of claim 4, wherein the nitride layer comprises boron nitride (h-BN) (as applied to claim 4).
Regarding claim 17, Seol in view of Lin discloses the semiconductor device of claim 14, but does not disclose wherein at least one of the source electrode and the drain electrode include a nitride layer on one surface of the graphene layer between the one surface of the graphene layer and the surface of the substrate.
In the same field of endeavor Woo discloses a transistor structure (for example Fig 6A; ¶ [0058]) comprising source and drain electrodes (S1 and D1; Figs 6A,6B; ¶ [0058-59]) comprising a graphene layer (GP1; Fig 6A; ¶ [0058-59, 0044-49]) and a nitride layer (UL3 {Fig 6A; ¶ [0046-49]}, comprising hexagonal boron nitride {h-BN; ¶ [0046-47]}) on one surface of the graphene layer between the one surface of the graphene layer and the surface of a substrate (SUB1; Fig 6A; ¶ [0058]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have included a nitride layer according to claim 17 in the transistor structure of Seol in view of Lin. One may have been motivated to do this in order to facilitate lattice matching of the graphene layer to a particular substrate material (Woo; ¶ [0006,0047-49]). One would have had a reasonable expectation of success because of the similar graphene material used in the similar structures of Woo and Seol.
Regarding claim 18, Seol in view of Lin and further in view of Wee discloses the semiconductor device of claim 17, wherein the nitride layer comprises boron nitride (h-BN) (as applied to claim 17).
Claims 7-8 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Seol; Minsu et al. (US 2021/0305378; hereinafter Seol) in view of Lin (Lin; Shih-Yen et al. (US 2023/0088634; hereinafter Lin), and further in view of Heo; Jinseong et al. (US 2016/0343891; hereinafter Heo).
Regarding claim 7, Seol in view of Lin discloses the transistor structure of claim 1, but does not disclose wherein in the source electrode and the drain electrode, an inside of the graphene layer is doped with at least one of N, S, B, P, O, and F.
In the same field of endeavor, Heo discloses a transistor structure (in particular, Fig 27,29A-29F; entire document) comprising doped graphene source and drain electrodes (E50 and E60 {may be the same as E10 and E20}; Fig 27; ¶ [0169-170,{doping: 0112-113}]), which may be doped with, for example, N (by replacing some carbon (C) in the graphene with nitrogen (N); ¶ [0113,0185]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have including doping similar to Heo in the transistor structure of claim 1. One would have been motivated to do this in order to control the work function of the graphene layer (Heo; ¶ [0104]) for the transistor structure to function as intended. One would have had a reasonable expectation of success because such doping is well-known in the art, and because of the similar transistor structures and materials of Seol and Heo. The Examiner interprets the disclosure of Heo (“replacing some carbon (C) in the graphene with nitrogen (N)”) to mean an inside of the graphene layer is doped; further, a clear definition or means to quantify “an inside” are not found in Applicant’s disclosure.)
Regarding claim 8, Seol in view of Lin discloses the transistor structure of claim 1, but does not disclose wherein the surface of the graphene layer is doped with a dopant, and the dopant includes at least one of Pd, Ti, W, Al, Ni, Cu, Ru, Ag, Au, and Pt.
In the same field of endeavor, Heo discloses a transistor structure (in particular, Fig 27,29A-29F; entire document) comprising doped source and drain electrodes (E50 and E60 {may be the same as E10 and E20}; Fig 27; ¶ [0169,{doped: 0112-113}]), which may be doped with, for example, Au (Au in AuCl.sub.3 may serve as a p-type dopant; ¶ [0113,0181]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have including doping similar to Heo in the transistor structure of claim 1. One would have been motivated to do this in order to control the work function of the graphene layer (Heo; ¶ [0104]) for the transistor structure to function as intended. One would have had a reasonable expectation of success because such doping is well-known in the art, and because of the similar transistor structures and materials of Seol and Heo. The Examiner interprets that the surface of the graphene layer is doped with a dopant because, as shown in Figs 289A-29B {¶ [0179-180), the doping is accomplished after formation of the graphene layer, and therefore must occur through the surface of the graphene layer.)
Regarding claim 19, Seol in view of Lin discloses the semiconductor device of claim 14, but does not disclose wherein the graphene layer is doped inside with a dopant , and the dopant includes at least one of N, S, B, P, O, and F.
In the same field of endeavor, Heo discloses a transistor structure (in particular, Fig 27,29A-29F; entire document) comprising doped graphene source and drain electrodes (E50 and E60 {may be the same as E10 and E20}; Fig 27; ¶ [0169-170,{dopant: 0112-113}]), which may be doped with, for example, N (by replacing some carbon (C) in the graphene with nitrogen (N); ¶ [0113,0185]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have including doping similar to Heo in the transistor structure of claim 14. One would have been motivated to do this in order to control the work function of the graphene layer (Heo; ¶ [0104]) for the transistor structure to function as intended. One would have had a reasonable expectation of success because such doping is well-known in the art, and because of the similar transistor structures and materials of Seol and Heo. The Examiner interprets the disclosure of Heo (“replacing some carbon (C) in the graphene with nitrogen (N)”) to mean the graphene layer is doped inside; further, a clear definition or means to quantify “inside” are not found in Applicant’s disclosure.)
Regarding claim 20, Seol in view of Lin discloses the semiconductor device of claim 14, but does not disclose wherein the surface of the graphene layer is doped with a dopant, and the dopant includes at least one of Pd, Ti, W, Al, Ni, Cu, Ru, Ag, Au, and Pt.
In the same field of endeavor, Heo discloses a transistor structure (in particular, Fig 27,29A-29F; entire document) comprising doped source and drain electrodes (E50 and E60 {may be the same as E10 and E20}; Fig 27; ¶ [0169,{doped: 0112-113}]), which may be doped with, for example, Au (Au in AuCl.sub.3 may serve as a p-type dopant; ¶ [0113,0181]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have including doping similar to Heo in the transistor structure of claim 1. One would have been motivated to do this in order to control the work function of the graphene layer (Heo; ¶ [0104]) for the transistor structure to function as intended. One would have had a reasonable expectation of success because such doping is well-known in the art, and because of the similar transistor structures and materials of Seol and Heo. The Examiner interprets that the surface of the graphene layer is doped with a dopant because, as shown in Figs 289A-29B {¶ [0179-180), the doping is accomplished after formation of the graphene layer, and therefore must occur through the surface of the graphene layer.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Zhang; Dacheng et al. (US 2017/0294516; the prior art discloses a transistor having source, drain, and gate electrodes composed of graphene).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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