DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species A and 2 in the reply filed on 7/7/2026 is acknowledged. Claims 1-20 are examined on the merits.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. It is suggested that the title include the phrase “including heat dissipation members.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5, 7-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. US 20180269126 A1 to Im et al. (hereinafter “Im”).
Regarding claim 1, Im teaches a high bandwidth memory comprising:
a buffer die (substrate 110; fig. 7D) [0095];
a memory (semiconductor chip 120 which may comprise a memory structure; fig. 7D) [0095] disposed on the buffer die (110);
one or more heat dissipation structures (140; fig. 7D) [0097] disposed on the buffer die (110), and horizontally adjacent (horizontally adjacent in fig. 7D) to the memory (120); and
a molding material (130; fig. 7D) [0096] disposed on the buffer die (110) so as to encapsulate (be disposed on both horizontal sides) the memory (120) and the one or more heat dissipation structures (140).
Im, in fig. 7D, does not teach that the memory is a stack or that the memory stack includes a stack of a plurality of memory dies.
Im, however, in fig. 19E, teaches a memory stack (of chips 120 and 220) including a stack of a plurality of memory dies (chips 120 and 220 which comprise memory structures; fig. 19E [0095] & [0143].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the structure of fig. 7D to comprise a memory stack including a stack of a plurality of memory dies to increase circuit density as taught by Im [0143].
The term “memory stack” is changed above is certain instances to improve clarity in the context of claim 1. In the interest of clarify for the claims which depend from claim 1, the term “memory stack” is unchanged, and it is noted that the memory of Im fig. 7D is modified to comprise a memory stack.
Regarding claim 5, Im teaches the high bandwidth memory of claim 1, wherein: the one or more heat dissipation structures each include heat slug. It is noted that the as-filed specification informs the public at least at ¶ [0065] that the heat slugs may also be referred to as a heat sink.
To further clarify, Im teaches a heat sink as the heat dissipation structures because they comprise conductive material and they dissipate heat to the surrounding area. Because the heat dissipation structure of Im does comprise further material disposed in physical contact with it from above, the heat dissipation structure fits this definition.
The above definition is evidenced by The optimal design of heat sinks: A review to Ali et al. (sec. 2; p. 1031).
Regarding claim 7, Im teaches the high bandwidth memory of claim 1, wherein: the one or more heat dissipation structures (140) are horizontally adjacent (horizontally flank) to respective side surfaces of the memory stack (120).
Regarding claim 8, Im teaches the high bandwidth memory of claim 7, wherein: the one or more heat dissipation structures (140) are horizontally spaced apart from the memory stack (120).
Regarding claim 9, Im teaches the high bandwidth memory of claim 1, wherein: the one or more heat dissipation structures (140) surround (are disposed flanking) one or more side surfaces of the memory stack (120).
Regarding claim 10, Im teaches the high bandwidth memory of claim 1, wherein: upper surfaces of the one or more heat dissipation structures (140) are exposed to the outside (are not covered) of the high bandwidth memory.
Regarding claim 11, Im teaches the high bandwidth memory of claim 1, further comprising: an additional heat dissipation structure (portion of 140 directly above 120) disposed on top of the memory stack (120).
Regarding claim 12, Im teaches the high bandwidth memory of claim 11, wherein: an upper surface of the additional heat dissipation structure (portion of 140 directly above 120) is exposed to the outside (not covered) of the high bandwidth memory.
Regarding clam 13, Im teaches the high bandwidth memory of claim 1, further comprising: an interconnection structure (inner terminals 122; fig. 7D) [0095] between the buffer die (110) and the memory stack (120).
Regarding claim 15, Im teaches the high bandwidth memory of claim 1, wherein: a first portion (portion closer to 120) of the molding material (130) is horizontally between the memory stack (120) and the one or more heat dissipation structures (140); and a second portion (portion further away from 120) of the molding material (130) is horizontally outside the one or more heat dissipation structures (140) to surround (be disposed laterally flanking) the one or more heat dissipation structures (140).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Im as applied to claim 1 above, and further in view of Fabrication of lightweight and flexible silicon rubber foams with ultra-efficient electromagnetic interference shielding and adjustable low reflectivity to Yang et al. (hereinafter “Yang”).
Regarding claim 2, Im does not teach the high bandwidth memory of claim 1, wherein: the one or more heat dissipation structures each include dummy dies. It is noted that Im teaches that the heat dissipation structures of fig. 7D further assist in electro-magnetic interference (EMI) mitigation [0131].
Yang, however, teaches the use of dummy die material (silicon; abstract) in a heat dissipation structure for communication devices (abstract; conclusion).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the heat dissipation structure of Im to include dummy dies to make the package more lightweight and flexible as taught by Yang in the abstract.
Regarding claim 3, Im in view of Yang teaches the high bandwidth memory of claim 2, wherein: the dummy dies (material of heat dissipation structure, as modified by Yang) include crystalline silicon (see Yang fig. 4 wherein is shown a crystalline material).
Regarding claim 4, Im in view of Yang, at least in the embodiment of Im fig. 7D, does not teach the high bandwidth memory of claim 3, further comprising: bonding members between the buffer die and the dummy dies.
However, Im, in the embodiment of fig. 1G, teaches bonding members (first heat dissipation layer 141; fig. 1G) between the buffer die (110) and the dummy dies (143; fig. 1G).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the structure of Im in view of Yang to comprise bonding members between the buffer die and the dummy dies, to increase adhesive strength as taught by Im [0105].
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Im in view of U.S. Pat. Pub. No. US 20220013475 A1, which is of record, to Kim et al. (hereinafter “Kim”).
Regarding claim 16, Im teaches a semiconductor package comprising:
a high bandwidth memory (structure of fig. 7D) [0131], wherein:
the high bandwidth memory (structure of fig. 7D) includes:
a buffer die (substrate 110; fig. 7D) [0095];
a memory (semiconductor chip 120 which may comprise a memory structure; fig. 7D) [0095] disposed on the buffer die (110);
one or more heat dissipation structures (140; fig. 7D) [0097] disposed on the buffer die (110), and horizontally adjacent (horizontally adjacent in fig. 7D) to the memory (120); and
a molding material (130; fig. 7D) [0096] disposed on the buffer die (110) and encapsulating (be disposed on both horizontal sides) the memory (120) and the one or more heat dissipation structures (140).
Im, in fig. 7D, does not teach that the memory is a stack or that the memory stack includes a stack of a plurality of memory dies.
Im, however, in fig. 19E, teaches a memory stack (of chips 120 and 220) including a stack of a plurality of memory dies (chips 120 and 220 which comprise memory structures; fig. 19E) [0095] & [0143].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the structure of fig. 7D to comprise a memory stack including a stack of a plurality of memory dies to increase circuit density as taught by Im [0143].
Im further does not teach an interposer, a logic die on the interposer, or a plurality of high bandwidth memories on the interposer.
Kim, however, teaches a semiconductor package (fig. 13) including: an interposer (substrate 110; fig. 13) [0024], a logic die (semiconductor chip structure 120a; fig. 13) [0051] on the interposer (110), and a plurality of high bandwidth memories (120b; fig. 13) [0051] on the interposer (110).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the package of Im to: comprise a plurality of high bandwidth memories to increase memory of the package as taught by Kim [0051]; and comprise an interposer with a logic die on the interposer to create a package with processing power and memory as taught by Kim [0051].
The term “memory stack” is changed above is certain instances to improve clarity in the context of claim 16. In the interest of clarify for the claims which depend from claim 16, the term “memory stack” is unchanged, and it is noted that the memory of Im fig. 7D is modified to comprise a memory stack. Other terms of claim 16 which were changed for clarity are treated in the same manner.
Regarding claim 17, Im in view of Kim teaches the semiconductor package of claim 16, wherein: the plurality of high bandwidth memories (structure of Im, fig. 7D, as modified by Kim) are disposed around the logic die (Kim 120a), and horizontally adjacent (laterally flanking; see Kim fig. 13) to the logic die (Kim 120a).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Im in view of Kim as applied to claim 16 above, and further in view of U.S. Pat. Pub. No. US 20220399287 A1 to Choi (hereinafter “Choi”).
Regarding claim 18, Im in view of Kim does not teach the semiconductor package of claim 16, wherein: the interposer is a silicon interposer. It is noted that Kim (used to modify Im to comprise an interposer) is silent on the material of the interposer.
Choi, however, teaches a semiconductor package (fig. 24B) wherein the interposer (50; fig. 24B) [0048] is a silicon interposer [0048].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the package of Im in view of Kim to comprise a silicon interposer to allow for the formation of a redistribution interposer as taught by Choi [0048].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Im in view of Kim and further in view of U.S. Pat. Pub. No. US 20230005526 A1 to Suthram et al. (hereinafter “Suthram”).
Regarding claim 19, Im teaches a semiconductor package (fig. 7D) comprising:
a high bandwidth memory (structure of fig. 7D), wherein:
the high bandwidth memory (structure of fig. 7D) includes:
a buffer die (substrate 110; fig. 7D) [0095];
a memory (semiconductor chip 120 which may comprise a memory structure; fig. 7D) [0095] disposed on the buffer die (110);
one or more heat dissipation structures (140; fig. 7D) [0097] disposed on the buffer die (110), and horizontally adjacent (horizontally adjacent in fig. 7D) to the memory (120); and
a first molding material (130; fig. 7D) [0096] disposed on the buffer die (110) and encapsulating (be disposed on both horizontal sides) the memory (120) and the one or more heat dissipation structures (140).
Im, in fig. 7D, does not teach that the memory is a stack or that the memory stack includes a stack of a plurality of memory dies.
Im, however, in fig. 19E, teaches a memory stack (of chips 120 and 220) including a stack of a plurality of memory dies (chips 120 and 220 which comprise memory structures; fig. 19E) [0095] & [0143].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the structure of fig. 7D to comprise a memory stack including a stack of a plurality of memory dies to increase circuit density as taught by Im [0143].
Im further does not teach an interposer, or a logic die on the interposer.
Kim, of record, however, teaches a semiconductor package (fig. 13) including: an interposer (substrate 110; fig. 13) [0024], a logic die (semiconductor chip structure 120a; fig. 13) [0051] on the interposer (110).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the package of Im to comprise an interposer with a logic die on the interposer, to create a package with processing power and memory as taught by Kim [0051].
Im further does not teach that the high bandwidth memory is on the logic die.
Suthram, however, teaches a semiconductor package (fig. 6) with a memory stack (stack with N memory dies; fig. 6) [0082] comprising a high bandwidth memory (memory stack) on a logic die (640; fig. 6) [0082].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the structure of Im in view of Kim to move the logic die below the memory stack to allow for signal and power connections to run vertically as taught by Suthram [0082]-[0083]. It is noted that the above modification further increases circuit density through vertical integration of components.
The term “memory stack” is changed above is certain instances to improve clarity in the context of claim 19. In the interest of clarify for the claims which depend from claim 19, the term “memory stack” is unchanged, and it is noted that the memory of Im fig. 7D is modified to comprise a memory stack. Other terms of claim 19 which were changed for clarity are treated in the same manner.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Im in view of Kim and Suthram as applied to claim 19 above, and further in view of U.S. Pat. Pub. No. US 20190229101 A1 to Lee (hereinafter “Lee”).
Regarding claim 20, Im in view of Kim and Suthram does not teach the semiconductor package of claim 19, further comprising: a second molding material that is provided on the interposer so as to encapsulate the logic die and the high bandwidth memory.
Lee, however, teaches a semiconductor package (fig. 9) comprising a memory stack (311, 321, 331, 341; fig. 9) [0105] further comprising a second molding material (encapsulation layer 360; fig. 9) [0113] that is provided on the interposer (lower package 610; fig. 9) so as to encapsulate the logic die (411; fig. 9) [0123] and the high bandwidth memory (memory stack).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the package of Im in view of Kim and Suthram to comprise a second molding material meeting the limitations of claim 20 to cover the packages as taught by Lee [0113].
Allowable Subject Matter
Claims 6 and 14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, Im teaches away from the modification of the structure to reach the limitations of claim 6, thus making a modification thereof untenable. See Im ¶ [0100].
Regarding claim 14, it is not found a reference or combination of references which reasonably reads on “a second silicon a second silicon insulating layer that surrounds the side surfaces of the plurality of second bonding pads and is directly bonded to the first silicon insulating layer.” It is understood that the term “directly bonded” refers to direct bonding, a term of art that at least requires physical contact. There are many references which teach two silicon insulating layers surrounding bonding pads (see U.S. Pat. Pub. No. US 20230352381 A1 to Liao et al., fig. 18, elements 950 and 292), but these elements are not in physical contact and thus not directly bonded.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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