DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communication dated 05/27/2026.
Claims 1-20 are pending in this application.
Remarks
2. Applicants’ argument(s) have been fully considered, but are not persuasive.
A. With respect to the prior art of Kim et al. (US 2018/0240729):
A1. Applicant argued that Kim does not disclose a third stacked semiconductor package (See Applicant’s Remarks, page 6 of 10). This is not agreed.
As discussed at para. 0117, Kim discloses a base substrate 300 (shown in figure 15) comprising a recess 302 in which a die 200 is embedded (Fig. 16). Figure 18 further discloses a redistribution layer 350 with solder balls 360 attached to exposed surface of the die 200 as well as to a surface of the substrate 300 forming substrate structure 300.
In Figure 19, Kim discloses, as stated at para. 0134:
“[0134] Referring to FIG. 19, a first semiconductor package structure P2a and a second semiconductor package structure P2b, according to the second exemplary embodiment described with reference to FIG. 18, may be provided. The second semiconductor package structure P2b may be disposed on the first semiconductor package structure P2a.”
At para. 0137, Kim further states:
“[0137] Although, in FIG. 19, two semiconductor package structures are illustrated to be stacked, the number of the stacked semiconductor package structures may be three or more.”
Accordingly, one of ordinary skill in the art would understand that should the number of the stacked semiconductor package structures be three or more as taught by Kim, three or more semiconductor package structures, according to the second exemplary embodiment described with reference to FIG. 18, may be disposed one on top of another in a manner similar to the second semiconductor package structure P2b disposed on the first semiconductor package structure P2a of Figure 18. That is, according to Kim, there may be a third semiconductor package structure similar to that shown in figure 18, let’s say, the semiconductor package structure P2c, stacked on the second package structure P2b, just similar to the second package structure P2b stacked on the first package structure P2a of figure 19. Since Kim does not teach otherwise, one of ordinary skill in the art would understand that the third or more semiconductor package structures should be stacked in the manner similar to the previous ones. There is no reason for one of ordinary skill in the art to understand otherwise.
A2. Applicant further argued that element 260b of Figure 19 is not a connection structure disposed between the substrates. See Applicant’s argument, the last paragraph of page 7 of 10. This in not persuasive.
Note: The reference to “260b” mentioned by the Applicant (which was used in the Office Action of 02/27/2026) is a typographical error and should be corrected to “360b”, which refers to a solder ball connection shown in Figure 19 of Kim, “360b” will be used hereinafter.
Figure 19 clearly shows solder balls 360b electrically connecting the substrate 300a of the first semiconductor package structure P2a to the substrate 300b of the second package structure P2b via the redistribution layer 350. See also para. 0128. That is, Kim does disclose the connection structures 360b connecting between the substrates.
B. With respect to the prior art of Dalmia et al. (US 2019/0139915)
B1. Applicant argued that semiconductor packages 102, 106, and 108 shown in Figure 1 of Dalmia are not substrates recited in the claimed invention because they are integrated, multi-layer package structures composed of successive laminated dielectric and metallization layers formed of built-up layers 120, 134, 136, 156, and core layers 116, 130, 152, and that they are not three distinct substrates built independently.
See Applicant’s Remarks, page 8 of 10 and page 9 of 10.
This in not found persuasive.
Paragraph 0023 of Dalmia recites:
“[0023] According to example embodiments, the semiconductor package may include a substrate. In some cases, the package substrate may be an organic structure. In other cases, the package substrate may be inorganic (e.g., ceramic, glass, etc.). The package substrate may, in example embodiments, include a core layer with one or more interconnect layers built up on one or both sides of the core layer. The build-up layers, as built up on the core, may have interconnects, or traces, formed therein. The traces may provide electrical pathways for signals between electronic components (e.g., integrated circuits, passive devices, etc.), input/output (I/O) connections on the semiconductor package, signal fan out from/to the electronic components, signal connections between two or more electrical components, power delivery to electrical component(s), ground connections to electrical component(s), clock signal delivery to the electrical component(s), combinations thereof, or the like. The build-up layers may be fabricated on one or both sides of the package core. In some cases, there may be the same number of build-up layers on both sides of the package core. In other cases, the build-up layers formed on either side of the package core may be asymmetric. The stack-up may also be asymmetric by having different layer thicknesses on either side of the core. Furthermore, the core of the semiconductor package may have a plurality of through vias to make electrical connections from one side of the core to the other side of the core. Thus, through vias in the core may allow electrical connections between one or more build-up layers on the top of the semiconductor package to one or more build-up layers on the bottom of the semiconductor package. In some alternative embodiments, a coreless substrate may be used, where the semiconductor package may not have a core. The layers in the substrate can be disparate, and of different thicknesses. It is possible for such a package to have components embedded in them, such as Si/packaged Si, and/or other SMT components.”,
Paragraph 0038 further recites:
[0038] In example embodiments, semiconductor package core 116, antenna package core 1152, and/or cap package core 130 may have build-up layers 120, 134, 136, 156 formed thereon. In example embodiments, the package substrate, the antenna substrate, and/or cap package substrate may be singulated into separate semiconductor packages 102, antenna packages 108, and/or cap packages 106 after completing other fabrication processes in a batch fashion with other packages on the same panel. The semiconductor package core 116, antenna package core 152, and/or cap package core 130 may be of any suitable size and/or shape. For example, the semiconductor package core 116, antenna package core 152, and/or cap package core 130, in example embodiments, may be a rectangular panel. In example embodiments, the cores 116, 130, 152 may be fabricated of any suitable material, including polymer material, ceramic material, plastics, composite materials, glass, epoxy laminates of fiberglass sheets, FR-4 materials, FR-5 materials, combinations thereof, or the like. The cores 116, 130, 152 may have through vias 118, 132, 154 formed therein. Through vias 118, 132, 154 may be used for propagating electrical signals from the top of the package core 116, 130, 152 to the bottom of the package core 116, 130, 152, and vice versa. It will be appreciated that in some example embodiments, the core 116 material may be the same as core 130 material and/or the core 152 material. In other example embodiments, one or more of the cores 116, 130, 152 cores may be constructed of different materials from the other of the cores 116, 130, 152.”
The instant claimed inventions, as recited in claim 1 and claim 16, for example, merely recite “a base substrate”, “a first substrate”, and “a second substrate”, and fail to exclude substrates comprising multi-layer package structures composed of successive laminated dielectric and metallization layers formed of built-up layers and core layers, nor do they explain how the substrates are built, whether independently or not.
Therefore, the substrates 102, 106, and 108 of Dalmia do meet the claimed features the “base substrate”, the “first substrate”, and the “second substrate”, respectively.
B2. Applicant argued that the cavity 138 in the first substrate 106 is not adjacent the first side (upper side in Fig. 1 of Dalmia) of the base substrate 102. This is not agreed.
Fig. 1 shows the first side (or upper side) of the base substrate 102 faces the bottom surface of the first substrate 106 as well as the cavity 138 formed through the bottom surface of the first substrate 106, wherein the first embedded component 104 is disposed in the cavity 138. The cavity 138 is clearly adjacent the first side of the base substrate 102.
Claim Rejections - 35 USC § 102 / § 103
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Kim et al. (US 2018/0240729)
Note: As stated at para. [0137] of Kim: “Although, in FIG. 19, two semiconductor package structures are illustrated to be stacked, the number of the stacked semiconductor package structures may be three or more.”
Accordingly, in case the number of stacked semiconductor package structure is three, such as a third package P2c similar to packages P2a, P2b is stacked on top of package P2b in fig. 19 (see also the above remarks with respect to Kim), then:
Regarding claim 1, Kim discloses an apparatus, comprising:
a base substrate 300b (see fig. 19) having a first side (upper side) and a second side (lower side);
a first substrate 300c on the first side of the base substrate 300b, the first substrate 300c having a first embedded component 200c disposed in a cavity 302 (fig. 15) adjacent the first side of the base substrate 300b;
a second substrate 300a on the second side of the base substrate 300b;
a first connection structure 360c disposed between the first substrate 300c and the base substrate 300b configured to electrically couple the first substrate 300c to the base substrate 300b; and
a second connection structure 360b disposed between the second substrate 300a and the base substrate 300b configured to electrically couple the second substrate 300a to the base substrate 300b.
Regarding claim 2, Kim discloses the apparatus of claim 1, wherein each of the base substrate, the first substrate, and the second substrate each comprise: a first solder resist layer (solder mask: see paras. 0020, 0033; or solder resist layer which is passivation layers described at paras. 0075, 0128) disposed on a first outer surface; and a second solder resist layer disposed on a second outer surface.
Regarding claim 3, Kim discloses the apparatus of claim 2, wherein:
the base substrate further comprises a base metallization structure 202, 312, 314, 316 (fig. 16) including a plurality of metal layers and vias coupling the plurality of metal layers,
the first substrate further comprises a first metallization structure including a plurality of metal layers and vias coupling the plurality of metal layers, and
the second substrate further comprises a second metallization structure including a plurality of metal layers and vias coupling the plurality of metal layers. See figs. 16, 19.
Regarding claim 4, Kim discloses the apparatus of claim 3, wherein:
the first connection structure 360c is coupled to the first metallization structure and the base metallization structure through openings in adjacent solder resist layers, and the second connection structure 360b is coupled to the second metallization structure and the base metallization structure through openings in adjacent solder resist layers. See fig. 19.
Regarding claim 5, Kim discloses the apparatus of claim 4, wherein the base substrate 300b comprises: a substrate having a core (which is central part of the substrate; note that the instant claim language fails to specifically define what is the core of the substrate, therefore, as a common sense or by dictionary definition, something that is central to its existence or character is the core of it).
Regarding claim 6, Kim discloses the apparatus of claim 5, wherein the base metallization structure comprises: at least one plated through hole (PTH) (through holes with seed layer along inner surface of the hole; para. 0071) disposed through the core configured to couple portions of the base metallization structure on opposite sides of the core.
Regarding claim 7, Kim discloses the apparatus of claim 6, wherein the base substrate 300b further comprises: a component embedded in the core (embedded component 312c or 330c or 321c in fig. 19; note that the instant claim language fails to particular describe what is the embedded component; therefore, any embedded component/element can meet the claim feature).
Regarding claim 8, Kim discloses the apparatus of claim 3, wherein the first embedded component 200c comprises a plurality of connectors 322c, 204c configured to couple the first embedded component 200c to the first metallization structure. See fig. 19.
Regarding claim 9, Kim discloses the apparatus of claim 3, wherein the first substrate 300c further comprises: at least one additional embedded component 312c or 330c or 321c (note that the instant claim language fails to particular describe what is the embedded component; therefore, any embedded component/element can meet the claim feature).
Regarding claim 10, Kim discloses the apparatus of claim 3, wherein the first metallization structure 314, 316 comprises: fiberglass impregnated with resin (prepreg), Ajinomoto build-up film (ABF), or a resin coated copper (RCC) build-up film. See paras. 0054-0056, 0072.
Regarding claim 11, Kim discloses the apparatus of claim 3, wherein the second substrate further comprises: a component 200a embedded in the second substrate 300a. See fig. 19.
Regarding claim 12, Kim discloses the apparatus of claim 3, wherein the second metallization structure comprises: fiberglass impregnated with resin (prepreg), Ajinomoto build-up film (ABF), or a resin coated copper (RCC) build-up film. See paras. 0054-0056, 0072.
Regarding claim 13, Kim discloses the apparatus of claim 1, further comprising:
a first molding compound 330c disposed between the first substrate 300c and the base substrate 300b, wherein the first molding compound 330c at least partially encapsulates the first connection structure 202 (fig. 16) and the first embedded component 200; and
a second molding compound 330b disposed between the second substrate 300a and the base substrate 300b, wherein the second molding compound at least partially encapsulates the second connection structure. See figs. 16, 19.
Regarding claim 14, Kim discloses the apparatus of claim 1, further comprising:
a die 200d (in the fourth package P2d) electrically coupled to the first substrate and disposed on a surface of the first substrate opposite the base substrate. See fig. 19, and para. 0137.
Regarding claim 15, Kim discloses the apparatus of claim 1, wherein the apparatus comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle. See paras. 0002-0003.
Regarding claim 16, Kim discloses a method of manufacturing an apparatus, the method comprising:
forming a base substrate 300b (see fig. 19) having a first side (upper side) and a second side (lower side);
a first substrate 300c on the first side of the base substrate 300b, the first substrate 300c having a first embedded component 200c disposed in a cavity 302 (fig. 15) adjacent the first side of the base substrate 300b;
forming a second substrate 300a on the second side of the base substrate 300b;
forming a first connection structure 360c disposed between the first substrate 300c and the base substrate 300b configured to electrically couple the first substrate 300c to the base substrate 300b; and
forming a second connection structure 360b disposed between the second substrate 300a and the base substrate 300b configured to electrically couple the second substrate 300a to the base substrate 300b.
Regarding claims 17, Kim discloses the method of claim 16, wherein each of the base substrate, the first substrate, and the second substrate each comprise:
a first solder resist layer (solder mask; see para. 0020) disposed on a first outer surface; and
a second solder resist layer (solder mask) disposed on a second outer surface.
Regarding claim 18, Kim discloses the method of claim 17, wherein:
the base substrate further comprises a base metallization structure 202, 312, 314, 316 (fig. 16) including a plurality of metal layers and vias coupling the plurality of metal layers,
the first substrate further comprises a first metallization structure 202, 312, 314, 316 (fig. 16) including a plurality of metal layers and vias coupling the plurality of metal layers, and
the second substrate further comprises a second metallization structure 202, 312, 314, 316 (fig. 16) including a plurality of metal layers and vias coupling the plurality of metal layers. See figs. 16, 19.
Regarding claim 19, Kim discloses the method of claim 18, further comprising:
coupling the first connection structure 360c to the first metallization structure and the base metallization structure through openings in adjacent solder resist layers, and
coupling the second connection structure 360b to the second metallization structure and the base metallization structure through openings in adjacent solder resist layers. See fig. 19.
Regarding claim 20, Kim discloses the method of claim 19, wherein forming the base substrate further comprises: forming at least one plated through hole (PTH) (through holes with seed layer along inner surface of the hole; para. 0071) disposed through a core (which is central part of the substrate; note that the instant claim language fails to specifically define what is the core of the substrate, therefore, as a common sense or by dictionary definition, something that is central to its existence or character is the core of it) configured to couple portions of the base metallization structure on opposite sides of the core; and
embedding a component (portion of connection plug 312, 314, and/or 316, fig. 19) in the core.
6. Claims 1-7, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dalmia et al. (US 2019/0139915)
Regarding claim 1, Dalmia discloses an apparatus, comprising:
a base substrate 102 (see fig. 1) having a first side (upper side) and a second side (lower side);
a first substrate 106 on the first side of the base substrate 102, the first substrate 106 having a first embedded component 104 disposed in a cavity 138 adjacent the first side of the base substrate 102;
a second substrate 108 on the second side of the base substrate 102;
a first connection structure 128, 142 (or connection structure formed in layers 136 and connected to interconnects 128) disposed between the first substrate 106 and the base substrate 102 configured to electrically couple the first substrate to the base substrate; and
a second connection structure 124, 160, 164 disposed between the second substrate 108 and the base substrate 102 configured to electrically couple the second substrate to the base substrate.
Regarding claim 2, Dalmia discloses the apparatus of claim 1, wherein each of the base substrate 102, the first substrate 106, and the second substrate 108 each comprise:
a first solder resist layer 120, 134, 136, 156 disposed on a first outer surface; and
a second solder resist layer 120, 134, 136, 156 disposed on a second outer surface. See fig. 1 and para. 0040.
Regarding claim 3, Dalmia discloses the apparatus of claim 2, wherein:
the base substrate 102 further comprises a base metallization structure 118, 122, 124 including a plurality of metal layers and vias coupling the plurality of metal layers, the first substrate 106 further comprises a first metallization structure 132, 140, 128 including a plurality of metal layers and vias coupling the plurality of metal layers, and the second substrate 108 further comprises a second metallization structure 154, 164 including a plurality of metal layers and vias coupling the plurality of metal layers. See fig. 19.
Regarding claim 4, Dalmia discloses the apparatus of claim 3, wherein:
the first connection structure 128 is coupled to the first metallization structure and the base metallization structure through openings in adjacent solder resist layers, and the second connection structure 124, 160, 164 is coupled to the second metallization structure and the base metallization structure through openings in adjacent solder resist layers. See fig. 1.
Regarding claim 5, Dalmia discloses the apparatus of claim 4, wherein the base substrate 102 comprises: a substrate having a core 116. See fig. 19.
Regarding claim 6, Dalmia discloses the apparatus of claim 5, wherein the base metallization structure comprises: at least one plated through hole (PTH) disposed through the core configured to couple portions of the base metallization structure on opposite sides of the core. See paras. 0019, 0038. It is noted that a plated through hole interconnection is well known for preventing unwanted diffusion from the conductive metal wires to the surrounding.
Regarding claim 7, Dalmia discloses the apparatus of claim 6, wherein the base substrate further comprises: a component 118 (or component 104 in fig. 7) embedded in the core. See fig. 1.
Regarding claim 16, Dalmia discloses a method of manufacturing an apparatus, the method comprising:
forming a base substrate 102 (fig. 1) having a first side and a second side;
forming a first substrate 106 on the first side of the base substrate 102, the first substrate having a first embedded component 104 disposed in a cavity 138 adjacent the first side of the base substrate 102;
forming a second substrate 108 on the second side of the base substrate 102;
forming a first connection structure 128, 142 (or connection structure formed in layers 136 and connected to interconnects 128) disposed between the first substrate 106 and the base substrate 102 configured to electrically couple the first substrate to the base substrate; and
forming a second connection structure 124, 160, 164 disposed between the second substrate and the base substrate configured to electrically couple the second substrate to the base substrate.
Regarding claim 17, Dalmia discloses the method of claim 16, wherein each of the base substrate, the first substrate, and the second substrate each comprise: a first solder resist layer 120, 134, 136, 156 disposed on a first outer surface; and a second solder resist layer 120, 134, 136, 156 disposed on a second outer surface. See fig. 1, and para. 0040.
Regarding claim 18, Dalmia discloses the method of claim 17, wherein:
the base substrate 102 further comprises a base metallization structure 118, 122, 124 including a plurality of metal layers and vias coupling the plurality of metal layers, the first substrate 106 further comprises a first metallization structure 128, 132, 140 including a plurality of metal layers and vias coupling the plurality of metal layers, and the second substrate 108 further comprises a second metallization structure 154, 164 including a plurality of metal layers and vias coupling the plurality of metal layers. See fig. 1.
Regarding claim 19, Dalmia discloses the method of claim 18, further comprising: coupling the first connection structure to the first metallization structure and the base metallization structure through openings in adjacent solder resist layers, and coupling the second connection structure to the second metallization structure and the base metallization structure through openings in adjacent solder resist layers. See fig. 1.
Regarding claim 20, Dalmia discloses the method of claim 19, wherein forming the base substrate further comprises: forming at least one plated through hole (PTH) disposed through a core configured to couple portions of the base metallization structure on opposite sides of the core; and embedding a component in the core. See paras. 0019, 0038. It is noted that a plated through hole interconnection is well known for preventing unwanted diffusion from the conductive metal wires to the surrounding.
Conclusion
7. THIS ACTION IS MADE FINAL. A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on 9:00AM - 5:00PM If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is (571)273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/
Primary Examiner, Art Unit 2818
July 31, 2026
Prosecution Insights