DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 06/25/2025.
Claims 1-20 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 01/05/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2018/0240729)
Note: As stated at para. [0137] of Kim: “Although, in FIG. 19, two semiconductor package structures are illustrated to be stacked, the number of the stacked semiconductor package structures may be three or more.”
Accordingly, in case the number of stacked semiconductor package structure is three, such as a third package P2c similar to packages P2a, P2b is stacked on top of package P2b in fig. 19, then:
Regarding claim 1, Kim discloses an apparatus, comprising:
a base substrate 300b (see fig. 19) having a first side (upper side) and a second side (lower side);
a first substrate 300c on the first side of the base substrate 300b, the first substrate 300c having a first embedded component 200c disposed in a cavity 302 (fig. 15) adjacent the first side of the base substrate 300b;
a second substrate 300a on the second side of the base substrate 300b;
a first connection structure 360c disposed between the first substrate 300c and the base substrate 300b configured to electrically couple the first substrate 300c to the base substrate 300b; and
a second connection structure 260b disposed between the second substrate 300a and the base substrate 300b configured to electrically couple the second substrate 300a to the base substrate 300b.
Regarding claim 2, Kim discloses the apparatus of claim 1, wherein each of the base substrate, the first substrate, and the second substrate each comprise: a first solder resist layer (solder mask: see paras. 0020, 0033; or solder resist layer which is passivation layers described at paras. 0075, 0128) disposed on a first outer surface; and a second solder resist layer disposed on a second outer surface.
Regarding claim 3, Kim discloses the apparatus of claim 2, wherein:
the base substrate further comprises a base metallization structure 202, 312, 314, 316 (fig. 16) including a plurality of metal layers and vias coupling the plurality of metal layers,
the first substrate further comprises a first metallization structure including a plurality of metal layers and vias coupling the plurality of metal layers, and
the second substrate further comprises a second metallization structure including a plurality of metal layers and vias coupling the plurality of metal layers. See figs. 16, 19.
Regarding claim 4, Kim discloses the apparatus of claim 3, wherein:
the first connection structure 360c is coupled to the first metallization structure and the base metallization structure through openings in adjacent solder resist layers, and the second connection structure 360b is coupled to the second metallization structure and the base metallization structure through openings in adjacent solder resist layers. See fig. 19.
Regarding claim 5, Kim discloses the apparatus of claim 4, wherein the base substrate 300b comprises: a substrate having a core (which is central part of the substrate; note that the instant claim language fails to specifically define what is the core of the substrate, therefore, as a common sense or by dictionary definition, something that is central to its existence or character is the core of it).
Regarding claim 6, Kim discloses the apparatus of claim 5, wherein the base metallization structure comprises: at least one plated through hole (PTH) (through holes with seed layer along inner surface of the hole; para. 0071) disposed through the core configured to couple portions of the base metallization structure on opposite sides of the core.
Regarding claim 7, Kim discloses the apparatus of claim 6, wherein the base substrate 300b further comprises: a component embedded in the core (embedded component 312c or 330c or 321c in fig. 19; note that the instant claim language fails to particular describe what is the embedded component; therefore, any embedded component/element can meet the claim feature).
Regarding claim 8, Kim discloses the apparatus of claim 3, wherein the first embedded component 200c comprises a plurality of connectors 322c, 204c configured to couple the first embedded component 200c to the first metallization structure. See fig. 19.
Regarding claim 9, Kim discloses the apparatus of claim 3, wherein the first substrate 300c further comprises: at least one additional embedded component 312c or 330c or 321c (note that the instant claim language fails to particular describe what is the embedded component; therefore, any embedded component/element can meet the claim feature).
Regarding claim 10, Kim discloses the apparatus of claim 3, wherein the first metallization structure 314, 316 comprises: fiberglass impregnated with resin (prepreg), Ajinomoto build-up film (ABF), or a resin coated copper (RCC) build-up film. See paras. 0054-0056, 0072.
Regarding claim 11, Kim discloses the apparatus of claim 3, wherein the second substrate further comprises: a component 200a embedded in the second substrate 300a. See fig. 19.
Regarding claim 12, Kim discloses the apparatus of claim 3, wherein the second metallization structure comprises: fiberglass impregnated with resin (prepreg), Ajinomoto build-up film (ABF), or a resin coated copper (RCC) build-up film. See paras. 0054-0056, 0072.
Regarding claim 13, Kim discloses the apparatus of claim 1, further comprising:
a first molding compound 330c disposed between the first substrate 300c and the base substrate 300b, wherein the first molding compound 330c at least partially encapsulates the first connection structure 202 (fig. 16) and the first embedded component 200; and
a second molding compound 330b disposed between the second substrate 300a and the base substrate 300b, wherein the second molding compound at least partially encapsulates the second connection structure. See figs. 16, 19.
Regarding claim 14, Kim discloses the apparatus of claim 1, further comprising:
a die 200d (in the fourth package P2d) electrically coupled to the first substrate and disposed on a surface of the first substrate opposite the base substrate. See fig. 19, and para. 0137.
Regarding claim 15, Kim discloses the apparatus of claim 1, wherein the apparatus comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle. See paras. 0002-0003.
Regarding claim 16, Kim discloses a method of manufacturing an apparatus, the method comprising:
forming a base substrate 300b (see fig. 19) having a first side (upper side) and a second side (lower side);
a first substrate 300c on the first side of the base substrate 300b, the first substrate 300c having a first embedded component 200c disposed in a cavity 302 (fig. 15) adjacent the first side of the base substrate 300b;
forming a second substrate 300a on the second side of the base substrate 300b;
forming a first connection structure 360c disposed between the first substrate 300c and the base substrate 300b configured to electrically couple the first substrate 300c to the base substrate 300b; and
forming a second connection structure 260b disposed between the second substrate 300a and the base substrate 300b configured to electrically couple the second substrate 300a to the base substrate 300b.
Regarding claims 17, Kim discloses the method of claim 16, wherein each of the base substrate, the first substrate, and the second substrate each comprise:
a first solder resist layer (solder mask; see para. 0020) disposed on a first outer surface; and
a second solder resist layer (solder mask) disposed on a second outer surface.
Regarding claim 18, Kim discloses the method of claim 17, wherein:
the base substrate further comprises a base metallization structure 202, 312, 314, 316 (fig. 16) including a plurality of metal layers and vias coupling the plurality of metal layers,
the first substrate further comprises a first metallization structure 202, 312, 314, 316 (fig. 16) including a plurality of metal layers and vias coupling the plurality of metal layers, and
the second substrate further comprises a second metallization structure 202, 312, 314, 316 (fig. 16) including a plurality of metal layers and vias coupling the plurality of metal layers. See figs. 16, 19.
Regarding claim 19, Kim discloses the method of claim 18, further comprising:
coupling the first connection structure 360c to the first metallization structure and the base metallization structure through openings in adjacent solder resist layers, and
coupling the second connection structure 360b to the second metallization structure and the base metallization structure through openings in adjacent solder resist layers. See fig. 19.
Regarding claim 20, Kim discloses the method of claim 19, wherein forming the base substrate further comprises: forming at least one plated through hole (PTH) (through holes with seed layer along inner surface of the hole; para. 0071) disposed through a core (which is central part of the substrate; note that the instant claim language fails to specifically define what is the core of the substrate, therefore, as a common sense or by dictionary definition, something that is central to its existence or character is the core of it) configured to couple portions of the base metallization structure on opposite sides of the core; and
embedding a component (portion of connection plug 312, 314, and/or 316, fig. 19) in the core.
6. Claims 1-7, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dalmia et al. (US 2019/0139915)
Regarding claim 1, Dalmia discloses an apparatus, comprising:
a base substrate 102 (see fig. 1) having a first side (upper side) and a second side (lower side);
a first substrate 106 on the first side of the base substrate 102, the first substrate 106 having a first embedded component 104 disposed in a cavity 138 adjacent the first side of the base substrate 102;
a second substrate 108 on the second side of the base substrate 102;
a first connection structure 128, 142 (or connection structure formed in layers 136 and connected to interconnects 128) disposed between the first substrate 106 and the base substrate 102 configured to electrically couple the first substrate to the base substrate; and
a second connection structure 124, 160, 164 disposed between the second substrate 108 and the base substrate 102 configured to electrically couple the second substrate to the base substrate.
Regarding claim 2, Dalmia discloses the apparatus of claim 1, wherein each of the base substrate 102, the first substrate 106, and the second substrate 108 each comprise:
a first solder resist layer 120, 134, 136, 156 disposed on a first outer surface; and
a second solder resist layer 120, 134, 136, 156 disposed on a second outer surface. See fig. 1 and para. 0040.
Regarding claim 3, Dalmia discloses the apparatus of claim 2, wherein:
the base substrate 102 further comprises a base metallization structure 118, 122, 124 including a plurality of metal layers and vias coupling the plurality of metal layers, the first substrate 106 further comprises a first metallization structure 132, 140, 128 including a plurality of metal layers and vias coupling the plurality of metal layers, and the second substrate 108 further comprises a second metallization structure 154, 164 including a plurality of metal layers and vias coupling the plurality of metal layers. See fig. 19.
Regarding claim 4, Dalmia discloses the apparatus of claim 3, wherein:
the first connection structure 128 is coupled to the first metallization structure and the base metallization structure through openings in adjacent solder resist layers, and the second connection structure 124, 160, 164 is coupled to the second metallization structure and the base metallization structure through openings in adjacent solder resist layers. See fig. 1.
Regarding claim 5, Dalmia discloses the apparatus of claim 4, wherein the base substrate 102 comprises: a substrate having a core 116. See fig. 19.
Regarding claim 6, Dalmia discloses the apparatus of claim 5, wherein the base metallization structure comprises: at least one plated through hole (PTH) disposed through the core configured to couple portions of the base metallization structure on opposite sides of the core. See paras. 0019, 0038. It is noted that a plated through hole interconnection is well known for preventing unwanted diffusion from the conductive metal wires to the surrounding.
Regarding claim 7, Dalmia discloses the apparatus of claim 6, wherein the base substrate further comprises: a component 118 (or component 104 in fig. 7) embedded in the core. See fig. 1.
Regarding claim 16, Dalmia discloses a method of manufacturing an apparatus, the method comprising:
forming a base substrate 102 (fig. 1) having a first side and a second side;
forming a first substrate 106 on the first side of the base substrate 102, the first substrate having a first embedded component 104 disposed in a cavity 138 adjacent the first side of the base substrate 102;
forming a second substrate 108 on the second side of the base substrate 102;
forming a first connection structure 128, 142 (or connection structure formed in layers 136 and connected to interconnects 128) disposed between the first substrate 106 and the base substrate 102 configured to electrically couple the first substrate to the base substrate; and
forming a second connection structure 124, 160, 164 disposed between the second substrate and the base substrate configured to electrically couple the second substrate to the base substrate.
Regarding claim 17, Dalmia discloses the method of claim 16, wherein each of the base substrate, the first substrate, and the second substrate each comprise: a first solder resist layer 120, 134, 136, 156 disposed on a first outer surface; and a second solder resist layer 120, 134, 136, 156 disposed on a second outer surface. See fig. 1, and para. 0040.
Regarding claim 18, Dalmia discloses the method of claim 17, wherein:
the base substrate 102 further comprises a base metallization structure 118, 122, 124 including a plurality of metal layers and vias coupling the plurality of metal layers, the first substrate 106 further comprises a first metallization structure 128, 132, 140 including a plurality of metal layers and vias coupling the plurality of metal layers, and the second substrate 108 further comprises a second metallization structure 154, 164 including a plurality of metal layers and vias coupling the plurality of metal layers. See fig. 1.
Regarding claim 19, Dalmia discloses the method of claim 18, further comprising: coupling the first connection structure to the first metallization structure and the base metallization structure through openings in adjacent solder resist layers, and coupling the second connection structure to the second metallization structure and the base metallization structure through openings in adjacent solder resist layers. See fig. 1.
Regarding claim 20, Dalmia discloses the method of claim 19, wherein forming the base substrate further comprises: forming at least one plated through hole (PTH) disposed through a core configured to couple portions of the base metallization structure on opposite sides of the core; and embedding a component in the core. See paras. 0019, 0038. It is noted that a plated through hole interconnection is well known for preventing unwanted diffusion from the conductive metal wires to the surrounding.
Conclusion
7. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 February 25, 2026