DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species (a) in the reply filed on 6/01/26 is acknowledged. Species (a) corresponds to the embodiment of Figs. 2-3. Applicant states in the response that the election of species (a) corresponds to all claims 1-20. However, claim 6 corresponds to the embodiment of Fig. 10 (third wiring pattern connected to gate); claims 10-13 correspond to the embodiment of Fig. 20 (different layout of regions); claim 15 corresponds to the embodiment of Figs. 11-12 (second diode) and claim 17 corresponds to the embodiment of Fig. 17 (no second resistor). These embodiments and claim limitations are all mutually incompatible with the embodiment of Figs. 2-3 and will be withdrawn from consideration. The examined claims will be 1-5, 7-9, 14, 16, and 18-20.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 18, the final limitation “wherein the source region and the drain region are isolated from each other by the first emitter region and a second device isolation film” renders the claim indefinite. The source and drain region comprise a claimed transistor structure, which would not function if isolated by those regions. What disclosed structure this might be intended to correspond to could not be determined. Therefore, for purposes of examination, this limitation will not be considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shan (CN 111739887 A).
Regarding claim 1, Shan teaches a semiconductor device (Fig. 7, [0096]-[0102]), comprising:
a first well region formed in a substrate, the first well region including first conductivity-type impurities (301, n-type, [0093]),
a second well region formed in the substrate, the second well region including second conductivity-type impurities (302, p-type, [0093]),
a first collector region disposed in the first well region, the first collector region including the first conductivity-type impurities (303, n-type, T2, [0093]),
a first emitter region disposed in the second well region, the first emitter region including the first conductivity-type impurities (306, n-type, T2, [0093]),
a second emitter region disposed in the first well region, the second emitter region including the second conductivity-type impurities, and the second emitter region being connected to the first collector region by a first wiring pattern (304, p-type, T1, [0093]),
a second collector region disposed in the second well region, the second collector region including the second conductivity-type impurities, and the second collector region being connected to the first emitter region by a second wiring pattern (307, p-type, T1, [0093]),
a source region and a drain region disposed in the second well region, the source region and the drain region including the first conductivity-type impurities, and the source region and the drain region electrically isolated from the first well region (502/503, [0100]), and
a gate structure disposed on the second well region between the source region and the drain region in a first direction, the first direction being parallel to an upper surface of the substrate, and the gate structure being electrically connected to the source region or the drain region (501, [0104]).
Regarding claim 3, Shan teaches a first external resistor connected between the gate structure and the source region (Fig. 7, R4, [0105]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shan (CN 111739887 A) in view of Shan 104 (CN 112018104 A)
Regarding claim 2, Shan does not explicitly teach wherein the first well region and the second well region are isolated from each other by a device isolation film in the first direction.
Shan 104 teaches wherein a device similar to that of claim 1 may not have a device isolation film isolating the first and second well regions, comparable to Fig. 7 of Shan, and an alternative embodiment wherein the first well region and the second well region are isolated from each other by a device isolation film in the first direction (Figs. 3-4, [0031]-[0034]), and pro
Therefore it would have been obvious to a person having ordinary skill in the art to combine the teachings of Shan 104 with Shan such that the first well region and the second well region are isolated from each other by a device isolation film in the first direction because the prior art teaches an element which differs from the claim by substitution with a different element, the claimed element is known in the art, a person of ordinary skill could have substituted one known element for another, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143.I.B.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shan (CN 111739887) in view of Domanski (U.S. PGPub 2012/0099229).
Regarding claim 4, Shan does not explicitly teach a second external resistor connected between the source region and the second wiring pattern.
Domanski teaches an SCR device (Fig. 3d, [0033]) comprising a transistor, where a first resistor is connected between the gate and the source region and a second resistor is connected between the source region and the wiring pattern it is connected to (110, 112, [0028], [0033]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Domanski with Shan such that a second resistor is connected between the source region and the second wiring pattern for the purpose of adjusting the trigger current (Domanski, [0028]).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Shan (CN 111739887) in view of Kang (U.S. PGPub 2008/0174924).
Regarding claim 5, Shan does not explicitly teach a first active region disposed in the first well region, the first active region including the first conductivity-type impurities or the second conductivity-type impurities, and the first active region being connected to the drain region by a third wiring pattern.
Kang teaches an SCR device comprising a transistor disposed in a p-region and an n-type well comprising an active region connected to an s/d region (Figs. 6-7, 20/23, N1, 38, [0036]-[0037]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kang with Shan such that the device comprises a first active region disposed in the first well region, the first active region including the first conductivity-type impurities or the second conductivity-type impurities, and the first active region being connected to the drain region by a third wiring pattern for the purpose of increasing the holding voltage (Kang, [0046]).
Regarding claim 7, the combination of Shan and Kang teaches wherein the third wiring pattern is isolated from the gate structure (Shan, Fig. 7; Kang, Fig. 6). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shan and Kang for the reasons set forth in the rejection of claim 5.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Shan (CN 111739887) in view of Kang (U.S. PGPub 2008/0174924) and Mahajan (U.S. PGPub 2024/0079482).
Regarding claim 8, the combination of Shan and Kang does not explicitly teach a second active region disposed in the first well region between the first active region and the second well region in the first direction, the second active region including the first conductivity-type impurities.
Mahajan teaches an SCR device ([0005]) comprising first and second well regions (28/30, [0023]), a transistor disposed in the second well region and having source/drain regions of a first conductivity (40/44, [0032]) and an active region disposed in the first well region adjacent to the source/drain region and having the same conductivity type (Fig. 5, 48, [0036]).
Therefore it would have been obvious to a person having ordinary skill in the art to combine the teachings of Mahajan with Shan and Kang such that the device comprises a second active region disposed in the first well region between the first active region and the second well region in the first direction, the second active region including the first conductivity-type impurities for the purpose of improving device properties (Mahajan, [0034]).
Regarding claim 9, the combination of Shan, Kang, and Mahajan does not explicitly teach wherein an area of the second active region is greater than an area of the first active region.
Mahajan teaches wherein the width of the second active region may vary (Figs. 1, and 3-4). Further, mere changes in size or shape are prima facie obvious absent a teaching of unexpected results (See MPEP 2144.04). In this case, there is no teaching in Applicant’s disclosure regarding the purpose for or effect of the claimed area.
Therefore it would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shan, Kang, and Mahajan such that an area of the second active region is greater than an area of the first active region.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shan (CN 111739887) in view of Shan 104 (CN 112018104 A)
Regarding claim 18, Shan teaches a semiconductor device (Fig. 7, [0096]-[0102]), comprising:
a first well region formed in a substrate, the first well region including first conductivity-type impurities (301, n-type, [0093]),
a second well region formed in the substrate, the second well region including second conductivity-type impurities (302, p-type, [0093]),
an NPN transistor provided by a first collector region and a first emitter region, the first collector region being formed in the first well region and including first conductivity-type impurities, and the first emitter region being formed in the second well region and including the first conductivity-type impurities (303/306, T2, n-type, [0093]);
a PNP transistor provided by a second emitter region and a second collector region, the second emitter region being formed in the first well region and including second conductivity-type impurities different from the first conductivity-type impurities, and the second collector region being formed in the second well region and including the second conductivity-type impurities (304/307, T1, p-type, [0093]),
an NMOS transistor including a source region, a drain region, and a gate structure, the source region and the drain region being formed in the second well region and including the first conductivity-type impurities, and the gate structure being disposed between the source region and the drain region (501/502/503, [0100], [0104]).
Shan does not explicitly teach wherein the first and second well regions are isolated from each other by a first device isolation film.
Shan 104 teaches wherein a device similar to that of claim 1 may not have a device isolation film isolating the first and second well regions, comparable to Fig. 7 of Shan, and an alternative embodiment wherein the first well region and the second well region are isolated from each other by a device isolation film in the first direction (Figs. 3-4, [0031]-[0034]), and pro
Therefore it would have been obvious to a person having ordinary skill in the art to combine the teachings of Shan 104 with Shan such that the first well region and the second well region are isolated from each other by a device isolation film in the first direction because the prior art teaches an element which differs from the claim by substitution with a different element, the claimed element is known in the art, a person of ordinary skill could have substituted one known element for another, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143.I.B.
Regarding claim 20, Shan teaches wherein an external resistor is connected to at least one of a first region or a second region, the first region being disposed between the source region and the gate structure, and the second region being disposed between the source region and the first emitter region (Fig. 7, R4, [0105]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Shan (CN 111739887) in view of Shan 104 (CN 112018104 A) and Kim (U.S. PGPub 2010/0301418).
Regarding claim 19, the combination of Shan and Shan 104 does not explicitly teach wherein the first well region and the second well region are disposed in a deep-well region, and
wherein the deep-well region and the first well region include the first conductivity-type impurities, and wherein the second well region includes the second conductivity-type impurities.
Kim teaches an ESD protection device (Fig. 3B) comprising a first well region having a first conductivity type and a second well region having a second conductivity type disposed in a deep-well region having the first conductivity type (320, NW; 310, PW; 300, DNW, [0021]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim with Shan and Shan 104 such that the first well region and the second well region are disposed in a deep-well region, and wherein the deep-well region and the first well region include the first conductivity-type impurities, and wherein the second well region includes the second conductivity-type impurities for the purpose of electrically separating the device from the substrate (Kim, [0021]).
Allowable Subject Matter
Claims 14 and 16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 14, Shan teaches a semiconductor device (Fig. 7, [0096]-[0102]), comprising:
a first pad configured to input and output a signal and a second pad configured to be supplied with a reference voltage (309/310, [0093], [0005]),
an NPN transistor including a first collector, a first emitter, and a first base, the first collector connected to the first pad and the first emitter connected to the second pad (T2, 303, 306, 302, [0093]),
a PNP transistor including a second emitter, a second collector, and a second base, the second emitter connected to the first pad, the second collector connected to the second pad and the first base, and the second base connected to the first collector (T1, 307, 304, 301, [0093]), and
an NMOS transistor including a drain, a source, and a gate, the source connected to the second pad, and the gate connected to the source or the drain (501/502/503, [0100], [0104]).
However, the prior art, alone or in combination, does not teach the drain connected to the first collector, a first diode including an anode and a cathode, the anode connected to the drain, and the cathode connected to the first collector and the second base, in combination with the rest of the claim limitations. Claim 16 depends from and further limits claim 14 and is therefore correspondingly allowable.
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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