DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 11,870,405. Although the conflicting claims are not identical, they are not patentably distinct from each other because all of the limitations of the present claims are present in the patented claims and the newly added limitations/feature, namely “output matching circuit” would be considered as well-known/widely-used feature in the field.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-13 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Youssef et al. (U.S. 2014/0266461).
Regarding claim 1, Youssef et al. (hereinafter, Ref~461) discloses (please see Figs. 2-5 and related text for details) a low noise amplifier (LNA) comprising:
an input port (RFin of Fig. 4B);
an output port (output port of 240 of Fig. 4B);
an output matching circuit (not expressly shown, but Ref~461 teaches that circuit 240 of Fig. 2 may include matching circuits as described in paragraph [0019]) coupled to the output port;
an amplifier circuit (430/440 of Fig. 4B) coupled to the input port and the output matching circuit, wherein the amplifier circuit comprises a plurality of transistors (e.g., input transistors 434/444 and cascode transistors 436/446 of Fig. 4B) configured to selectively provide (via gate control signals Vcas1/Vcas2 of Fig. 4B) an output signal (via drain) to the output port by the output matching circuit based on an input signal (RFin of Fig. 4B) received at the input port;
a bypass path (provided by the ON/OFF from cascode transistors 436 and/or 446 of Fig. 4B) coupled to the input port and the output port and configured to selectively (via gate control signals Vcas1 and/or Vcas2 of Fig. 4B) provide the input signal from the input port to the output port; and
a capacitor circuit (420x of Fig. 4B and/or 470 of Fig. 4C) and/or an inductor circuit (432 of Fig. 4B):
wherein the capacitor circuit is coupled to a first transistor (e.g., 434 and/or 444 of Fig. 4B) of the plurality of transistors and has a first terminal (upper terminal of 420x of Fig. 4B) and a second terminal (lower terminal of 420x of Fig. 4), wherein the capacitor circuit comprises:
a capacitive element (e.g., 422 of Fig. 4) between the first terminal and the second terminal; and
a capacitor switch (424 of Fig. 4B) between the first terminal and the second terminal and connected in series with the capacitive element as seen; and
wherein the inductor circuit comprises:
a first inductive element (please note that inductor 432 of Fig. 4B may be implemented as a fix inductive element or a configurable one as described in paragraph 0051) coupled between ground and the first transistor; and
an inductor switch (not expressly shown, but suggested/mentioned in paragraph 0051) coupled in parallel with at least a portion of the first inductive element (please also note that linearization circuit 420 may also be coupled between the source of the gain transistor and the circuit ground as described in paragraph 0053), meeting claim 1.
Regarding claim 2, Ref~461 discloses the LNA of claim 1, further comprising a second inductive element (please inductor 484 from Fig. 4A) coupled to the output matching circuit (matching circuits from reference numeral 240 of Fig. 2 as described above) and to a power supply (VDD of Fig. 4A), meeting claim 2.
Regarding claim 3, Ref~461 discloses the LNA of claim 2, wherein a second transistor (see cascode transistors 436/446 of Fig. 4B) of the plurality of transistors is coupled to the first transistor, the output matching circuit, and the second inductive element, meeting claim 3.
Regarding claim 4, Ref~461 discloses the LNA of claim 1, wherein a second transistor of the plurality of transistors is coupled to the first transistor, wherein the second transistor is an output transistor coupled to the output port, wherein the output transistor is configured to receive a bias voltage (disposed at gate of cascode transistor) from a bias control processor (not expressly shown, but needed to at least provide control signals to switches disposed at gate of those cascode transistors), wherein a gain associated with the LNA is based at least in part on a voltage value of the bias voltage as described throughout the disclosure, and the newly added limitations/feature, namely “wherein the output matching circuit comprises a second capacitive element coupled to the output port and the plurality of transistors” would be considered as widely-used feature to in the field that may be employed for said generic matching circuits disclosed by Ref~461 in paragraph[ 0019] (also known as coupling capacitor for matching purposes) depending on custom specifications, meeting claim 4.
Regarding claim 7, Ref~461 discloses the LNA of claim 1, wherein the LNA comprises the inductor circuit, and wherein the first transistor is coupled to the input port, the inductor switch, and the first inductive element as seen from Fig. 4, meeting claim 7.
Regarding claim 8, Ref~461 discloses the LNA of claim 7, further comprising the capacitor circuit, wherein the plurality of transistors comprises a set of input transistors (434/444 of Fig. 4), wherein the set of input transistors comprises the first transistor (434 of Fig. 4) and at least one additional transistor (444 of Fig. 4 or more transistor if needed), wherein each input transistor of the set of input transistors is coupled to the input port, the capacitor switch, the capacitive element, the inductor switch, and the first inductive element, wherein a second transistor (cascode transistors of Fig. 4) of the plurality of transistors is coupled to the first transistor, wherein the second transistor is an output transistor coupled to the output port, and wherein the first inductive element is coupled between ground and a source of the first transistor as seen from Fig. 4, meeting claim 8.
Regarding claim 9, Ref~461 discloses the LNA of claim 1, further comprising a set of switches (see switches from 420y and/or 470 of Fig. 4C) each coupled to the input port, wherein the set of input transistors comprises at least the first transistor, wherein each switch of the set of switches is configured to selectively couple at least one transistor of the set of input transistors to the output port, and wherein a gain mode associated with the LNA is based at least in part on a state of each switch of the set of switches and a state of the capacitor switch of the capacitor circuit and/or a state of the inductor switch of the inductor circuit as seen (please note that more switches would be expected to at least provide adjustable features to inductor(s) and/or capacitor(s) shown in Fig. 4C as described in paragraph 0051-0053), meeting claim 9.
Regarding claim 10, Ref~461 discloses the LNA of claim 9, wherein for each switch of the set of switches: the switch is configured to receive a respective control signal (disposed at gate of those switches as expected); and
the state of the switch is based on the respective control signal, meeting claim 10.
Regarding claim 11, Ref~461 discloses the LNA of claim 1, wherein the amplifier circuit is configured to provide output signals, based on input signals received at the input port, to only the output port, and wherein the output port is the only output port of the LNA as seen from Fig. 4 (please note that one or more outputs would be possible as shown in various embodiments), meeting claim 11.
As to claims 12-13 and 15-19, these claims are merely the method and means to operate the circuit having structure recited in claims 1-11. Since Ref~461 teaches the structure, the method and means to operate such a circuit is inherently disclosed, meeting claims 12-20.
Response to Arguments
Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Allowable Subject Matter
Claims 5-6, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (Please note: this allowable subject matter is subject to an approval of a terminal disclaimer).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843
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