CTNF 18/406,068 CTNF 87887 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions 08-25-01 AIA Applicant's election without traverse of Group I (claims 1-12) in the reply filed on April 27 th , 2026 is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 07-34-01 AIA Claim s 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 11 recites the limitation “wherein the third dielectric layer includes a plurality of polishing marks opposite the first side of the interface die” in lines 7-9 while “a third dielectric layer disposed on the second side of the interface die” in line 7. It is unclear to the examiner how can the polishing marks opposite the first side of the interface die when the first side is facing away from the interface die and the second side is contacting the interface die. Claim 12 is rejected for depending on claim 11 and having the above issue incorporate into the claim. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-7 and are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SU et al. (Pub. No.: US 2024/0258302 A1), hereinafter as SU . Regarding claim 1 , SU discloses a semiconductor device assembly in Fig. 2B, comprising: a semiconductor die (die 206) having a frontside surface (top surface of region 212), a first plurality of bond pads (plurality of contacts 226) at the frontside surface and a first dielectric layer (dielectric layer 222) at the frontside surface (see [0036-0037] and [0047]); and an interface die (die 202) having a frontside surface (bottom surface of region 216) and a backside surface (top surface of region 214) (see [0034-0035]), the interface die including: a second plurality of bond pads (plurality of contacts 232) and a second dielectric layer (dielectric layer 228) disposed on the backside surface of the interface die (see [0049]), a third dielectric layer (dielectric layer 236) disposed on the frontside surface of the interface die, wherein the third dielectric layer includes an altered surface (top surface of dielectric layer 236 being altered dues to the process of deposition UBM layer 242 and terminals 244 through CVD, PVD or ALD) opposite the frontside surface of the interface die, and a redistribution layer (UBM layer 242, vias and metallization layers 238) disposed on the third dielectric layer and above the frontside surface of the interface die, wherein hybrid bonds (directly bonded between contacts 226 and 232 and between two dielectric materials 222 and 228) are disposed between the frontside surface of the semiconductor die and the backside surface of the interface die (see Fig. 2B and [0036-0037]). SU fails to disclose the altered surface of the third dielectric done by mechanically. However, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe , 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 1 is directed to a device, the method of forming the altered surface is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…altered by mechanically” stated in claim 1 has not been given any patentable weight. MPEP 2113 [R-1]. Regarding claim 2 , SU discloses the semiconductor device assembly of claim 1, wherein the hybrid bonds include a metal-metal bond directly (between contacts 226 and 232 (and a dielectric-dielectric bond (between two dielectric materials 222 and 228) (see Fig. 2B and [0036-0037], [0122]). Regarding claim 3 , SU discloses the semiconductor device assembly of claim 2, wherein the plurality of bond pads of the semiconductor die and the interface die are made of materials including at least one of copper, silver, gold, nickel, tungsten, or a combination thereof (see [0047] and [0049]). Regarding claim 4 , SU discloses the semiconductor device assembly of claim 2, wherein the metal-metal bond is a bond formed between the first plurality of bond pads of the semiconductor die and the second plurality of bond pads of the interface die, and wherein the metal-metal bond is gap free (see Fig. 2B and [0122]). SU fails to disclose the metal-metal bond is a diffusion bond. However, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe , 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 4 is directed to a device, the method of forming the metal-metal bond is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…diffusion bond” stated in claim 4 has not been given any patentable weight. MPEP 2113 [R-1]. Regarding claim 5 , SU discloses the semiconductor device assembly of claim 2, wherein the dielectric- dielectric bond is a covalent bond (bond between 2 silicon oxide material of layers 222 and 228) formed between the first dielectric layer of the semiconductor die and the second dielectric layer of the interface die, and wherein the dielectric-dielectric bond is gap free (see Fig. 2B and [0046], [0048]). Regarding claim 6 , SU discloses the semiconductor device assembly of claim 5, wherein the first and the second dielectric layers are made of at least one of silicon oxide and silicon nitride (see Fig. 2B and [0046], [0048]). Regarding claim 7 , SU discloses the semiconductor device assembly of claim 5, further comprising a micro bump (conductive terminals 244) electrically connected to the redistribution layer of the interface die and disposed on the front surface of the interface die (see Fig. 2B and [0055]) . 07-15-03-aia AIA Claim s 1-6 and 8 and are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHUANG et al. (Pub. No.: US 2024/0153895 A1), hereinafter as CHUANG . Regarding claim 1 , CHUANG discloses a semiconductor device assembly in Fig. 2, comprising: a semiconductor die (die 202) having a frontside surface (top surface of region 210), a first plurality of bond pads (plurality of contacts 224) at the frontside surface and a first dielectric layer (one dielectric layer 220 of region 210) at the frontside surface (see [0034-0036], [0038-0039]); and an interface die (device region 212) having a frontside surface (top surface of device region 212) and a backside surface (bottom surface of device region 212) (see [0036]), the interface die including: a second plurality of bond pads (plurality of contacts 230) and a second dielectric layer (dielectric layer 226) disposed on the backside surface of the interface die (see [0041]), a third dielectric layer (combination of layers 240, 242, 234, 246a-246b, 248a-b and 250a) disposed on the frontside surface of the interface die, wherein the third dielectric layer includes a mechanically altered surface (top surface of layer 250a being planarized in CMP operation) opposite the frontside surface of the interface die (see [0046-0047], [0043], [0050] and [0091]), and a redistribution layer (conductive terminal 244) disposed on the third dielectric layer and above the frontside surface of the interface die, wherein hybrid bonds are disposed between the frontside surface of the semiconductor die and the backside surface of the interface die (bond between contacts 224 and 230, and bond between dielectric layers 226 and 220) (see [0035-0036] and [0080]). It should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe , 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 1 is directed to a device, the method of forming the altered surface is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…altered by mechanically” stated in claim 1 has not been given any patentable weight. MPEP 2113 [R-1]. Regarding claim 2 , CHUANG discloses the semiconductor device assembly of claim 1, wherein the hybrid bonds include a metal-metal bond directly (between contacts 230 and 224) and a dielectric-dielectric bond (between two dielectric materials 220 and 226) (see Fig. 2 and [0038-0041]). Regarding claim 3 , CHUANG discloses the semiconductor device assembly of claim 2, wherein the plurality of bond pads of the semiconductor die and the interface die are made of materials including at least one of copper, silver, gold, nickel, tungsten, or a combination thereof (see [0039] and [0041]). Regarding claim 4 , CHUANG discloses the semiconductor device assembly of claim 2, wherein the metal-metal bond is a bond formed between the first plurality of bond pads of the semiconductor die and the second plurality of bond pads of the interface die, and wherein the metal-metal bond is gap free (see Fig. 2 and [0028] and [0080]). CHUANG fails to disclose the metal-metal bond is a diffusion bond. However, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe , 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 4 is directed to a device, the method of forming the metal-metal bond is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…diffusion bond” stated in claim 4 has not been given any patentable weight. MPEP 2113 [R-1]. Regarding claim 5 , CHUANG discloses the semiconductor device assembly of claim 2, wherein the dielectric- dielectric bond is a covalent bond (bond between 2 silicon oxide material of layers 220 and 226) formed between the first dielectric layer of the semiconductor die and the second dielectric layer of the interface die, and wherein the dielectric-dielectric bond is gap free (see Fig. 2 and [0038], [0040]). Regarding claim 6 , CHUANG discloses the semiconductor device assembly of claim 5, wherein the first and the second dielectric layers are made of at least one of silicon oxide and silicon nitride (see Fig. 2 and [0038], [0040]). Regarding claim 8 , CHUANG discloses the semiconductor device assembly of claim 1, further comprising a molding compound (polymer layer 252) encapsulating the semiconductor die (indirectly encapsulate die 202), wherein the molding compound comprises a polymer (see [0050-0051]) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: a. Determining the scope and contents of the prior art. b. Ascertaining the differences between the prior art and the claims at issue. c. Resolving the level of ordinary skill in the pertinent art. d. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-22-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over CHUANG et al. (Pub. No.: US 2024/0153895 A1), hereinafter as CHUANG , as applied to claim 1 above, and further in view of Chen et al. (US Patent No.: 2020/0235073 A1), hereinafter as Chen . Regarding claim 9 , CHUANG discloses the semiconductor device assembly of claim 1, further comprising a dielectric layer (layer 248b) disposed on the front surface of the interface die, the polyimide layer encapsulating the third dielectric layer and the redistribution layer of the interface die (see Fig. 2 and [0051]), but fails to disclose further comprising the dielectric layer is made of polyimide layer. Chen discloses a semiconductor device assembly in Fig. 3F comprising a polyimide layer (layer 250) disposed on a front surface of an interface die (die 200) (see [0048], [0059]), the polyimide layer encapsulating a third dielectric layer (dielectric layer 218/216a) and a redistribution layer (pad 252) of the interface die (see [0058-0059]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the polyimide material of Chen into the semiconductor device assembly of CHUANG for making the dielectric layer on the front surface of the interface die because the teaching of CHUANG discloses polyimide can be used to substitute for silicon oxide for forming an effective and reliable encapsulation layer over the package chip . 07-22-aia AIA Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over CHUANG et al. (Pub. No.: US 2024/0153895 A1), hereinafter as CHUANG , as applied to claim 1 above, and further in view of Wang et al. (US Patent No.: 2019/0333846 A1), hereinafter as Wang . Regarding claim 10 , CHUANG discloses the semiconductor device assembly of claim 1, but fails to disclose wherein the mechanically altered surface of the third dielectric layer includes a dishing, zigzag profiles, polishing marks, and / or whorls. Wang discloses a semiconductor device assembly comprising a mechanically altered surface of a third dielectric layer (dielectric layer 26) comprising polishing marks after CMP process (see Figs. 3-4 and [0021]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the mechanically altered surface of the third dielectric of CHUANG having polishing marks dues to CMP process as shown in Wang’s semiconductor device because dues to grinding process it is well known that the ground surface of dielectric layer will left with polishing marks . 07-21-aia AIA Claim s 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over CHUANG et al. (Pub. No.: US 2024/0153895 A1), hereinafter as CHUANG, and further in view of Wang et al. (US Patent No.: 2019/0333846 A1), hereinafter as Wang . Regarding claim 11 , CHUANG discloses a semiconductor device assembly in Fig. 2, comprising: a semiconductor die (die 202) having a first surface (top surface of one layer 220), a first plurality of bond pads (plurality of contacts 224) and a first dielectric layer (an uppermost dielectric layer 220 of region 210) at the first side (see [0034-0036], [0038-0039]); and an interface die (device region 212) having a first side (bottom surface of device region 212) and a second side (top surface of device region 212) (see [0036]), the interface die including: a second plurality of bond pads (plurality of contacts 230) and a second dielectric layer (dielectric layer 226) disposed on the first side the interface die (see [0041]), a third dielectric layer (combination of layers 240, 242, 234, 246a-246b, 248a-b and 250a) disposed on the second side of the interface die (see [0046-0047], [0043], [0050] and [0091]), and wherein hybrid bonds are disposed between the first side of the semiconductor die and the first side the interface die (bond between contacts 224 and 230, and bond between dielectric layers 226 and 220) (see [0035-0036] and [0080]). CHUANG fails to disclose wherein the third dielectric layer includes a plurality of polishing marks opposite the first side of the interface die. Wang discloses a semiconductor device assembly comprising a mechanically altered surface of a third dielectric layer (dielectric layer 26) comprising polishing marks after CMP process (see Figs. 3-4 and [0021]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the mechanically altered surface of the third dielectric of CHUANG having polishing marks opposite the first side of interface die dues to CMP process as shown in Wang’s semiconductor device because dues to grinding process it is well known that the ground surface of dielectric layer will left with polishing marks. Regarding claim 12 , the combination of CHUANG and Wang discloses the semiconductor device assembly of claim 11, wherein the hybrid bonds include gap free metal-metal bond between the first and the second plurality of bond pads (see CHUANG, Fig. 2 and [0028] and [0080]), and gap free dielectric-dielectric covalent bond (bond between 2 silicon oxide material of layers 220 and 226) between the first dielectric layer of the semiconductor die and the second dielectric layer of the interface die. (see CHUANG, Fig. 2 and [0038], [0040]). CHUANG fails to disclose the metal-metal bond is a diffusion bond. However, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe , 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 12 is directed to a device, the method of forming the metal-metal bond is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…diffusion bond” stated in claim 12 has not been given any patentable weight. MPEP 2113 [R-1]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov) . The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CUONG B NGUYEN/Primary Examiner, Art Unit 2818 Application/Control Number: 18/406,068 Page 2 Art Unit: 2818 Application/Control Number: 18/406,068 Page 3 Art Unit: 2818 Application/Control Number: 18/406,068 Page 4 Art Unit: 2818 Application/Control Number: 18/406,068 Page 5 Art Unit: 2818 Application/Control Number: 18/406,068 Page 6 Art Unit: 2818 Application/Control Number: 18/406,068 Page 7 Art Unit: 2818 Application/Control Number: 18/406,068 Page 8 Art Unit: 2818 Application/Control Number: 18/406,068 Page 9 Art Unit: 2818 Application/Control Number: 18/406,068 Page 11 Art Unit: 2818 Application/Control Number: 18/406,068 Page 12 Art Unit: 2818 Application/Control Number: 18/406,068 Page 13 Art Unit: 2818
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