Prosecution Insights
Last updated: October 04, 2026
Application No. 18/406,220

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

Non-Final OA §102§103
Filed
Jan 08, 2024
Priority
Dec 15, 2023 — TW 112148958
Examiner
CRITE, ANTONIO B
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Powerchip Semiconductor Manufacturing Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
376 granted / 461 resolved
+13.6% vs TC avg
Minimal -13% lift
Without
With
+-13.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
27 currently pending
Career history
484
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
54.1%
+14.1% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
19.6%
-20.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 461 resolved cases

Office Action

§102 §103
DETAILED ACTION This Action is responsive to the Restriction/Election Response filed on 08/02/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant’s election of Invention I, drawn to a semiconductor device, in the reply filed on 08/02/2026 is acknowledged and entered into the record. Because Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 11-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, drawn to a method for forming a semiconductor device, there being no allowable generic or linking claim. Brief Description of the Drawings The Brief Description of the Drawings is objected to under 37 C.F.R. 1.74. When there are drawings, there shall be a brief description of the several views of the drawings and the detailed description of the invention shall refer to the different views by specifying the numbers of the figures and to the different parts by use of reference letters or numerals (preferably the latter). The Brief Description of the Drawings must provide a brief description of the several views of the drawings. Paragraph 0027 on Page 6, in the disclosure as originally filed, does not provide a brief description of each of the cross-sectional views of illustrating a method of forming semiconductor device for FIG. 1 – FIG. 10. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Trivedi (US 2021/0184051). Regarding claim 1, Trivedi (see, e.g., FIG. 1A – FIG. 1C) discloses a semiconductor device, comprising: a substrate 101 comprising a first active region e.g., region left of break 104 in 101 and a second active region e.g., region right of break 104 in 101 defined by an element isolation structure 103 (Para 0021-Para 0023, Para 0035); a first element 172A disposed in the first active region e.g., region left of break 104 in 101 and comprising a first gate structure 130 (left of break 104), 112A, and the first gate structure 130 (left of break 104), 112A comprising a first gate electrode 130 (left of break 104) and a first gate dielectric layer 112A disposed between the substrate 101 and the first gate electrode 130 (left of break 104) (Para 0024, Para 0025); and a second element 172B (also labeled as 172E) disposed in the second active region e.g., region right of break 104 in 101 and comprising a second gate structure 130 (right of break 104), 112B (also labeled as 112E), and the second gate structure 130 (right of break 104), 112B (also labeled as 112E) comprising a second gate electrode 130 (right of break 104) and a second gate dielectric layer 112B (also labeled as 112E) disposed between the substrate 101 and the second gate electrode 130 (right of break 104), wherein the first gate dielectric layer 112A comprises a first portion e.g., horizontal portion of 112A in contact with the substrate 101 and a second portion e.g., vertical portion of 112A protruding from the first portion e.g., horizontal portion of 112A in a vertical direction, a thickness TA of the first portion e.g., horizontal portion of 112A in the vertical direction is smaller than a thickness e.g., thickness of 112B (also labeled as 112E) of the second gate dielectric layer 112B (also labeled as 112E) in the vertical direction, and a top surface of the second portion e.g., top surface of vertical portion of 112A is at a level height identical to a top surface of the second gate dielectric layer e.g., top surface of 112B (also labeled as 112E) (Para 0024, Para 0026, Para 0028-Para 0029). Regarding claim 4, Trivedi (see, e.g., FIG. 1A – FIG. 1C) teaches the semiconductor device of claim 1, wherein a horizontal area of the second element 172B (also labeled as 172E) is greater than a horizontal area of the first element 172A. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Trivedi (US 2021/0184051), in view of Hwang (US 2025/0081599). Regarding claim 2, although Trivedi shows substantial features of the claimed invention, Trivedi fails to expressly teach the semiconductor device of claim 1, wherein a top surface of the first gate electrode comprises a recess recessed toward the substrate. Regarding “a top surface of the first gate electrode comprises a recess recessed toward the substrate,” it would have been an obvious matter of design choice to adjust the shape of the gate electrode to include a recess recessed toward the substrate as taught by Hwang (see, e.g., FIG. 3, FIG. 5, FIG. 6) who teaches a gate electrode 220 with a recess recessed toward the substrate 100 and a gate electrode 120 with a flat surface (Para 0065, Para 0066). Moreover, a change in shape is a matter of design choice, which a person within the level of ordinary skill in the art would have found to be obvious absent persuasive evidence that the particular configuration of the claimed top surface of the first gate electrode comprising a recess recessed toward the substrate was significant, and a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Regarding claim 3, the combination of Trivedi (see, e.g., FIG. 1A – FIG. 1C) / Hwang (see, e.g., FIG. 3; FIG. 6) teaches the semiconductor device of claim 2, wherein the top surface of the first gate electrode e.g., top surface of 130 (left of break 104) (as taught by Trivedi, modified to include a recess as taught by Hwang) in a region 220R2 (as taught by Hwang) other than the recess e.g., region 220R1 that includes recess (as taught by Hwang) is at a level height identical to a top surface of the second gate electrode e.g., top surface of 130 (right of break 104). Allowable Subject Matter Claims 5-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jan 08, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
68%
With Interview (-13.4%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 461 resolved cases by this examiner. Grant probability derived from career allowance rate.

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