Prosecution Insights
Last updated: April 19, 2026
Application No. 18/406,222

Electronic device and manufacturing method thereof

Non-Final OA §103
Filed
Jan 08, 2024
Examiner
MAIGA, SIDI MOHAMED
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
85%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
22 granted / 29 resolved
+7.9% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
32 currently pending
Career history
61
Total Applications
across all art units

Statute-Specific Performance

§103
64.2%
+24.2% vs TC avg
§102
28.5%
-11.5% vs TC avg
§112
6.6%
-33.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 29 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Invention I in the reply filed on 09/30/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8 - 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIWANAMI et al. (US 20140360765 A1, “KIWANAMI”) in view of KIM et al. (US 20220052080 A1, “KIM”) Regarding claim 8, KIWANAMI discloses (Fig. 1, 7A, 7B) an electronic device (10) comprising: a first substrate; a second substrate; an adhesive layer arranged between the first substrate and the second substrate (See annotated figure below); and a lateral wiring arranged on the side surface of the first substrate and the side surface of the adhesive layer, wherein the lateral wiring having a first portion and a second portion (See annotated figure below); wherein the first portion at least partially overlaps the adhesive layer, and the second portion overlaps the side surface of the first substrate, and the first portion and the second portion respectively have a first edge and a second edge extending along a first direction, the first edge and the second edge are separated from each other, and the first direction is the arrangement direction of the first substrate and the second substrate (See annotated figure below). PNG media_image1.png 517 1038 media_image1.png Greyscale KIWANAMI is silent on the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer. However, KIM (Fig. 4A-B, 12) discloses the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer (See Fig. 4A). KIWANAMI and KIM are both considered to be analogous to the claimed invention because they are in the same field of electronic device. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified KIWANAMI to incorporate the teachings of KIM and provide the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer (See Fig. 4A). Doing so would improve wiring density, connection reliability and enhances structural stability and durability (para [0096] and [0139]). Regarding claim 9, KIWANAMI in view of KIM discloses the electronic device according to claim 8, wherein KIWANAMI further discloses that the first portion (39 made of copper) and the second portion(57 made of copper alloy) of the lateral wiring comprise different materials (para [0034] and [0049]). Regarding claim 10, KIWANAMI in view of KIM discloses the electronic device according to claim 8, wherein KIWANAMI further discloses that the first edge and the second edge are separated from each other by a first pitch, and the first pitch is between 5 and 15 microns (The first pitch can be defined as (the diameter of 39 minus the diameter of 57) divided by 2. From para [0034] and [0049] d39 is from 50 to 100 microns and d57 is from 50 to 75. If d39 = 100 and d57 = 75, the first pitch will be 12.5). . Regarding claim 11, KIWANAMI in view of KIM discloses the electronic device according to claim 10, wherein KIWANAMI further discloses the first portion and the second portion respectively have a third edge and a fourth edge extending along the first direction, the first edge is opposite to the third edge, the second edge is opposite to the fourth edge, and the third edge and the fourth edge are separated from each other (See annotated figure below). PNG media_image2.png 517 838 media_image2.png Greyscale Regarding claim 12, KIWANAMI in view of KIM discloses the electronic device according to claim 11, wherein KIWANAMI further discloses the third edge and the fourth edge are separated from each other by a second pitch, and the second pitch is between 5 and 15 microns (The second pitch can be defined as (the diameter of 39 minus the diameter of 57) divided by 2. From para [0034] and [0049] d39 is from 50 to 100 microns and d57 is from 50 to 75. If d39 = 100 and d57 = 75, the second pitch will be 12.5). . Regarding claim 13, KIWANAMI in view of KIM discloses the electronic device according to claim 12, wherein the difference between the first pitch and the second pitch is greater than or equal to zero (The first pitch and the second pitch are equal, so the difference is zero). Regarding claim 14, KIWANAMI in view of KIM discloses the electronic device according to claim 8, wherein KIWANAMI further discloses the first portion is separated from the edge of the first substrate far from the second substrate by a first distance greater than 80 microns (the thickness of each insulating layer 51, 53 and 55 can be up to 35 microns, which combined is more than 80 microns). Regarding claim 15, KIWANAMI in view of KIM discloses the electronic device according to claim 8, wherein KIWANAMI further discloses the first portion is separated from the edge of the second substrate far from the second substrate by a second distance greater than 80 microns (the thickness of each insulating layer 51, 53 and 55 can be up to 35 microns, which combined is more than 80 microns). Regarding claim 16, KIWANAMI in view of KIM discloses the electronic device of claim 8, wherein KIWANAMI further discloses a length of the first portion is greater than 600 microns (See para [0031]). Regarding claim 17, KIWANAMI discloses (Fig. 1, 7A, 7B) an electronic device comprising: a first substrate; a second substrate; an adhesive layer arranged between the first substrate and the second substrate (See annotated figure below); and a lateral wiring arranged on the side surface of the first substrate and the side surface of the adhesive layer, the lateral wiring having a first portion and a second portion; wherein the first portion at least partially overlaps the adhesive layer, and the second portion overlaps a part of the side surface of the first substrate (See annotated figure below), and the region of the side surface of the first substrate without the lateral wiring has a third region adjacent to the first portion and a fourth region adjacent to the second portion, and there is a height difference between the third region and the fourth region. PNG media_image1.png 517 1038 media_image1.png Greyscale KIWANAMI is silent on the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer, and the region of the side surface of the first substrate without the lateral wiring has a third region adjacent to the first portion and a fourth region adjacent to the second portion, and there is a height difference between the third region and the fourth region. However, KIM (Fig. 4A-B, 12) discloses the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer (See Fig. 4A), and the region of the side surface of the first substrate without the lateral wiring has a third region (G1) adjacent to the first portion and a fourth region (G2) adjacent to the second portion, and there is a height difference between the third region and the fourth region (See para [0099]). KIWANAMI and KIM are both considered to be analogous to the claimed invention because they are in the same field of electronic device. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified KIWANAMI to incorporate the teachings of KIM and provide the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer (See Fig. 4A), and the region of the side surface of the first substrate without the lateral wiring has a third region (G1) adjacent to the first portion and a fourth region (G2) adjacent to the second portion, and there is a height difference between the third region and the fourth region (See para [0099]). Doing so would improve wiring density, connection reliability and enhances structural stability and durability (para [0096] and [0139]). Claim(s) 8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over OSAWA et al. (US 20180031933 A1, “OSAWA”) in view of KIM et al. (US 20220052080 A1, “KIM”) Regarding claim 8, OSAWA discloses (Fig. 6, 10, 12) an electronic device comprising: a first substrate; a second substrate; an adhesive layer (SE) arranged between the first substrate and the second substrate (See annotated figure below); and a lateral wiring arranged on the side surface of the first substrate and the side surface of the adhesive layer, wherein the lateral wiring having a first portion and a second portion (See annotated figure below); wherein the first portion at least partially overlaps the adhesive layer, and the second portion overlaps the side surface of the first substrate, and the first portion and the second portion respectively have a first edge and a second edge extending along a first direction, the first edge and the second edge are separated from each other, and the first direction is the arrangement direction of the first substrate and the second substrate (See annotated figure below). PNG media_image3.png 566 1209 media_image3.png Greyscale OSAWA is silent on the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer. However, KIM (Fig. 4A-B, 12) discloses the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer (See Fig. 4A). OSAWA and KIM are both considered to be analogous to the claimed invention because they are in the same field of electronic device. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified OSAWA to incorporate the teachings of KIM and provide the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer (See Fig. 4A). Doing so would improve wiring density, connection reliability and enhances structural stability and durability (para [0096] and [0139]). Regarding claim 17, OSAWA discloses (Fig. 6, 10, 12) an electronic device comprising: a first substrate; a second substrate; an adhesive layer (SE) arranged between the first substrate and the second substrate (See annotated figure below); and a lateral wiring arranged on the side surface of the first substrate and the side surface of the adhesive layer, the lateral wiring having a first portion and a second portion; wherein the first portion at least partially overlaps the adhesive layer, and the second portion overlaps a part of the side surface of the first substrate (See annotated figure below), and the region of the side surface of the first substrate without the lateral wiring has a third region adjacent to the first portion and a fourth region adjacent to the second portion, and there is a height difference between the third region and the fourth region. PNG media_image3.png 566 1209 media_image3.png Greyscale OSAWA is silent on the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer, and the region of the side surface of the first substrate without the lateral wiring has a third region adjacent to the first portion and a fourth region adjacent to the second portion, and there is a height difference between the third region and the fourth region. However, KIM (Fig. 4A-B, 12) discloses the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer (See Fig. 4A), and the region of the side surface of the first substrate without the lateral wiring has a third region (G1) adjacent to the first portion and a fourth region (G2) adjacent to the second portion, and there is a height difference between the third region and the fourth region (See para [0099]). OSAWA and KIM are both considered to be analogous to the claimed invention because they are in the same field of electronic device. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified OSAWA to incorporate the teachings of KIM and provide the wiring being arranged on the side surface of the first substrate and the side surface of the adhesive layer (See Fig. 4A), and the region of the side surface of the first substrate without the lateral wiring has a third region (G1) adjacent to the first portion and a fourth region (G2) adjacent to the second portion, and there is a height difference between the third region and the fourth region (See para [0099]). Doing so would improve wiring density, connection reliability and enhances structural stability and durability (para [0096] and [0139]). Allowable Subject Matter Claim 18 - 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIDI M MAIGA/Examiner, Art Unit 2847 /STANLEY TSO/ Primary Examiner, Art Unit 2847
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Prosecution Timeline

Jan 08, 2024
Application Filed
Jan 10, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12586995
ELECTRICAL APPARATUS AND PLUG
2y 5m to grant Granted Mar 24, 2026
Patent 12588142
HIGH-FREQUENCY ELECTRONIC COMPONENT
2y 5m to grant Granted Mar 24, 2026
Patent 12568584
WIRING BOARD
2y 5m to grant Granted Mar 03, 2026
Patent 12563665
INSULATING CIRCUIT BOARD AND SEMICONDUCTOR DEVICE IN WHICH SAME IS USED
2y 5m to grant Granted Feb 24, 2026
Patent 12550257
WIRING SUBSTRATE
2y 5m to grant Granted Feb 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
85%
With Interview (+9.4%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 29 resolved cases by this examiner. Grant probability derived from career allow rate.

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