DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-10, in the reply filed on 23 March 2026 is acknowledged.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 23 March 2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Information disclosure statement filed 8 January 2024 has been fully considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: BONDED SEMICONDUCTOR WAFERS COMPRISING GROUNDED BURIED OXIDE LAYER.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US Patent Application Publication 2022/0415930, hereinafter Chuang ‘930) in view of Lan et al. (US Patent Application Publication 2016/0093591, hereinafter Lan ‘591).
With respect to claim 1, Chuang ‘930 teaches (FIG. 1) a semiconductor device substantially as claimed, comprising:
a first wafer (105) ([0022]), comprising:
a first substrate (142) ([0015]); and
a first interconnection layer (144) disposed on the first substrate (142) ([0022]);
a second wafer (104 and 106) ([0015, 0017]), comprising:
a second substrate (104) comprising a buried layer (110) and a semiconductor layer (114) disposed on the buried layer ([0015]); and
a second interconnection layer (106) disposed on the semiconductor layer (114), wherein the second interconnection layer is bonded with the first interconnection layer (144) ([0017]);
a dielectric layer (126) disposed on the buried layer (110) ([0017]); and
a first metal structure (pair of legs of 302) disposed through the dielectric layer (126), wherein an end of the first metal structure physically contacts the buried layer (110), and the buried layer is grounded through the first metal structure ([0033]).
Thus, Chuang ‘930 is shown to teach all the features of the claim with the exception of wherein the buried layer is a buried oxide layer.
However, Lan ‘591 teaches (FIG. 20) a buried layer (400) comprising a buried oxide (BOX) layer as a basis for using bulk, thin-film SOI technology to fabricate 3D ICs ([0049, 0055]). Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the buried layer of Chuang ‘930 as a buried oxide layer as taught by Lan ‘591 as a basis for using bulk, thin-film SOI technology to fabricate 3D ICs.
With respect to claim 2, Chuang ‘930 teaches further comprising: a first metal pad (single connecting portion of 302) disposed on the dielectric layer (126); and a protective layer (128) disposed on the dielectric layer and the first metal pad, wherein the protective layer partially covers the first metal pad (the protective layer covers only the top surface of the first metal pad, and thus only “partially covers” said first metal pad), and another end of the first metal structure (pair of legs of 302) is connected with the first metal pad ([0017, 0033]).
With respect to claim 6, Chuang ‘930 teaches wherein the protective layer (128) comprises a dielectric material ([0017]).
With respect to claim 7, Chuang ‘930 teaches wherein the dielectric material (126) comprises a nitride, a plasma enhanced oxide or a combination thereof ([0032]).
With respect to claim 8, Chuang ‘930 and Lan ‘591 teach the device as described in claim 2 above, with primary reference Chuang ‘930 teaching the additional limitation wherein the first substrate (142) comprises a semiconductor layer, and the first interconnection layer (144) is disposed on the semiconductor layer of the first substrate ([0015, 0022]).
Thus, Chuang ‘930 is shown to teach all the features of the claim with the exception of wherein the first substrate comprises a buried oxide layer, the semiconductor layer disposed on the buried oxide layer.
However, Lan ‘591 teaches (FIG. 20) a first substrate (1202) comprising a buried oxide layer (SOI), the semiconductor layer disposed on the buried oxide layer as a basis for using bulk, thin-film SOI technology to fabricate 3D ICs ([0049, 0053]). Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the first substrate of Chuang ‘930 comprising a buried oxide layer, the semiconductor layer disposed on the buried oxide layer as taught by Lan ‘591 as a basis for using bulk, thin-film SOI technology to fabricate 3D ICs.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang ‘930 and Lan ‘591 as applied to claim 2 above, and further in view of Yang (US Patent Application Publication 2022/0130956, hereinafter Yang ‘956).
With respect to claim 9, Chuang ‘930 and Lan ‘591 teach the device as described in claim 2 above with the exception of the additional limitation wherein the first wafer further comprises a trap rich layer disposed on the buried oxide layer of the first substrate.
However, Yang ‘956 teaches (FIG. 1) a wafer comprising a trap rich layer (220) disposed on a buried oxide layer (120 or 230) of a substrate ([0014]) to cancel parasitic surface conduction channels in the substrate, to increase effective resistivity of the substrate, and to reduce harmonic distortion and substrate loss ([0020]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the first wafer of Chuang ‘930 and Lan ‘591 comprising a trap rich layer disposed on the buried oxide layer of the first substrate as taught by Yang ‘956 to cancel parasitic surface conduction channels in the substrate, to increase effective resistivity of the substrate, and to reduce harmonic distortion and substrate loss.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang ‘930, Lan ‘591, and Yang ‘956 as applied to claim 9 above, and further in view of Hou et al. (US Patent Application Publication 2025/0142958, hereinafter Hou ‘958).
With respect to claim 10, Chuang ‘930, Lan ‘591, and Yang ‘956 teach the device as described in claim 9 above, with primary reference Chuang ‘930 teaching the additional limitation further comprising: a second metal pad (any other metal pad formed in dielectric layer 126) disposed on the dielectric layer (126), wherein the protective layer (128) partially covers the second metal pad (the protective layer covers only the top surface of the second metal pad, and thus only “partially covers” said second metal pad).
Thus, Chuang ‘930 is shown to teach all the features of the claim with the exception of a third metal structure disposed through the buried oxide layer and the semiconductor layer of the first substrate, wherein an end of the third metal structure physically contacts the trap rich layer, and another end of the third metal structure is connected with the second metal pad.
However, Hou ‘958 teaches (FIG. 4) a third metal structure (DV) disposed through a buried oxide layer (202b) and a semiconductor layer (203) of a first substrate, wherein an end of the third metal structure physically contacts a trap rich layer (202a), and another end of the third metal structure is connected with a second metal pad (430) to provide electrical connection to said trap rich layer ([0034, 0038]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Chaung ‘930, Lan ‘591, and Yang ‘956 further comprising a third metal structure disposed through the buried oxide layer and the semiconductor layer of the first substrate, wherein an end of the third metal structure physically contacts the trap rich layer, and another end of the third metal structure is connected with the second metal pad as taught by Hou ‘958 to provide electrical connection to said trap rich layer.
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the semiconductor device of claim 3 in the combination of limitations as claimed, noting particularly the limitation, “wherein the second wafer further comprises a diode disposed in the semiconductor layer, and the diode is electrically connected with the first metal pad.” Chuang ‘930 represents the closest prior art of record. See the 35 U.S.C. 103 rejection of claims 1 and 2 above. However, Chuang ‘930 is silent to a diode disposed in the semiconductor layer and electrically connected with the first metal pad as claimed. Claims 4 and 5 are indicated as containing allowable subject matter based merely upon their dependency from claim 3 indicated as containing allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Shen et al. (US Patent Application Publication 2020/0135617); Chen et al. (US Patent Application Publication 2021/0082873); Kao et al. (US Patent Application Publication 2021/0391302); Chen et al. (US Patent Application Publication 2024/0371758); and Chen et al. (US Patent Application Publication 2024/0387418); teach bonding semiconductor wafers in 3D architecture.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893