Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, these claims are drafted as if they depend on claims 12-13, but claims 10-11 are the actual dependency that is written. To perform compact prosecution, claims 13-14 and 16-21 will be interpreted as if they are drafted to rely on claim 12. To perform compact prosecution, claim 15 will be interpreted as if it depends on claim 13.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(d)
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 13-21 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Specifically, these claims depend on claims 10 and 11, which are a method claims. However, claims 13-21 are claiming a medium, which is short for the non-transitory computer readable medium claimed in claim 12. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12, 16, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Spice Circuit Reduction for Speeding Up Simulation and Verification” (2019-Yin)
With respect to claim 12, Yin teaches A non-transitory computer-readable medium storing program instructions executable by a processing device, causing the processing device to perform operations comprising (computer executing Python, (see [Abstract paragraph 3 line 1]; specifically instructions shown on the right side of FIG. 1.1, [page 2]; where a computer is implied by every being coded in Python [Abstract paragraph 3 line 1]; and notes such as being aware of processor memory overflow, [page 42 paragraph 1 line 14]): reading a netlist of an electronic circuit (see box labeled "original netlist" in FIG. 1.1, [page 2]; a discussion of circuit netlists is given in section 2.1.2.1, [page 11 paragraphs 3-5]); and providing, by the processing device (where a computer is implied by every being coded in Python [Abstract paragraph 3 line 1]; and notes such as being aware of processor memory overflow, [page 42 paragraph 1 line 14]), simulator optimization such that two or more devices sharing one or more device parameters are combined and simulated as a single optimized device (see box labeled "reduced netlist" and box labeled "simulator (fast)" in FIG. 1.1, [page 2]; a simulation requires the act of calculating, but the simulator is the set of equations required for the simulation, see “Simulators use complex device models to simulate the whole circuit, including active parts and inactive parts. Some inactive parts of the circuit do influence the active parts of the circuit somehow, and the influence comes from the resistance and capacitance characteristics of transistors. However, the simulator will perform a very complicated calculation based on a corresponding transistor model library. This process is very time-consuming and memory-consuming since the intensive computation can generate a huge amount of data. This can be solved if the inactive part of the circuit is replaced by equivalent resistance and capacitance models”, [page 12 paragraph 5]-[page 13 paragraph 1]; the details of netlist reduction are provided in Chapter 3, [page 21-35]; a very clear example is shown in FIGS. 3.5 and 3.6, where a bitcell and surrounding bitcells in FIG. 3.5 are replaced by an equivalent model in FIG. 3.6, [page 25]; for explanation see section labeled “3.1.3 Add equivalent model of bitcell”, [page 24], specifically, “To compensate for the capacitance loss, a pure capacitance model shown in Figure. 3.6 is used. The capacitors which connect to one net will be combined together in the end, [page 24 paragraph 2 lines 1-3]).
With respect to claim 16, Yin teaches all of the limitations of claim 12, as noted above. Yin further teaches mapping two or more devices in the electronic circuit that share the same netlist parametric expressions (One cluster object contains all the information of the transistors that have been classified into this cluster, [page 30 paragraph 1 lines 1-2]).
With respect to claim 21, Yin teaches all of the limitations of claim 12, as noted above. Yin further teaches: combining a group of memory cells in the electronic circuit to form the optimized device (this is the process of netlist reduction, see box labeled "reduction engine" in FIG. 1.1, [page 2]; the details of netlist reduction are provided in Chapter 3, [page 21-35]; a very clear example is shown in FIGS. 3.5 and 3.6, where a bitcell and surrounding bitcells in FIG. 3.5 are replaced by an equivalent model in FIG. 3.6, [page 25]; for explanation see section labeled “3.1.3 Add equivalent model of bitcell”, [page 24], specifically, “To compensate for the capacitance loss, a pure capacitance model shown in Figure. 3.6 is used. The capacitors which connect to one net will be combined together in the end, [page 24 paragraph 2 lines 1-3]); and applying a variation to the optimized device (after netlist reduction is simulator running a simulation as shown in FIG. 1.1, [page 2]; where simulation includes testing SRAM corners in a Monte Carlo simulation, [Abstract paragraph 2 lines 7-12], and Monte Carlo by definition applies variation to what is being simulated (in this case the optimized device)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-10, 13, 15, 17-20, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Spice Circuit Reduction for Speeding Up Simulation and Verification” (2019-Yin) in view of “Efficient Smart Sampling based Full-Chip Leakage Analysis for Intra-Die Variation Considering State Dependence” (2009-Veetil)
With respect to claim 1, Yin teaches A method for performing a Monte Carlo simulation of an electronic circuit, the method comprising (see FIG. 1.1, “Simulation flow overview showing the application of the netlist reduction engine. The reduction process speeding up the simulation is shown inside a dashed square”, [page 2]; the focus of the thesis is on netlist reduction, which results in speeding up any future simulation, as discussed in the Abstract: “Unfortunately, due to the huge size of SRAM, it is unfeasible to simulate the whole SRAM, since it would take in the order of months to perform simulations. Also, a typical SRAM needs to be run for different corners, which is performed by Monte Carlo simulations, which is even more computationally intensive. Tackling these issues is the key focus of this thesis”, [Abstract paragraph 2 lines 7-12]): receiving a netlist of the electronic circuit (see box labeled "original netlist" in FIG. 1.1, [page 2]; a discussion of circuit netlists is given in section 2.1.2.1, [page 11 paragraphs 3-5]); determining an optimized device based on combining two or more devices sharing one or more device parameters in the netlist of the electronic circuit (this is the process of netlist reduction, see box labeled "reduction engine" in FIG. 1.1, [page 2]; the details of netlist reduction are provided in Chapter 3, [page 21-35]; a very clear example is shown in FIGS. 3.5 and 3.6, where a bitcell and surrounding bitcells in FIG. 3.5 are replaced by an equivalent model in FIG. 3.6, [page 25]; for explanation see section labeled “3.1.3 Add equivalent model of bitcell”, [page 24], specifically, “To compensate for the capacitance loss, a pure capacitance model shown in Figure. 3.6 is used. The capacitors which connect to one net will be combined together in the end, [page 24 paragraph 2 lines 1-3]); generating a netlist parametric expression for the optimized device (see box labeled "reduced netlist" and box labeled "simulator (fast)" in FIG. 1.1, [page 2]; a simulation requires the act of calculating, but the simulator is the set of equations required for the simulation, see “Simulators use complex device models to simulate the whole circuit, including active parts and inactive parts. Some inactive parts of the circuit do influence the active parts of the circuit somehow, and the influence comes from the resistance and capacitance characteristics of transistors. However, the simulator will perform a very complicated calculation based on a corresponding transistor model library. This process is very time-consuming and memory-consuming since the intensive computation can generate a huge amount of data. This can be solved if the inactive part of the circuit is replaced by equivalent resistance and capacitance models”, [page 12 paragraph 5]-[page 13 paragraph 1]; where example RC model equations are provided in eq. (2.1)-(2.6), [page 16-17]; and section 3.4 describes building RC models for redundant circuits, [pages 33-34])... by a processing device,... (where a computer is implied by every being coded in Python [Abstract paragraph 3 line 1]; and notes such as being aware of processor memory overflow, [page 42 paragraph 1 line 14]).
Yin does not teach and generating, by a processing device, random values for the optimized device and updating the netlist parametric expression for the optimized device based on the random values.
However, Veetil teaches and generating, ..., random values for the optimized device and updating the netlist parametric expression for the optimized device based on the random values (In the proposed approach the characterization is performed at samples generated using a Quasi Monte Carlo (QMC) based approach. In particular we use Sobol sequences in the QMC approach in this work. QMC samples refer to Sobol samples in the rest of the paper. The same process variation samples are used for characterization of all element types in the standard cell library and their states, [page 156 col 1 paragraph 5 line 5]-[page 156 col 2 paragraph 1 line 4]; see also quasi-random samples shown in FIG. 2, [page 156], samples are random values or sets of random values, and they are used to represent process variation parameters such as transistor gate length: “Therefore, each source of variation is represented by a set of random variables, one for each panel in the grid. For example, transistor gate length variation is represented by a set of random variables for all grids and the set is of multivariate normal distribution with covariance matrix R_Lg”, [page 155 col 2 paragraph 4 lines 15-19]).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin with Veetil because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin discloses a system and method for performing generic netlist reduction, that speeds up Monte Carlo simulations, (see Yin [Abstract]). Yin does not go into details about the specific Monte Carlo simulation used to generate random values. Veetil teaches:
Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy.
(Veetil [Abstract lines 9-13])
A person having skill in the art would have a reasonable expectation of successfully increasing the speed of the Monte Carlo simulation after performing netlist reduction in the system and method of Yin by modifying Yin with the Quasi Monte Carlo simulation of Veetil. Therefore, it would have been obvious to combine Yin with Veetil to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 3, Yin in view of Veetil teaches all of the limitations of claim 1, as noted above. Yin does not teach simulating the optimized device using the random values and updated netlist parametric expression.
However, Veetil teaches simulating the optimized device using the random values and updated netlist parametric expression (Our simulation results, [page 157 col 2 paragraph 3 line 1]; shown in Table 1, [page 158]; where simulation data comes from: In the proposed approach the characterization is performed at samples generated using a Quasi Monte Carlo (QMC) based approach. In particular we use Sobol sequences in the QMC approach in this work. QMC samples refer to Sobol samples in the rest of the paper. The same process variation samples are used for characterization of all element types in the standard cell library and their states, [page 156 col 1 paragraph 5 line 5]-[page 156 col 2 paragraph 1 line 4]; see also quasi-random samples shown in FIG. 2, [page 156], samples are random values or sets of random values, and they are used to represent process variation parameters such as transistor gate length: “Therefore, each source of variation is represented by a set of random variables, one for each panel in the grid. For example, transistor gate length variation is represented by a set of random variables for all grids and the set is of multivariate normal distribution with covariance matrix R_Lg”, [page 155 col 2 paragraph 4 lines 15-19]).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin with Veetil because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin discloses a system and method for performing generic netlist reduction, that speeds up Monte Carlo simulations, (see Yin [Abstract]). Yin does not go into details about the specific Monte Carlo simulation used to generate random values. Veetil teaches:
Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy.
(Veetil [Abstract lines 9-13])
A person having skill in the art would have a reasonable expectation of successfully increasing the speed of the Monte Carlo simulation after performing netlist reduction in the system and method of Yin by modifying Yin with the Quasi Monte Carlo simulation of Veetil. Therefore, it would have been obvious to combine Yin with Veetil to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 4, Yin in view of Veetil teaches all of the limitations of claim 1, as noted above. Yin does not teach storing the random values and the updated netlist parametric expression for each optimized device.
However, Veetil teaches storing the random values and the updated netlist parametric expression for each optimized device (see FIG. 3 for the main flow of the simulation, [page 156]; in step 3 the samples are generated, and step 4 is the simulation; where “The inter-die samples are precomputed during cell library characterization”, [page 156 col 2 paragraph 1 lines 2-3]; here, precomputed means calculated and stored for the simulation/computing the leakage in step 4; where this is all in the context of: In the proposed approach the characterization is performed at samples generated using a Quasi Monte Carlo (QMC) based approach. In particular we use Sobol sequences in the QMC approach in this work. QMC samples refer to Sobol samples in the rest of the paper. The same process variation samples are used for characterization of all element types in the standard cell library and their states, [page 156 col 1 paragraph 5 line 5]-[page 156 col 2 paragraph 1 line 4]; see also quasi-random samples shown in FIG. 2, [page 156], samples are random values or sets of random values, and they are used to represent process variation parameters such as transistor gate length: “Therefore, each source of variation is represented by a set of random variables, one for each panel in the grid. For example, transistor gate length variation is represented by a set of random variables for all grids and the set is of multivariate normal distribution with covariance matrix R_Lg”, [page 155 col 2 paragraph 4 lines 15-19]).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin with Veetil because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin discloses a system and method for performing generic netlist reduction, that speeds up Monte Carlo simulations, (see Yin [Abstract]). Yin does not go into details about the specific Monte Carlo simulation used to generate random values. Veetil teaches:
Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy.
(Veetil [Abstract lines 9-13])
A person having skill in the art would have a reasonable expectation of successfully increasing the speed of the Monte Carlo simulation after performing netlist reduction in the system and method of Yin by modifying Yin with the Quasi Monte Carlo simulation of Veetil. Therefore, it would have been obvious to combine Yin with Veetil to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 5, Yin in view of Veetil teaches all of the limitations of claim 1, as noted above. Yin further teaches mapping two or more devices in the electronic circuit that share the same netlist parametric expressions to the optimized device (One cluster object contains all the information of the transistors that have been classified into this cluster, [page 30 paragraph 1 lines 1-2]).
With respect to claim 6, Yin in view of Veetil teaches all of the limitations of claim 1, as noted above. Yin does not teach computing and applying variation to the optimized device.
However, Veetil teaches computing and applying variation to the optimized device (In the proposed approach the characterization is performed at samples generated using a Quasi Monte Carlo (QMC) based approach. In particular we use Sobol sequences in the QMC approach in this work. QMC samples refer to Sobol samples in the rest of the paper. The same process variation samples are used for characterization of all element types in the standard cell library and their states, [page 156 col 1 paragraph 5 line 5]-[page 156 col 2 paragraph 1 line 4]; see also quasi-random samples shown in FIG. 2, [page 156], samples are random values or sets of random values, and they are used to represent process variation parameters such as transistor gate length: “Therefore, each source of variation is represented by a set of random variables, one for each panel in the grid. For example, transistor gate length variation is represented by a set of random variables for all grids and the set is of multivariate normal distribution with covariance matrix R_Lg”, [page 155 col 2 paragraph 4 lines 15-19]).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin with Veetil because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin discloses a system and method for performing generic netlist reduction, that speeds up Monte Carlo simulations, (see Yin [Abstract]). Yin does not go into details about the specific Monte Carlo simulation used to generate random values. Veetil teaches:
Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy.
(Veetil [Abstract lines 9-13])
A person having skill in the art would have a reasonable expectation of successfully increasing the speed of the Monte Carlo simulation after performing netlist reduction in the system and method of Yin by modifying Yin with the Quasi Monte Carlo simulation of Veetil. Therefore, it would have been obvious to combine Yin with Veetil to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 7, Yin in view of Veetil teaches all of the limitations of claim 1, as noted above. Yin does not teach computing and applying the same variation to two or more devices located in two or more locations in the electronic circuit, wherein the two or more devices share one or more device parameters.
However, Veetil teaches computing and applying the same variation to two or more devices located in two or more locations in the electronic circuit, wherein the two or more devices share one or more device parameters (A given inter-die sample is assigned to every element type in the library as before and the circuit leakage is obtained by adding up the leakage values from element types as in the traditional flow, [page 156 col 2 paragraph 2 lines 3-6]; where this is all in the context of: In the proposed approach the characterization is performed at samples generated using a Quasi Monte Carlo (QMC) based approach. In particular we use Sobol sequences in the QMC approach in this work. QMC samples refer to Sobol samples in the rest of the paper. The same process variation samples are used for characterization of all element types in the standard cell library and their states, [page 156 col 1 paragraph 5 line 5]-[page 156 col 2 paragraph 1 line 4]; see also quasi-random samples shown in FIG. 2, [page 156], samples are random values or sets of random values, and they are used to represent process variation parameters such as transistor gate length: “Therefore, each source of variation is represented by a set of random variables, one for each panel in the grid. For example, transistor gate length variation is represented by a set of random variables for all grids and the set is of multivariate normal distribution with covariance matrix R_Lg”, [page 155 col 2 paragraph 4 lines 15-19]).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin with Veetil because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin discloses a system and method for performing generic netlist reduction, that speeds up Monte Carlo simulations, (see Yin [Abstract]). Yin does not go into details about the specific Monte Carlo simulation used to generate random values. Veetil teaches:
Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy.
(Veetil [Abstract lines 9-13])
A person having skill in the art would have a reasonable expectation of successfully increasing the speed of the Monte Carlo simulation after performing netlist reduction in the system and method of Yin by modifying Yin with the Quasi Monte Carlo simulation of Veetil. Therefore, it would have been obvious to combine Yin with Veetil to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 8, Yin in view of Veetil teaches all of the limitations of claim 1, as noted above. Yin does not teach computing and applying unique variations to two or more devices in the electronic circuit that are in contact.
However, Veetil teaches computing and applying unique variations to two or more devices in the electronic circuit that are in contact (this is called “intra-die variation” in the reference, see “Process variation consists of inter-die and intra-die components. In Section 3 we discussed generation of samples in the space of inter-die variation distributed according to the joint probability distribution of the variables involved. We apply intra-die variation to such a sample around the nominal and obtain a local leakage distribution for the circuit, [page 156 col 2 paragraph 4 lines 2-7]; where this is all in the context of: In the proposed approach the characterization is performed at samples generated using a Quasi Monte Carlo (QMC) based approach. In particular we use Sobol sequences in the QMC approach in this work. QMC samples refer to Sobol samples in the rest of the paper. The same process variation samples are used for characterization of all element types in the standard cell library and their states, [page 156 col 1 paragraph 5 line 5]-[page 156 col 2 paragraph 1 line 4]; see also quasi-random samples shown in FIG. 2, [page 156], samples are random values or sets of random values, and they are used to represent process variation parameters such as transistor gate length: “Therefore, each source of variation is represented by a set of random variables, one for each panel in the grid. For example, transistor gate length variation is represented by a set of random variables for all grids and the set is of multivariate normal distribution with covariance matrix R_Lg”, [page 155 col 2 paragraph 4 lines 15-19]).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin with Veetil because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin discloses a system and method for performing generic netlist reduction, that speeds up Monte Carlo simulations, (see Yin [Abstract]). Yin does not go into details about the specific Monte Carlo simulation used to generate random values. Veetil teaches:
Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy.
(Veetil [Abstract lines 9-13])
A person having skill in the art would have a reasonable expectation of successfully increasing the speed of the Monte Carlo simulation after performing netlist reduction in the system and method of Yin by modifying Yin with the Quasi Monte Carlo simulation of Veetil. Therefore, it would have been obvious to combine Yin with Veetil to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 9, Yin in view of Veetil teaches all of the limitations of claim 1, as noted above. Yin does not teach computing and applying the same variation to two or more devices in the electronic circuit that are not in contact.
However, Veetil teaches computing and applying the same variation to two or more devices in the electronic circuit that are not in contact (A given inter-die sample is assigned to every element type in the library as before and the circuit leakage is obtained by adding up the leakage values from element types as in the traditional flow, [page 156 col 2 paragraph 2 lines 3-6]; where this is all in the context of: In the proposed approach the characterization is performed at samples generated using a Quasi Monte Carlo (QMC) based approach. In particular we use Sobol sequences in the QMC approach in this work. QMC samples refer to Sobol samples in the rest of the paper. The same process variation samples are used for characterization of all element types in the standard cell library and their states, [page 156 col 1 paragraph 5 line 5]-[page 156 col 2 paragraph 1 line 4]; see also quasi-random samples shown in FIG. 2, [page 156], samples are random values or sets of random values, and they are used to represent process variation parameters such as transistor gate length: “Therefore, each source of variation is represented by a set of random variables, one for each panel in the grid. For example, transistor gate length variation is represented by a set of random variables for all grids and the set is of multivariate normal distribution with covariance matrix R_Lg”, [page 155 col 2 paragraph 4 lines 15-19]).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin with Veetil because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin discloses a system and method for performing generic netlist reduction, that speeds up Monte Carlo simulations, (see Yin [Abstract]). Yin does not go into details about the specific Monte Carlo simulation used to generate random values. Veetil teaches:
Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy.
(Veetil [Abstract lines 9-13])
A person having skill in the art would have a reasonable expectation of successfully increasing the speed of the Monte Carlo simulation after performing netlist reduction in the system and method of Yin by modifying Yin with the Quasi Monte Carlo simulation of Veetil. Therefore, it would have been obvious to combine Yin with Veetil to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 10, Yin in view of Veetil teaches all of the limitations of claim 1, as noted above. Yin further teaches: combining a group of memory cells in the electronic circuit to form the optimized device (this is the process of netlist reduction, see box labeled "reduction engine" in FIG. 1.1, [page 2]; the details of netlist reduction are provided in Chapter 3, [page 21-35]; a very clear example is shown in FIGS. 3.5 and 3.6, where a bitcell and surrounding bitcells in FIG. 3.5 are replaced by an equivalent model in FIG. 3.6, [page 25]; for explanation see section labeled “3.1.3 Add equivalent model of bitcell”, [page 24], specifically, “To compensate for the capacitance loss, a pure capacitance model shown in Figure. 3.6 is used. The capacitors which connect to one net will be combined together in the end, [page 24 paragraph 2 lines 1-3]); and applying a variation to the optimized device (after netlist reduction is simulator running simulation as shown in FIG. 1.1, [page 2]; where simulation includes testing SRAM corners in a Monte Carlo simulation, [Abstract paragraph 2 lines 7-12]).
With respect to claim 13, Yin further teaches wherein the operations further comprise: generating a netlist parametric expression for the optimized device (This process is very time-consuming and memory-consuming since the intensive computation can generate a huge amount of data. This can be solved if the inactive part of the circuit is replaced by equivalent resistance and capacitance models”, [page 12 paragraph 5]-[page 13 paragraph 1]; where example RC model equations are provided in eq. (2.1)-(2.6), [page 16-17]; and section 3.4 describes building RC models for redundant circuits, [pages 33-34]).
Yin does not teach and generating random values for the optimized device and updating the netlist parametric expression for the optimized device; and simulating the optimized device using the random values and updated netlist parametric expression.
However, Veetil teaches and generating random values for the optimized device and updating the netlist parametric expression for the optimized device (In the proposed approach the characterization is performed at samples generated using a Quasi Monte Carlo (QMC) based approach. In particular we use Sobol sequences in the QMC approach in this work. QMC samples refer to Sobol samples in the rest of the paper. The same process variation samples are used for characterization of all element types in the standard cell library and their states, [page 156 col 1 paragraph 5 line 5]-[page 156 col 2 paragraph 1 line 4]; see also quasi-random samples shown in FIG. 2, [page 156], samples are random values or sets of random values, and they are used to represent process variation parameters such as transistor gate length: “Therefore, each source of variation is represented by a set of random variables, one for each panel in the grid. For example, transistor gate length variation is represented by a set of random variables for all grids and the set is of multivariate normal distribution with covariance matrix R_Lg”, [page 155 col 2 paragraph 4 lines 15-19]); and simulating the optimized device using the random values and updated netlist parametric expression (simulating is the last box of FIG. 3, “Estimate moments of circuit leakage...” and “compute sum...”, [page 156]; example simulation results using method shown in FIG. 3 is given in section 5, starting with, “Our simulation results are based on a 45nm commercial technology”, [page 157 col 2 paragraph 3 line 1]; see also Table 1, [page 158]).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin with Veetil because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin discloses a system and method for performing generic netlist reduction, that speeds up Monte Carlo simulations, (see Yin [Abstract]). Yin does not go into details about the specific Monte Carlo simulation used to generate random values. Veetil teaches:
Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy.
(Veetil [Abstract lines 9-13])
A person having skill in the art would have a reasonable expectation of successfully increasing the speed of the Monte Carlo simulation after performing netlist reduction in the system and method of Yin by modifying Yin with the Quasi Monte Carlo simulation of Veetil. Therefore, it would have been obvious to combine Yin with Veetil to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 15, incorporating the rejection of claim 4 and claim 13, claim 15 is rejected for a substantially similar rationale.
With respect to claim 17, incorporating the rejection of claim 6 and claim 12, claim 17 is rejected for a substantially similar rationale.
With respect to claim 18, incorporating the rejection of claim 7 and claim 12, claim 18 is rejected for a substantially similar rationale.
With respect to claim 19, incorporating the rejection of claim 8 and claim 12, claim 19 is rejected for a substantially similar rationale.
With respect to claim 20, incorporating the rejection of claim 9 and claim 12, claim 20 is rejected for a substantially similar rationale.
With respect to claim 22, Yin teaches A system for performing a Monte Carlo simulation of an electronic circuit, the system comprising: a processing device; and a memory coupled to the processing device, the memory storing computer readable instructions that when executed by the processing device cause the processing device to perform operations comprising (computer executing Python, (see [Abstract paragraph 3 line 1]; specifically instructions shown on the right side of FIG. 1.1, [page 2]; where a computer is implied by every being coded in Python [Abstract paragraph 3 line 1]; and notes such as being aware of processor memory overflow, [page 42 paragraph 1 line 14]; and a computer has a processor and memory as indicated by “processor memory overflow”): reading a netlist of the electronic circuit (see box labeled "original netlist" in FIG. 1.1, [page 2]; a discussion of circuit netlists is given in section 2.1.2.1, [page 11 paragraphs 3-5]); enabling simulator optimization such that two or more devices sharing one or more device parameters are combined and simulated as an optimized device (see box labeled "reduced netlist" and box labeled "simulator (fast)" in FIG. 1.1, [page 2]; a simulation requires the act of calculating, but the simulator is the set of equations required for the simulation, see “Simulators use complex device models to simulate the whole circuit, including active parts and inactive parts. Some inactive parts of the circuit do influence the active parts of the circuit somehow, and the influence comes from the resistance and capacitance characteristics of transistors. However, the simulator will perform a very complicated calculation based on a corresponding transistor model library. This process is very time-consuming and memory-consuming since the intensive computation can generate a huge amount of data. This can be solved if the inactive part of the circuit is replaced by equivalent resistance and capacitance models”, [page 12 paragraph 5]-[page 13 paragraph 1]; the details of netlist reduction are provided in Chapter 3, [page 21-35]; a very clear example is shown in FIGS. 3.5 and 3.6, where a bitcell and surrounding bitcells in FIG. 3.5 are replaced by an equivalent model in FIG. 3.6, [page 25]; for explanation see section labeled “3.1.3 Add equivalent model of bitcell”, [page 24], specifically, “To compensate for the capacitance loss, a pure capacitance model shown in Figure. 3.6 is used. The capacitors which connect to one net will be combined together in the end, [page 24 paragraph 2 lines 1-3]); generating equations of netlist parametric expressions for the optimized device (This process is very time-consuming and memory-consuming since the intensive computation can generate a huge amount of data. This can be solved if the inactive part of the circuit is replaced by equivalent resistance and capacitance models”, [page 12 paragraph 5]-[page 13 paragraph 1]; where example RC model equations are provided in eq. (2.1)-(2.6), [page 16-17]; and section 3.4 describes building RC models for redundant circuits, [pages 33-34]); mapping devices that share the same netlist parametric expressions (One cluster object contains all the information of the transistors that have been classified into this cluster, [page 30 paragraph 1 lines 1-2]).
Yin does not teach generating random values for each optimized device and computing equations of parametric expressions for each optimized device; and simulating the optimized device using the random values and the equations of parametric expressions.
However, Veetil teaches generating random values for each optimized device and computing equations of parametric expressions for each optimized device (In the proposed approach the characterization is performed at samples generated using a Quasi Monte Carlo (QMC) based approach. In particular we use Sobol sequences in the QMC approach in this work. QMC samples refer to Sobol samples in the rest of the paper. The same process variation samples are used for characterization of all element types in the standard cell library and their states, [page 156 col 1 paragraph 5 line 5]-[page 156 col 2 paragraph 1 line 4]; see also quasi-random samples shown in FIG. 2, [page 156], samples are random values or sets of random values, and they are used to represent process variation parameters such as transistor gate length: “Therefore, each source of variation is represented by a set of random variables, one for each panel in the grid. For example, transistor gate length variation is represented by a set of random variables for all grids and the set is of multivariate normal distribution with covariance matrix R_Lg”, [page 155 col 2 paragraph 4 lines 15-19]); and simulating the optimized device using the random values and the equations of parametric expressions (simulating is the last box of FIG. 3, “Estimate moments of circuit leakage...” and “compute sum...”, [page 156]; example simulation results using method shown in FIG. 3 is given in section 5, starting with, “Our simulation results are based on a 45nm commercial technology”, [page 157 col 2 paragraph 3 line 1]; see also Table 1, [page 158]).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin with Veetil because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin discloses a system and method for performing generic netlist reduction, that speeds up Monte Carlo simulations, (see Yin [Abstract]). Yin does not go into details about the specific Monte Carlo simulation used to generate random values. Veetil teaches:
Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy.
(Veetil [Abstract lines 9-13])
A person having skill in the art would have a reasonable expectation of successfully increasing the speed of the Monte Carlo simulation after performing netlist reduction in the system and method of Yin by modifying Yin with the Quasi Monte Carlo simulation of Veetil. Therefore, it would have been obvious to combine Yin with Veetil to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
Claim(s) 2 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Spice Circuit Reduction for Speeding Up Simulation and Verification” (2019-Yin) in view of Efficient Smart Sampling based Full-Chip Leakage Analysis for Intra-Die Variation Considering State Dependence (2009-Veetil) in further view of US 7,231,623 B2 (Miller)
With respect to claim 2, Yin in view of Veetil teaches all of the limitations of claim 1, as noted above. Yin further teaches storing ... that maps the two or more devices to the optimized device (One cluster object contains all the information of the transistors that have been classified into this cluster, [page 30 paragraph 1 lines 1-2]).
Yin and Veetil do not specifically teach a table as the format for the mapping.
However, Miller teaches storing a table... (The netlist text file parser program 106 creates
a hierarchical netlist database structure 110 consisting of a devices table 112, a nets table 114, and a macros table 116, [col 6 ln 26-28]; where “A macro is a Sub-circuit that is a grouping of primitive electrical devices and other macros”, [col 6 ln 52-54]; see also FIG. 3).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin in view of Veetil with Miller because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin in view of Veetil discloses a system and method that teaches all of the claimed features except for a table. Miller teaches:
The present invention overcomes the disadvantages and limitations of the prior art by providing an object oriented netlist database that stores electrical circuit data representative of an electrical circuit.
(Miller [col 3 ln 38-42]), and further teaches:
Performing analysis on data stored in a text file may be difficult, and very time consuming. Placing the electrical circuit data parsed from the netlist text file into an object oriented database allows more sophisticated programmatic analysis of the electrical circuit data.
(Miller [col 3 ln 48-52]).
A person having skill in the art would have a reasonable expectation of successfully storing objects created in the system and method of Yin in view Veetil by modifying Yin in view Veetil with the netlist database of Miller. Therefore, it would have been obvious to combine Yin in view of Veetil with Miller to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 14, incorporating the rejection of claim 2 and claim 12, claim 14 is rejected for a substantially similar rationale.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Spice Circuit Reduction for Speeding Up Simulation and Verification” (2019-Yin) in view of Efficient Smart Sampling based Full-Chip Leakage Analysis for Intra-Die Variation Considering State Dependence (2009-Veetil) in further view of “Machine Learning for the Performance Assessment of High-Speed Links” (2018-Trinchero)
With respect to claim 11, Yin in view of Veetil teaches all of the limitations of claim 1, as noted above. Yin and Veetil do not teach wherein generating random values for the optimized device further comprises using a machine learning model comprising at least one of an artificial neural network (ANN), a support vector machine (SVM), a radial basis function (RBF), fuzzy logic, a decision tree, random forest, or k-means algorithm.
However, Trinchero teaches wherein generating random values for the optimized device further comprises using a machine learning model comprising at least one of an artificial neural network (ANN), a support vector machine (SVM), a radial basis function (RBF), fuzzy logic, a decision tree, random forest, or k-means algorithm (This section discusses the application of the PC and SVM techniques to the case of a realistic high-speed communication link, such as the one depicted in Fig. 4, [page 1631 col 2 paragraph 1 lines 1-3]; Therefore, each parameter exhibits a uniform ±50% variation of around its central value, [page 1631 col 2 paragraph 2 lines 11-13]; where “a small subset of the MC realizations has been used to train the PC and SVM surrogate models” [page 1631 col 2 paragraph 4 lines 1-2]; Next, the surrogate models are used to compute the PDF of the transfer function (27) at the frequencies f1 = 275 MHz and f2 = 830 MHz, which are indicated by the dashed vertical lines in Fig. 5. The results are collected in Fig. 6 and highlight again the better accuracy of the SVM regression (dashed red lines) w.r.t. the PC expansion (dashed green line) in predicting the reference MC result (solid black line) from a very small training set size (e.g., L = 30 or 50), [page 1631 col 1 paragraph 2 lines 1-8]).
It would have been obvious to one skilled in the art before the effective filing date to combine Yin in view of Veetil with Trinchero because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Yin in view of Veetil discloses a system that teaches all of the claimed features except for using a machine learning surrogate model such as SVM to produce the random distribution in order to run the Monte Carlo simulation. Yin teaches that the Monte Carlo simulation needs to be executed, (Yin [Abstract paragraph 2 lines 7-12]; but does not give further details. Trinchero teaches “Even though MC is accurate, it requires a high computational cost without providing a parametric surrogate of the system”, Trinchero [page 1627 col 1 paragraph 3 lines 1-2]), and then goes on to list 4 reasons an SVM surrogate is an ideal surrogate model for this problem space, (Trinchero [page 1627 col 2 paragraph 1]). A person having skill in the art would have a reasonable expectation of successfully speeding up the Monte Carlo simulation described in Yin and further taught in Veetil with the with the surrogate modeling using a SVM from Trinchero. Therefore, it would have been obvious to combine Yin in view of Veetil with Trinchero to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 8453102 B1 (Pack) - Technique assesses the impact of physical circuit variations, specification parameter variation, or process variations on clock, signal, and power network performance and through a hierarchical modeling and hierarchical Monte Carlo simulation method, [Abstract].
US 2003/0126575 A1 (Yang) - A circuit reduction method that generates a netlist that maintains a topology of an original circuit while preserving an original circuit's functions and characteristics is provided. Further, a circuit reduction method that allows a user to selectively determine which nodes of an original circuit to reduce is provided. Further, a circuit reduction tool that is capable of removing loops that are not present in an original circuit but are present in an extraction of the original circuit is provided, [Abstract].
US 20240028803 A1 (Wolf) - A method may include obtaining a netlist representation of a circuit comprising a single-cell (S-Cell) or multi-cell (M-Cell), performing one or more test simulations using the netlist representation of the circuit, receiving one or more parameters comprising performance metrics of the circuit responsive to the one or more test simulations, and generating a parameterized model of the circuit responsive to the one or more parameters, [Abstract]; In addition to corners, which vary across an entire circuit in the same way, designers may be enabled to use test types such as Monte Carlo simulations to replicate a condition where not all devices have the same variation. Once the test type is modeled, the designer may be enabled to run any sort of test and have the modeled circuit accurately reflect the original's performance, [0034].
US 2007/0133245 A1 (Kerns) - A memory array can be optimized for SPICE simulation by modeling the memory array as a collection of boundary elements that track the cell states of memory cells connected to a particular array terminal. By maintaining a cell state distribution for each boundary element, the simulation behavior at the array terminal associated with that boundary element can be accurately determined by modeling each unique cell state, multiplying the results by the corresponding quantities from the cell state distribution, and then adding the results to obtain final values for the array terminal. This allows accurate simulation results to be achieved without needing to simulate each cell independently. Furthermore, by removing any references to unoccupied cell states (e.g., by removing such states from the cell state distribution and/or eliminating model equations for such states), the memory and cpu usage requirements during the simulation can be minimized, [Abstract].
US 2008/0243414 A1 (Oh) - A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately, [Abstract]; see also FIG. 4.
US 2018/0225399 A1 (Das) - At stage 1316, embodiments can extract, automatically, a timing-sensitive circuit defined by a subset of the connectivity graph having the circuit blocks of the integrated circuit corresponding to the sequence of through-nodes. As described above, the timing-sensitive circuit can be used to facilitate a number of features. In some embodiments, the timing-sensitive circuit can be used to automatically generate circuit test bench data, such as a set of side nodes and side-node stimuli for use with a test bench. The test bench data can be used, for example, to execute Monte Carlo simulations of the circuit with appropriate process corner definition, [0058].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL MILLER whose telephone number is (408) 918-7548. The examiner can normally be reached on Monday-Friday from 11am to 5pm (PT). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang, can be reached at telephone number 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.M./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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