DETAILED ACTION
Oath/Declaration
Oath and declaration filed on 1/8/2024 is accepted.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 ,7-10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Cohen et al (2024/0147874 A1) in view of Huang (2021/0118830 A1) further in view of Fu et al (2021/0408276 A1).
Regarding claim 1, Cohen et al discloses (refer to figures 8) a method for manufacturing a semiconductor device (800) , comprising: forming a first dielectric layer (3) on a semiconductor substrate (2) (paragraph 0076) ; forming a plurality of spaced-apart electrodes (4) (paragraph 0056) in the first dielectric layer; forming a patterned stack on the electrodes opposite to the semiconductor substrate (4) , the patterned stack including a plurality of stack portions spaced apart from each other, each of the stack portions including a heater portion (34) disposed on and connected to at least one of the electrodes (4) (figure 4) and a phase change material portion (44) (paragraph 0076) disposed on the heater portion opposite to the at least one of the electrodes (4); forming a second dielectric layer (22) to conformally cover the patterned stack; and forming a third dielectric layer (23) on the second dielectric layer (paragraph 0059).
Cohen et al discloses all of the claimed limitations except the third dielectric layer being formed with a plurality of air gaps such that the stack portions are spaced apart from each other by the air gaps.
Huang discloses third dielectric layer being formed with a plurality of air gaps (150) such that the stack portions are spaced apart from each other by the air gaps (paragraph 0054, semiconductor device 100a, air gaps 130 and dielectric layers 113,129,133,149,153,159, and 163).
It would have been obvious to one of ordinary skill in the art at the time of invention was made to provide adding the third dielectric layer with a plurality of air gaps such that the stack portions are spaced apart from each other by the air gaps in to the Cohen semiconductor structure for the purpose of conductive formed third dielectric layer as taught by Huang (paragraph 0017).
Cohen et al in view of Huang discloses all of the claimed limitations except patterned stacks and stack portion.
Fu et al discloses patterned stacks (115) (paragraph 0033, figure 1) and stack portion (paragraph 0101).
It would have been obvious to one of ordinary skill in the art at the time of invention was made to provide teaching patterned stacks and stack portion in to the Cohen et al in view of Huang a semiconductor device improve the integration density various electronic components as taught by Fu et al (paragraph 0002).
Regarding claim 2, Cohen et al discloses wherein in formation of the patterned stack, a first dielectric spacer is formed between the heater portion (34) and the phase change material portion and a second dielectric spacer is formed on the phase change material portion opposite to the first dielectric spacer (paragraph 0062).
Regarding claim 3, Cohen et al discloses wherein formation of the patterned stack includes: forming a patterned heater layer (34) on the electrodes; and after forming the patterned heater layer, forming a lower pattered dielectric layer on the patterned heater layer(34) , forming a patterned phase change material layer on the lower pattered dielectric layer opposite to the patterned heater layer, and forming an upper patterned dielectric layer on the patterned phase change material layer opposite to the lower patterned dielectric layer (figures 1,4 and 8).
Regarding claim 7, Cohen et al discloses further comprising: forming an interconnect structure below the electrodes (46) (shown in figure 4), the interconnect structure including a plurality of spaced-apart conductive interconnects, such that at least one of the electrodes is connected to at least one of the conductive interconnects, respectively; and forming a bond pad which is spaced apart from one of the stack portions adjacent to the bond pad and which is connected to a corresponding one of the conductive interconnects.
Regarding claim 8, Cohen et al discloses (refer to figures 8) a method for manufacturing a semiconductor device (800) , comprising: forming a first dielectric layer (3) on a semiconductor substrate (2) ; forming a plurality of spaced-apart electrodes (4) in the first dielectric layer; on the electrodes opposite to the semiconductor substrate (2), the patterned stack including a patterned heater layer(34) disposed on and connected to the electrodes and a patterned phase change material layer disposed on the patterned heater layer opposite to the electrodes; forming a second dielectric layer (22) to conformally cover the patterned stack; and forming a third dielectric layer (23) on the second dielectric layer.
(paragraph 0059).
Cohen et al discloses all of the claimed limitations except the third dielectric layer being formed with a plurality of air gaps .
Huang discloses third dielectric layer being formed with a plurality of air gaps (150) such that by the air gaps (paragraph 0054, semiconductor device 100a, air gaps 130 and dielectric layers 113,129,133,149,153,159, and 163).
It would have been obvious to one of ordinary skill in the art at the time of invention was made to provide adding the third dielectric layer with a plurality of air gaps such that the by the air gaps in to the Cohen semiconductor structure for the purpose of conductive formed third dielectric layer as taught by Huang (paragraph 0017).
Cohen et al in view of Huang discloses all of the claimed limitations except patterned stacks and stack portion.
Fu et al discloses patterned stacks (115) (paragraph 0033, figure 1) and stack portion (paragraph 0101).
It would have been obvious to one of ordinary skill in the art at the time of invention was made to provide teaching patterned stacks and stack portion in to the Cohen et al in view of Huang a semiconductor device improve the integration density various electronic components as taught by Fu et al (paragraph 0002).
Regarding claim 9, Cohen et al discloses wherein: the patterned stack includes a plurality of stack portions spaced apart from each other; and the air gaps are formed in the patterned stack such that the stack portions are spaced apart from each other by the air gaps (figures 1,4 and 8).
Regarding claim 10, combination of Cohen et al in view of Huang discloses
formation of the patterned stack, a lower patterned dielectric layer (22) (figure 4) is formed between the patterned heater layer and the patterned phase change material layer and an upper patterned dielectric layer is formed on the patterned phase change material layer opposite to the lower patterned dielectric layer.
Regarding claim 15, combination of Cohen et al in view of Huang discloses further comprising: forming an interconnect structure below the electrodes (22 and 23), the interconnect structure including a plurality of spaced-apart conductive interconnects, such that at least one of the electrodes is connected to at least one of the conductive interconnects, respectively; and forming a bond pad which is spaced apart from one of the stack portions adjacent to the bond pad and which is connected to a corresponding one of the conductive interconnects.
Claim(s) 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Cohen et al (2024/0147874 A1) in view of Kim et al (2024/0142850 A1).
Regarding claim 16, Cohen et al discloses (refer to figures 1,4,8) a semiconductor device (100), comprising: a semiconductor substrate (4);a first dielectric layer (3) disposed on the semiconductor substrate (4) ; a plurality of spaced-apart electrodes disposed in the first dielectric layer (3); and a second dielectric layer (22), which includes a heater portion (34) disposed on and connected to at least one of the electrodes and a phase change material portion disposed on the heater portion opposite to the at least one of the electrodes(paragraph 0076).
Cohen discloses all of the claim limitations except a spatial light modulator disposed on the electrodes and the first dielectric layer, the spatial light modulator including a plurality of pixels spaced apart from each other.
Kim et al discloses a spatial light modulator (10) disposed on the electrodes and the first dielectric layer, the spatial light modulator including a plurality of pixels spaced apart from each other (PX1 and PX2) (paragraph 0068).
It would have been obvious to one of ordinary skill in the art at the time of invention was made to provide adding a spatial light modulator and the spatial light modulator including a plurality of pixels spaced apart from each other in to the Cohen semiconductor structure for the purpose of high reliability a semiconductor device as taught by Kim (paragraph 0006).
Regarding claim 17, Cohen et al discloses further comprising a third dielectric layer (23) formed on the second dielectric layer (22) (figure 4), the third dielectric layer including a plurality of air gaps such that the pixels are spaced apart from each other by the air gaps.
Regarding claim 18, combination Cohen et al in view of Kim et al discloses wherein the stack portion further includes a first dielectric spacer disposed between the heater portion and the phase change material portion and a second dielectric spacer disposed on the phase change material portion opposite to the first dielectric spacer.
Regarding claim 19, combination of Cohen et al in view of Kim et al discloses further comprising: an interconnect structure disposed below the electrodes, the interconnect structure including a plurality of spaced-apart conductive interconnects, such that at least one of the electrodes is connected to at least one of the conductive interconnects, respectively; and a bond pad which is disposed to be spaced apart from one of the stack portions adjacent to the bond pad and which is connected to a corresponding one of the conductive interconnects.
Allowable Subject Matter
3.Claims 4-6, 11-14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
4. The following is a statement of reasons for the indication of allowable subject matter: wherein formation of the patterned heater layer includes: forming a heater material layer on the electrodes; patterning the heater material layer to form the patterned heater layer; forming a fourth dielectric layer on the first dielectric layer to cover the patterned heater layer; and removing a portion of the fourth dielectric layer such that the patterned heater layer is disposed in remainder of the fourth dielectric layer and wherein formation of the lower pattered dielectric layer, the patterned phase change material layer, and the upper patterned dielectric layer includes: forming a fifth dielectric layer on the remainder of the fourth dielectric layer and the patterned heater layer; forming a phase change material layer on the fifth dielectric layer; forming a sixth dielectric layer on the phase change material layer opposite to the fifth dielectric layer; and patterning the fifth dielectric layer, the phase change material layer, and the sixth dielectric layer so as to form the fifth dielectric layer into the lower pattered dielectric layer, to form the phase change material layer into the patterned phase change material layer, and to form the sixth dielectric layer into the upper patterned dielectric layer and wherein formation of the patterned stack includes: forming a heater material layer on the electrodes; forming a fourth dielectric layer on the heater material layer opposite to the electrodes; forming a phase change material layer on the fourth dielectric layer opposite to the heater material layer; forming a fifth dielectric layer on the phase change material layer opposite to the fourth dielectric layer; and patterning the heater material layer, the fourth dielectric layer, the phase change material layer, and the fifth dielectric layer so as to form the heater material layer into the patterned heater layer, to form the fourth dielectric layer into the lower pattered dielectric layer, to form the phase change material layer into the patterned phase change material layer, and to form the fifth dielectric layer into the upper patterned dielectric layer and wherein formation of the patterned stack includes: forming the patterned heater layer on the electrodes; and after forming the patterned heater layer, forming the lower pattered dielectric layer on the patterned heater layer, forming the patterned phase change material layer on the lower pattered dielectric layer opposite to the patterned heater layer, and forming the upper patterned dielectric layer on the patterned phase change material layer opposite to the lower patterned dielectric layer and wherein formation of the patterned heater layer includes: forming a heater material layer on the electrodes; patterning the heater material layer to form the patterned heater layer; forming a fourth dielectric layer on the first dielectric layer to cover the patterned heater layer; and removing a portion of the fourth dielectric layer such that the patterned heater layer is disposed in remainder of the fourth dielectric layer and wherein formation of the lower pattered dielectric layer, the patterned phase change material layer, and the upper patterned dielectric layer includes: forming a fifth dielectric layer on the remainder of the fourth dielectric layer and the patterned heater layer; forming a phase change material layer on the fifth dielectric layer; forming a sixth dielectric layer on the phase change material layer opposite to the fifth dielectric layer; and patterning the fifth dielectric layer, the phase change material layer, and the sixth dielectric layer so as to form the fifth dielectric layer into the lower pattered dielectric layer, to form the phase change material layer into the patterned phase change material layer, and to form the sixth dielectric layer into the upper patterned dielectric layer and wherein formation of the patterned stack includes: forming a heater material layer on the electrodes; forming a fourth dielectric layer on the heater material layer opposite to the electrodes; forming a phase change material layer on the fourth dielectric layer opposite to the heater material layer; forming a fifth dielectric layer on the phase change material layer opposite to the fourth dielectric layer; and patterning the heater material layer, the fourth dielectric layer, the phase change material layer, the fifth dielectric layer so as to form the heater material layer into the patterned heater layer, to form the fourth dielectric layer into the lower pattered dielectric layer, to form the phase change material layer into the patterned phase change material layer, and to form the fifth dielectric layer into the upper patterned dielectric layer and wherein each of the pixels has a pixel size ranging from 200 nm to 500 nm, and two adjacent ones of the pixels are spaced apart from each other by a spacing distance ranging from 50 nm to 100 nm.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A HASAN whose telephone number is (571)272-2331. The examiner can normally be reached M-TH 6 AM -4 PM.
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/MOHAMMED A HASAN/Primary Examiner, Art Unit 2872 3/17/2026