Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/406,634 filed on 01/08/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-7 and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2021/0050475 to Tsai et al. (Tsai).
Regarding independent claim 1, Tsai discloses a vertical thin-film (VTF) light emitting diode (LED) (Figs. 4-10 and ¶0032-0053 and Table 1) comprising:
an epitaxial stack (411-414; Table 1) comprising a plurality of group Ill-V semiconductor material layers, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (AI), indium (In), and phosphorus (P) (Table: binary GaP, ternary AllnP, quaternary AIGaInP)and a multiple quantum well layer (412) on a substrate (400), wherein at least one of the plurality of group Ill-V semiconductor material layers is a low confinement layer (LCL) (barrier sublayer serving for optical and carrier confinement) comprising aluminum indium gallium phosphide (AIInGaP);
a first dielectric layer (Fig. 10: 440) on the epitaxial stack (411-414);
an n-contact (422) and a p-contact (421) within the first dielectric layer (440); and
a metal layer (431) on the first dielectric layer (Fig. 10: 440) in electrical contact with the plurality of group Ill-V semiconductor material layers.
Regarding claim 2, Tsai discloses wherein at least one of the plurality of group Ill-V semiconductor material layers comprise an aluminum indium phosphide (AIInP) layer (see Table 1).
Regarding claim 3, Tsai discloses wherein at least one of the plurality of group Ill-V semiconductor material layers comprise an aluminum indium gallium phosphide (AIInGaP) layer (see Table 1).
Regarding claim 6, Tsai discloses wherein one of the plurality of group Ill-V semiconductor material layers comprise an aluminum (AI) layer (see Table 1).
Regarding claim 7, Tsai discloses wherein the metal layer (431) comprises one or more of aluminum (AI), platinum (Pt), and silver (Ag) (¶0052).
Regarding claim 9, Tsai discloses a bonding layer (Fig. 10: 432).
Regarding claim 10, Tsai discloses wherein the P-contact (421) comprises an alloy of gold (Au) and zinc (Zn) (¶0050).
Regarding claim 11, Tsai discloses herein the N-contact (422) comprises an alloy of gold (Au) and germanium (Ge) (¶0050).
Regarding claim 12, Tsai discloses wherein the first dielectric layer (440) comprises one or more of silicon oxide (SiOx), titanium oxide (TiOx), niobium oxide (NbyOx), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AIOx), and aluminum nitride (AIN) (¶0051).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # US Pub # 2021/0050475 to Tsai et al. (Tsai).
Regarding claim 4, Tsai discloses wherein the low confinement layer (LCL) (see Table 1), but Tsai does not explicitly disclose wherein the low confinement layer (LCL) contains in a range of from about 30% to about 40% aluminum indium gallium phosphide (AIInGaP) (see Table 1). However, Tsai does teach (Table 1) a low confinement layer (LCL) (barrier sublayer serving for optical and carrier confinement) comprising aluminum indium gallium phosphide (AIInGaP).
It would have been obvious to one of ordinary skill in the art at the time of the invention to have provided the low confinement layer (LCL) of Tsai to contain in a range of from about 30% to about 40% aluminum indium gallium phosphide (AIInGaP).
The motivation to do so is that the low confinement layer (LCL) contains in a range of from about 30% to about 40% aluminum indium gallium phosphide (AIInGaP) provides the predictable result of tuning the bandgap and refractive index to balance sufficient carrier confinement and to reduce optical absorption which is necessary of Tsai.
While the cited prior art does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization.
The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 5, Tsai discloses wherein the low confinement layer (LCL) has a thickness (Table 1: the cladding and barrier sublayers may commonly be referred to as the LCL, since they fulfil the confinement function and comprise AllnGaP at least in the sublayer), but Tsai does not explicitly disclose wherein the low confinement layer (LCL) has a thickness in a range of from 2 µm to 5 µm. However, Tsai does teach (Table 1) an overlapping range for the low confinement layer (LCL).
It would have been obvious to one of ordinary skill in the art at the time of the invention to form the low confinement layer (LCL) of Tsai having a thickness range of from 2 µm to 5 µm, to the invention of Tsai.
The motivation to do so is that a layer of the low confinement layer (LCL) having a thickness of range of from 2 µm to 5 µm provides the predictable result to balance carrier confinement and optical performance for improving overall LED efficiency which is necessary of Tsai.
While the cited prior art does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization.
The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Claims 8, 13, 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2018/0138366 to Sung et al. (Sung) in view of US Pub # 2021/0050475 to Tsai et al. (Tsai).
Regarding claim 8, Tsai discloses all of the limitations of claim 7 from which this claim depends.
Tsai fails to explicitly disclose a second dielectric layer on the metal layer.
Sung teaches a second dielectric layer (215c) on the metal layer (210a) (¶0066-0074 and Figs. 4a-4b).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have utilized the vertical thin-film (VTF) LED of Tsai with the second dielectric layer as taught by Sung so as to expose the contact electrode inside the connection groove such that the contact electrode and the bonding electrode can be electrically connected to each other inside the connection groove (¶0073).
Regarding independent claim 13, Sung discloses a method of manufacturing a vertical thin-film (VTF) LED (Figs. 6a-6i and ¶0093-0106), the method comprising:
sequentially forming a plurality of group Ill-V semiconductor material layers (205a, 205b, 205c), including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (AI), indium (In), and phosphorus (P) (¶0031: quaternary AllnGaP layer 105a; ¶0035: ternary AlGaP and binary GaP) and a multiple quantum well layer (¶0035: 105c) to form an epitaxial stack (205) on a substrate (225), wherein at least one of the plurality of group Ill-V semiconductor material layers is a low confinement layer (LCL) (205a) comprising aluminum indium gallium phosphide (AIInGaP);
depositing a first dielectric layer (Fig. 6B: 215a) on the epitaxial stack (205);
removing (Fig. 6B and ¶0095: etching step) a portion of the first dielectric layer (215a) to form openings (Fig. 6B: area between 215a) in the dielectric layer (215a), the openings exposing the plurality of group Ill-V semiconductor material layers;
forming a metal layer (210a) on the first dielectric layer in electrical contact with the plurality of group Ill-V semiconductor material layers;
forming a bond pad (Fig. 6e: 210b);
depositing a second dielectric layer (Fig. 6F: 215c) on the metal layer; and
forming an N-contact (Fig. 6c: 220a) on the epitaxial stack.
Sung fails to explicitly disclose forming a P-contact in the openings in the dielectric layer.
Tsai discloses forming a P-contact (Fig. 9: 421) in the openings in the dielectric layer (440).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the opening of Sung with a P-contact as taught by Tsai so as to be in ohmic contact with the epitaxial structure (¶0050).
Regarding claim 15, Sung discloses all of the limitations of claim 13 from which this claim depends.
Sung fails to explicitly disclose wherein at least one of the plurality of group Ill-V semiconductor material layers comprise an aluminum indium phosphide (AIInP) layer.
Tsai discloses wherein at least one of the plurality of group Ill-V semiconductor material layers comprise an aluminum indium phosphide (AIInP) layer (¶0023).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided at least one of the plurality of group Ill-V semiconductor material layers of Sung with an aluminum indium phosphide (AIInP) layer as taught by Tsai so as to provide electrons (¶0023).
Regarding claim 16, Sung discloses wherein at least one of the plurality of group Ill-V semiconductor material layers comprise an aluminum (AI) layer (¶0031).
Regarding claim 17, Sung discloses wherein the metal layer (210a) comprises one or more of aluminum (AI), platinum (Pt), and silver (Ag) (¶0043).
Regarding claim 18, Sung discloses all of the limitations of claim 13 from which this claim depends.
Sung fails to explicitly disclose wherein the P-contact comprises an alloy of gold (Au) and zinc (Zn).
Tsai discloses wherein the P-contact (Fig. 9: 421) comprises an alloy of gold (Au) and zinc (Zn) (¶0050).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the opening of Sung with a P-contact as taught by Tsai so as to be in ohmic contact with the epitaxial structure (¶0050).
Regarding claim 20, Sung discloses wherein the first dielectric layer (215a) comprises one or more of silicon oxide (SiOx), titanium oxide (TiOx), niobium oxide (NbyOx), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AIOx), and aluminum nitride (AIN) (¶0053).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2018/0138366 to Sung et al. (Sung) in view of US Pub # 2021/0050475 to Tsai et al. (Tsai) and further in view of US Pub # 2023/0420627 to Armitage.
Regarding claim 14, Sung and Tsai discloses all of the limitations of claim 13 from which this claim depends.
Sung and Tsai fails to explicitly disclose annealing the epitaxial stack prior to forming the N-contact and the P-contact in the dielectric openings.
Armitage discloses annealing the epitaxial stack prior to forming the N-contact and the P-contact in the dielectric openings (¶0123).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the epitaxial stack of Sung with the annealing as taught by Armitage so as to activate the dopants (¶0077).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2018/0138366 to Sung et al. (Sung) in view of US Pub # 2021/0050475 to Tsai et al. (Tsai) and further in view of US Pub # 2023/0402572 to Jia et al. (Jia).
Regarding claim 19, Sung and Tsai discloses all of the limitations of claim 13 from which this claim depends.
Sung and Tsai fails to explicitly disclose wherein the N-contact comprises an alloy of one or more of gold (Au), germanium (Ge), and nickel (Ni).
Jia disclose wherein the N-contact comprises an alloy of one or more of gold (Au), germanium (Ge), and nickel (Ni) (¶0032).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the N-contact of Sung with an alloy of one or more of gold (Au), germanium (Ge), and nickel (Ni) so as to uniformly deliver current from the metal reflection layer 102 and the metal bonding layer to the semiconductor epitaxial stack (¶0032).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.US Pub # 2021/0257393 to Yuan et al., US Pub # 2018/0374953 to Zhang., US Pub # 2014/0103307 to Chang et al., US Pub # 2006/0175609 to Chan et al., US Pub # 2020/0105972 to Dimitropoulos et al., and US Pub # 2012/0267665 to Lin.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
Prosecution Insights