DETAILED ACTION
This correspondence is in response to the communications received January 8, 2024. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1, 2, 4, 6, 10 and the claims that depend therefrom are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, recites, “wherein the first molded layer surrounds a lowermost, in a direction, die, of the plurality of stacked dies”. The usage of “lowermost, in a direction, die” is confusing. The only disclosed direction that the first molded layer surrounds the lowermost die, is a lateral direction. So an amendment to the effect of, “wherein the first molded layer laterally surrounds a lowermost
Then, as the concept of “the direction” is subsequently used in the claim, in the recitation of, “wherein the second molded layer is disposed above, in the [lateral] direction, the first molded layer”, further confuses the claim language. If the previously established “direction” can only be interpreted to be a “lateral direction”, this recitation does not make sense.
For purposes of examination, the recitation will be interpreted in the following manner as guided by the disclosure,
“wherein the first molded layer laterally surrounds a lowermost
wherein the second molded layer is disposed above
Claim 2 recites, “wherein the second molded layer is a thick molded layer that substantially encompasses a thickness, in the direction, of the molded die assembly, wherein the first molded layer includes a plurality of interconnections extending, in the direction, from an upper surface of the first molded layer to a lower surface of the first molded layer”. Again, the “in a direction” has the issues discussed above for claim 1. It is unclear what direction is being referred to.
Claim 6 recites, “wherein the substrate is disposed below, in a direction, the molded die assembly, and wherein the other molded die assembly is disposed above, in the direction, the molded die assembly.” Again, the “in a direction” has the issues discussed above for claim 1. It is unclear what direction is being referred to. Further “other molded die assembly” lacks antecedent basis. It is unclear which molded die assembly is being referred to. As the claim language is unclear, and as best understood by Examiner, this claim means that an additional modular package is established in electrical connection above the construction of claim 1.
Similarly, claims 4 and 10, recite “in the direction”, which then suffers from the same lack of clarity as to the meaning of this portion of the claims. It is unclear what direction is being referred to.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 4F and 5, a semiconductor device assembly, comprising:
a substrate (308);
a molded die assembly (302, ¶ 0054) electrically coupled to the substrate (coupled to 308),
the molded die assembly (302) including:
a plurality of stacked dies (312) electrically coupled to the substrate (to 308) via a plurality of wire bonds (314); and
a molded casing (316 and 318, ¶ 0036, hereinafter referred to as ‘MC’) surrounding the plurality of stacked dies and encapsulating the plurality of wire bonds (318 surrounds and encapsulates 312 and 314),
wherein the molded casing (MC) includes a first molded layer (316) and a second molded layer (318),
wherein the first molded layer (316) laterally surrounds a lowermost
wherein the second molded layer (318) is disposed above
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2020/0251447).
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Regarding claim 1, the prior art of Kang discloses in Fig. 1A, a semiconductor device assembly (see title, “SEMICONDUCTOR PACKAGES HAVING STACKED CHIP STRUCTURE”), comprising:
a substrate (“substrate 100”, ¶ 0022);
a molded die assembly (combination of features encapsulated within both of 120 and 140, “second mold layer 140 disposed on the first mold layer 120”, ¶ 0022, hereinafter referred to as ‘MDA’) electrically coupled to the substrate (¶ 0026, discloses that bond wires 501 are connected to 111, which is within 100, and also discloses that bond wires 502 are connected to 112, which is within 100, thus components within 120 and 140 are “electrically coupled to the substrate” 100),
the molded die assembly (MDA: 120 and 140) including:
a plurality of stacked dies (within 120 there are “first semiconductor chips 210, 220, 230, 240, and 250 of the first chip stack 200”, ¶ 0026, and within 140 there are “second semiconductor chips 310, 320, 330, 340, and 350 of the second chip stack 300”, ¶ 0026) electrically coupled to the substrate via a plurality of wire bonds (as stated above from ¶ 0026, chips 200 are connected to 111 of 100, by way of 501, and chips 300 are connected to 112 of 100 by way of 502); and
a molded casing (“first mold layer 120”, ¶ 0022, and “second mold layer 140”, ¶ 0022) surrounding the plurality of stacked dies (120 surround 200, 140 surround 300) and encapsulating the plurality of wire bonds (120 encapsulates 501, 140 encapsulates 502), wherein the molded casing includes a first molded layer (120) and a second molded layer (140),
wherein the first molded layer (120) laterally surrounds a lowermost
wherein the second molded layer is disposed above
Kang does not disclose in the embodiment of Fig. 1A, that the “semiconductor chip” is a “semiconductor die”.
Kang discloses in paragraph 0018, that “semiconductor chip” is equivalent to “semiconductor die”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, that “semiconductor chip” is equivalent to “semiconductor die”, as disclosed by paragraph 0018 of Kang in the system of Fig. 1A of Kang, for the purpose of utilizing a semiconductor portion from a wafer which is a standard unit of semiconductor material as base infrastructure for fabricating integrated circuits. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Kang discloses the semiconductor device assembly of claim 1, wherein the first molded layer (120) is a thin molded layer (120 is relatively thinner than 140 as can be seen in Fig. 1A), wherein the second molded layer (140) is a thick molded layer (140 is relatively thicker than 120) that substantially encompasses a thickness, in the direction, of the molded die assembly (140 encompasses 300), wherein the first molded layer (120) includes a plurality of interconnections extending, in the direction, from an upper surface of the first molded layer to a lower surface of the first molded layer (122, 124, 501 extend through 120), and wherein the second molded layer embeds the plurality of wire bonds within the second molded layer (140 has 502 embedded therein).
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2020/0251447) in view of Goh et al. (US 2023/0178502).
Regarding claim 3, the prior art of Kang discloses the semiconductor device assembly of claim 2, however Kang does not disclose, “wherein the plurality of interconnections include a plurality of contacts disposed in the first molded layer, wherein a first subset of the plurality of contacts form an electrical connection with one or more wire bonds, of the plurality of wire bonds, and wherein a second subset of the plurality of contacts are electrically isolated from the plurality of wire bonds.”
Goh discloses in Figs. 9-15, wherein the plurality of interconnections include a plurality of contacts (“metal (e.g., copper) stubs 416”, ¶ 0035, and “bonding pads 406”, ¶ 0035) disposed in the first molded layer (equivalent “first molded layer”, is “molding compound 220”, ¶ 0039), wherein a first subset of the plurality of contacts form an electrical connection with one or more wire bonds (several 406/416 are in contact with “wire bonds 214”, ¶ 0039), of the plurality of wire bonds (plural 214 shown), and wherein a second subset of the plurality of contacts are electrically isolated from the plurality of wire bonds (several 406/416 are shown to be electrically isolated from wire bonds 214).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the plurality of interconnections include a plurality of contacts disposed in the first molded layer, wherein a first subset of the plurality of contacts form an electrical connection with one or more wire bonds, of the plurality of wire bonds, and wherein a second subset of the plurality of contacts are electrically isolated from the plurality of wire bonds”, as disclosed by Goh in the system of Kang, for the purpose of providing input electrodes for electrical connection to the inner devices within the molding and potential bypass electrodes for further electrical signal routing as may be needed for further integration. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 5, the prior art of Kang discloses the semiconductor device assembly of claim 1, however Kang does not disclose, “wherein the molded die assembly is coupled to the substrate via a plurality of micro balls, wherein a first subset of the plurality of micro balls provide an electrical connection between the molded die assembly and the substrate, and wherein a second subset of the plurality of micro balls do not provide an electrical connection between the molded die assembly and the substrate.”
Goh discloses in Fig. 16, wherein the molded die assembly is coupled to the substrate via a plurality of micro balls (402 connects to “Package Substrate” via “microballs 1602”, ¶ 0041), wherein a first subset of the plurality of micro balls provide an electrical connection between the molded die assembly and the substrate (some of electrical connections are in contact with bond wires in module), and wherein a second subset of the plurality of micro balls do not provide an electrical connection between the molded die assembly and the substrate (some of electrical connections are not in contact with bond wires in module).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the molded die assembly is coupled to the substrate via a plurality of micro balls, wherein a first subset of the plurality of micro balls provide an electrical connection between the molded die assembly and the substrate, and wherein a second subset of the plurality of micro balls do not provide an electrical connection between the molded die assembly and the substrate”, as disclosed by Goh in the system of Kang, for the purpose of providing input electrodes for electrical connection to the inner devices within the molding and potential bypass electrodes for further electrical signal routing as may be needed for further integration. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 4, 6 and 7, are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2020/0251447) in view of Nam et al. (US 2016/0225744).
Regarding claim 4, the prior art of Kang discloses the semiconductor device assembly of claim 1, however Kang does not disclose, “further comprising another molded die assembly electrically coupled to the substrate, the other molded die assembly including: at least one other die electrically coupled to the substrate via another plurality of wire bonds; and another molded casing surrounding the at least one other die and encapsulating the other plurality of wire bonds, wherein the other molded casing includes another first molded layer and another second molded layer, wherein the other first molded layer surrounds another lowermost die, in the direction, die, of the at least one other die, and wherein the second molded layer is disposed above, in the direction, the first molded layer.”
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Replacing Kang’s Fig. 1A, top module 140/300 with a repeating module arrangement such as shown by Nam, claim 4 would be satisfied.
Nam discloses in Fig. 9, further comprising another molded die assembly (modules 23 and 25, ¶ 0054, 0056) electrically coupled to the substrate,
the other (for purposes of examination, the terms “another” and “other” appear to refer to the same element, and will be treated as such.) molded die assembly including:
at least one other die (module 23, ¶ 0049, including “semiconductor die 3100”, ¶ 0054) electrically coupled to the substrate (adding module 23 to Kang, where Kang’s substrate is still present in the combination construction) via another plurality of wire bonds (module 23, ¶ 0049, including “bonding wires 3900”, ¶ 0054, ); and
another molded casing (“encapsulation part 3300”, ¶ 0054) surrounding the at least one other die (shown surrounding 3100 of 25) and encapsulating the other plurality of wire bonds (module 23, ¶ 0049, including “bonding wires 3900”, ¶ 0054, ),
wherein the other (It is unclear what this refers to? A second extra module? module 23) molded casing includes another first molded layer (molding 3300 for 23 shown) and another second molded layer (including module 25’s molding),
wherein the other first molded layer surrounds another lowermost die (3300 surrounds 3100 in 23), in the direction, die, of the at least one other die (3100 in 23), and
wherein the second molded layer (molding for 25) is disposed above, in the direction, the first molded layer (above the 3300 for 23).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “further comprising another molded die assembly electrically coupled to the substrate, the other molded die assembly including: at least one other die electrically coupled to the substrate via another plurality of wire bonds; and another molded casing surrounding the at least one other die and encapsulating the other plurality of wire bonds, wherein the other molded casing includes another first molded layer and another second molded layer, wherein the other first molded layer surrounds another lowermost die, in the direction, die, of the at least one other die, and wherein the second molded layer is disposed above, in the direction, the first molded layer.”, as disclosed by Goh in the system of Kang, for the purpose of providing input electrodes for electrical connection to the inner devices within the molding and potential bypass electrodes for further electrical signal routing as may be needed for further integration. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 6, the prior art of Kang discloses the semiconductor device assembly of claim 1, however Kang does not disclose, “further comprising another molded die assembly electrically coupled to the substrate, wherein the substrate is disposed below, in a direction, the molded die assembly, and wherein the other molded die assembly is disposed above, in the direction, the molded die assembly.”
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As the claim language is unclear as stated in the 112b rejection above, and as best understood by Examiner, this claim means that an additional modular package is established in electrical connection above the construction of claim 1.
Replacing Kang’s Fig. 1A, top module 140/300 with a repeating module arrangement such as shown by Nam, claim 4 would be satisfied. So the top module (identified by elements 140/300) of Kang’s Fig. 1A, is equivalent to Nam’s Fig. 9 module 21. Replacing the module of Kang with the module of Nam, would allow for further modules to be included in the stack of modules.
Nam discloses in Fig. 9, further comprising another molded die assembly electrically coupled to the substrate, wherein the substrate is disposed below, in a direction, the molded die assembly, and wherein the other molded die assembly is disposed above, in the direction, the molded die assembly (on top of module 21, a first molding module equivalent is module 23, and second molding module equivalent is module 25, each module including a “semiconductor die 3100”, ¶ 0054).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “further comprising another molded die assembly electrically coupled to the substrate, wherein the substrate is disposed below, in a direction, the molded die assembly, and wherein the other molded die assembly is disposed above, in the direction, the molded die assembly.”, as disclosed by Goh in the system of Kang, for the purpose of providing input electrodes for electrical connection to the inner devices within the molding and potential bypass electrodes for further electrical signal routing as may be needed for further integration. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 7, the prior art of Kang discloses the semiconductor device assembly of claim 6, and following up after claim 6 in view of Nam, Nam shows in Fig. 9, wherein the other molded memory assembly is electrically coupled to the substrate by a through mold via provided in the molded casing of the molded die assembly (each module has electrical connection means all the way down to the module stack, this coupled with the substrate of Kang, satisfies the limitation).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2020/0251447) in view of Kwon (US 12,191,221).
Regarding claim 8, the prior art of Kang discloses the semiconductor device assembly of claim 1, however Kang does not disclose,
“wherein at least one of:
the first molded layer exhibits a higher modulus of elasticity than the second molded layer, the first molded layer exhibits a higher coefficient of thermal expansion than the second molded layer, or the first molded layer exhibits a lower thermal conductivity than the second molded layer.”
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Kwon discloses a dual molding and chip electrical packaging scheme in Fig. 1 and in col. 7, lines 51-60, “The first and second molding portions 310 and 320 may have different material properties from each other. For example, the first and second molding portions 310 and 320 may differ from each other in thermal expansion coefficient and/or elastic modulus. For example, the thermal expansion coefficient of the first molding portion 310 may be smaller or greater than the thermal expansion coefficient of the second molding portion 320. The elastic modulus of the first molding portion 310 may be smaller or greater than the elastic modulus of the second molding portion 320.”, a teaching which satisfies,
“wherein at least one of:
the first molded layer exhibits a higher modulus of elasticity than the second molded layer, the first molded layer exhibits a higher coefficient of thermal expansion than the second molded layer, or the first molded layer exhibits a lower thermal conductivity than the second molded layer.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein at least one of:
the first molded layer exhibits a higher modulus of elasticity than the second molded layer, the first molded layer exhibits a higher coefficient of thermal expansion than the second molded layer, or the first molded layer exhibits a lower thermal conductivity than the second molded layer.”, as disclosed by Kwon in the system of Kang, for the purpose of providing a counter balancing effect during thermal events which can aid in maintaining planarity and prevention of mechanical failure. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
REASONS FOR ALLOWANCE
Claims 9-20 are allowed.
The following is an Examiner's statement of reasons for allowance: The semiconductor die stack package as recited in the claims of the instant invention fail to be taught by the prior art cited of interest.
Regarding claim 9, the prior art of Kang (US 2020/0251447) discloses in Fig. 1A, a semiconductor die stack package, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of claimed features of plural stacked NAND dies, bond wires, first mold, second mold, copper contacts, and their relative orientation to each other, in conjunction with the limitations of,
“the molded casing including a first mold surrounding a first portion of a first NAND die, of the plurality of stacked NAND dies, and a second mold surrounding a second portion the first NAND die and each additional NAND die, of the plurality of stacked NAND dies; and
… the plurality of copper contacts being disposed in the first mold.” So The first die is partially surrounded by a first mold compound, and partially surrounded by a second mold compound, as the first die is part of the die stack, see Applicant’s Fig. 3B (below), where lower die 312-1 is actually partially embedded in lower mold 316, and also partially encapsulated by upper mold compound 318.
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Regarding claim 13, the prior art of Kang (US 2020/0251447) discloses in Fig. 1A, a method of making a semiconductor die stack package, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of claimed method steps establishing the features of first die, first mold compound, second die, wire bonds, second mold compound, and their relative orientation to each other, in conjunction with the limitations of,
“surrounding a first portion of a first die with a first mold compound;
adhering at least a second die to the first die, thereby forming a die stack;
…
surrounding the die stack with a second mold compound”. So The first die is partially surrounded by a first mold compound, and partially surrounded by a second mold compound, as the first die is part of the die stack, see Applicant’s Fig. 3B (above), where lower die 312-1 is actually partially embedded in lower mold 316, and also partially encapsulated by upper mold compound 318.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893