Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to claim to priority to Provisional Application number 63/482,181.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed June 26, 2026. Claims 1, 5, 8-13, 16, and 18-19 are amended. Claims 2-4, 6-7, 14-15, 17, and 20 are cancelled. Claims 21-22 are newly added. The Examiner notes that claims 1, 5, 8-13, 16, 18-19, and 21-22 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 8-13, 16, 18-19, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Maros (US 2021/0234063 A1) in view of Li (US 2020/0161501 A1) and Jain (US 2018/0315879 A1).
With respect to claim 1, Maros teaches in Fig. 3:
Note: Although the embodiment of Fig. 3 is relied upon for this rejection, the elements of Fig. 3 are similar to the elements of the embodiments of Fig. 2 and many details are only described by Maros in the discussion of Fig. 2. Therefore, some cited passages below use reference numerals from Fig. 2 instead of Fig. 3.
A light emitting diode (LED) ([0002] “The present invention relates to multiple-junction semiconductor light emitting diodes”) comprising:
a device stack (SLD structure 301) comprising:
an n-type cladding layer (first lower cladding layer 306. In reference to Fig. 2, which has similar composition to the embodiment of Fig. 3, para. 43 describes that the SLD structures each have an n-type and a p-type cladding layer and n-layer of one structure is adjacent to the p-layer of the other with a tunnel junction between the cladding layers)
an n-type (para. 41 “in some embodiments at least a portion of the waveguiding layers 208 and 212 may be doped at a doping level lower than about 1×10.sup.17 cm.sup.−3, in order to reduce series resistance while, at the same time, minimizing waveguide optical losses associated with the presence of the dopant material.”) outer barrier layer (first lower waveguide layer 308) comprising at least one of GaAs (para. 40 “For example, the waveguiding layers 208 and 212 may be made of GaAs”);
a quantum well (first active region 310 “The active region 210 includes at least one quantum well, formed using a first semiconductor material layer formed between two barrier layers”);
a p-type (para. 41 “in some embodiments at least a portion of the waveguiding layers 208 and 212 may be doped at a doping level lower than about 1×10.sup.17 cm.sup.−3, in order to reduce series resistance while, at the same time, minimizing waveguide optical losses associated with the presence of the dopant material.”) outer barrier layer (first upper waveguide layer 312) comprising GaAs (para. 40 “For example, the waveguiding layers 208 and 212 may be made of GaAs”);
and a p-type cladding layer (first upper cladding layer 314)
an adjacent device stack (SLD structure 303) comprising n-type layers (second lower cladding layer 318, second lower waveguide layer 320); and
a tunnel junction (tunnel junction 316) positioned between the p-type cladding layer of the device stack (314 of 301) and the n-type layers (318 of 303) of the adjacent device stack (para. 43 “the tunnel junction 216 overlies and is adjacent to the first SLD structure 201. In one example, the tunnel junction 216 includes a thin highly doped n+ layer and a thin highly doped p+ layer adjacent to each other. The n+ layer is adjacent to an n-doped cladding layer of one SLD structure (of the structures 201 and 203), and the p+ layer is adjacent to a p-doped cladding layer of another SLD structure”) wherein:
the tunnel junction is configured to electrically connect the device stack and the adjacent device stack ([0002] “multiple junctions are connected by tunnel junctions”),
the LED is capable of emitting light having a wavelength between 880 nm and 1300 nm (para. 8 “this quantum well structure is characterized by an emission center wavelength in a range from about 900 nm to about 1300 nm”),
Maros fails to teach:
an n-type cladding layer comprising Ga1-vInvP, with 0.4 ≤ v ≤ 0.6, and having a thickness between greater than 25 nm and less than or equal to 200 nm;
and a p-type cladding layer comprising Ga1-vInvP, with 0.4 ≤ v ≤ 0.6, and having a thickness between greater than 25 nm and less than or equal to 200 nm;
the tunnel junction comprises a p-type layer, an n-type layer, and a second n-type layer positioned between the p-type layer and the n-type layer, and the tunnel junction is transparent to emitted light
Li teaches:
an n-type cladding layer (140 or 160, [0076] “one of the cladding layers will be p-doped and the other cladding layer will be n-doped”) comprising Ga1-vInvP, with 0.4 ≤ v ≤ 0.6, and having a thickness between greater than 25 nm and less than or equal to 200 nm;
and a p-type cladding layer (140 or 160, [0076] “one of the cladding layers will be p-doped and the other cladding layer will be n-doped”) comprising Ga1-vInvP, with 0.4 ≤ v ≤ 0.6 ([0126] “([0129] “In a preferred embodiments, the bottom cladding layer 160 is made of In.sub.0.5Ga.sub.0.5P.”), and having a thickness between greater than 25 nm and less than or equal to 200 nm (claim 15 “a first cladding layer made of In0.49Ga0.51P, the first cladding layer being between 100 nm and 300 nm thick; a second cladding layer made of In.sub.0.49Ga.sub.0.51P, the second cladding layer being between 1.00 nm and 300 nm thick;”);
Maros discloses the claimed invention except for the composition and thickness of the cladding layers. Li teaches that it is known to use GaInP with the claimed composition as n and p cladding layers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Maros to use the materials and thicknesses taught by Li for the cladding layer in order to make a cladding layer that is thin enough to avoid excess electrical resistance but thick enough to confine carriers within the well [0068 of Li] and to use a material for the cladding layer that lattice matches with GaAs and has a low recombination velocity [0102] that does not react with oxygen during processing as much as Al containing materials. See MPEP 2144.
The ranges of the thickness of Li of 100-300 nm overlaps with the claimed thickness of 20-200 nm. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to choose a thickness of the cladding layer within the range taught by Li that is also within the claimed range with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). The ordinary artisan would be motivated to optimize the thickness because thickness is known to have an effect on the transport properties and carrier confinement of the device.
Jain teaches:
the tunnel junction comprises a p-type layer, an n-type layer, and a second n-type layer positioned between the p-type layer and the n-type layer, (claim 1, “first layer comprising p-type AlGaAs; a second layer comprising n-type GaAs, wherein the second layer is a quantum well; and a third layer comprising n-type AlGaAs.”), and the tunnel junction is transparent to the emitted light.
Maros/Li discloses the claimed invention except for composition of the tunnel junction. Jain teaches that it is known to form a tunnel junction from an p-type layer and two n-type layers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Maros/Li to use the materials taught by Jain for the purpose of forming a tunnel junction that is transparent to emitted light and high tunneling current density. See MPEP 2144.
With respect to claim 5, Li further teaches:
wherein the n-type cladding layer has a bandgap greater than about 1.4 eV. (bandgap is an inherent property of a material. GaInP has a bandgap over 1.4 eV when concentrations of Ga and In are approximately equal)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Maros in view of Li and Jain as explained above.
With respect to claim 8, Li further teaches:
wherein v is about equal to 0.5 (Li teaches cladding layers with composition In0.49Ga0.51P, which is about equal to v = 0.5).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Maros in view of Li and Jain as explained above.
With respect to claim 9, Li further teaches:
wherein the p-type cladding layer has a bandgap greater than about 1.4 eV. (bandgap is an inherent property of a material. GaInP has a bandgap over 1.4 eV when concentrations of Ga and In are approximately equal)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Maros in view of Li and Jain as explained above.
With respect to claim 10, Maros further teaches:
wherein the quantum well comprises a well layer positioned between a first barrier layer and a second barrier layer (“The active region 210 includes at least one quantum well, formed using a first semiconductor material layer formed between two barrier layers”).
With respect to claim 11, Maros further teaches:
wherein for each quantum well, the well layer, the first barrier layer, and the second barrier layer are strain-balanced. (para. 50 “in related embodiments the barrier layers 410 can be dimensioned to have thicknesses between about 5 nm and about 30 nm, and can include any of AlGaAs, GaAs, GaAsN, GaAsP, and GaAsN(Sb), that are either lattice-matched or pseudomorphically strained to the substrate. The barrier layers 410 may have more than one sub-layer, with differing material compositions. In one example, the quantum wells may be characterized by compressive strain, while the barrier layers may possess tensile strain to provide a strain-compensated active region”)
With respect to claim 12, Maros further teaches:
wherein the quantum well comprises between 1 and 50 inclusively (para. 50, “the active region 406 may be configured to include n quantum wells and n+1 barrier layers, where n is an integer greater than or equal to one”.)
With respect to claim 13, Maros further teaches:
wherein both the n-type barrier layer and the p-type barrier layer comprise GaAs1-wPw and 0 ≤ w < 0.35 (para. 51)
The range of Maros overlaps with the claimed range of 0.01 < w < 0.5. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to choose a value for w with routine experiment and optimization for the purpose of tuning the bandgap and improving lattice matching. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
With respect to claim 16, Jain further teaches:
wherein the second n-type layer of the tunnel junction comprises GaAs. (claim 1, “a second layer comprising n-type GaAs”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Maros in view of Li and Jain as explained above.
With respect to claim 18, Jain further teaches:
Wherein the second n-type layer of the tunnel junction has a thickness between 3 nm and 20 nm (The exemplary example of Fig. 1 of Jain teaches the second n-type layer (GaAs layer) with a thickness of 6 nm)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Maros in view of Li and Jain as explained above.
With respect to claim 19, Jain further teaches:
wherein the p-type layer of the tunnel junction comprises Al1-yGayAs and 0.2 ≤ y ≤ 1. (The exemplary example of Fig. 1 of Jain teaches Al0.6Ga0.4As as the p-type layer)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Maros in view of Li and Jain as explained above.
With respect to claim 21, Jain further teaches:
wherein the n-type layer of the tunnel junction comprises Al1-kGakAs and 0.2 ≤ k ≤ 1. (The exemplary example of Fig. 1 of Jain teaches Al0.5Ga0.5As as the n-type layer)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Maros in view of Li and Jain as explained above.
With respect to claim 22, Jain teaches:
wherein each of the n-type layer and the p-type layer of the tunnel unction is doped to about from about 1×1018 cm−3 to about 1×1020 cm−3 (wherein the first layer, the second layer and the third layer are doped with Se, Si, Te or any combination thereof at a concentration of from about 1×1018 cm−3 to about 1×1020 cm−3)
The range of Jain overlaps with the claimed range of about 1x1019cm-3. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to choose a value of doping concentrations within the tunnel junction with routine experiment and optimization for the purpose of tuning the current density within the tunnel junction. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Response to Arguments
Applicant’s arguments with respect to claims 1 and its dependents have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Rejection of claim 14 under 35 U.S.C. §112(a) is made moot as claim 14 is now cancelled.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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