DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Leobandung (U.S. Pub #2019/0043812), in view of Clegg et al (U.S. Pub #2018/0068980), in view of Kariyazaki et al (U.S. Pub #2019/0363050).
With respect to claim 1, Leobandung teaches a semiconductor package comprising:
a substrate (Fig. 5, 30);
a first semiconductor structure (Fig. 5, 100) on the substrate, wherein the first semiconductor structure includes:
a first redistribution layer structure (see Fig. 3, 16+18; Paragraph 19), and
a first semiconductor die (Fig. 3, 10 and Paragraph 21-23) that is disposed on the first redistribution layer structure and includes a plurality of first through-semiconductor vias (Fig. 3, 22) extending between a bottom surface of the first semiconductor die facing the substrate and a top surface of the first semiconductor die facing away from the substrate;
a second semiconductor structure (Fig. 5, 102) disposed side by side with the first semiconductor structure on the substrate, wherein the second semiconductor structure includes:
a second redistribution layer structure, and
a second semiconductor die that is disposed on the second redistribution layer structure and includes a plurality of second through-semiconductor vias extending between a bottom surface of the second semiconductor die facing the substrate and a top surface of the second semiconductor die facing away from the substrate;
a plurality of bonding wires (Fig. 5, 34 and Paragraph 34) electrically connecting the first semiconductor die and the second semiconductor die, the plurality of bonding wires on the top surface of the first semiconductor die and on the top surface of the second semiconductor die.
Leobandung does not teach an electrical routing layer in the substrate and electrically connecting the first semiconductor die to the second semiconductor die.
Clegg teaches an electrical routing layer (Fig. 16B, 1615) in a substrate (Figs. 16B and 15, 705) and electrically connecting a first semiconductor die to a second semiconductor die (Figs. 16B and 15, 100 and 200).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide an electrical routing layer in the substrate of Leobandung to connect the first and second semiconductor dies as taught by Clegg in order to establish die to die communication (Paragraph 70-71).
Leobandung and Clegg teach the first semiconductor die and the second semiconductor die are connected to exchange a second type of signal through the plurality of bonding wires (Paragraph 43 and 71 of Clegg);
wherein the second type of signals are relatively high speed signals exchanged through the plurality of bonding wires at a relatively faster speed than the first type of signals (Paragraph 43 and 71 of Clegg).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to exchange a signal through the substrate and to exchange a signal through the plurality of bonding wires as taught by Clegg in order to provide high speed connections using the bonding wires (Paragraph 43).
Leobandung and Clegg do not teach wherein the first semiconductor die and the second semiconductor die are connected to exchange a first type of signal through the substrate between bottom surfaces of the first semiconductor die and second semiconductor die,
the first type of signals, which are relatively low speed signals having a relatively lower speed than the relatively high speed signals, and are exchanged through the electrical routing layer in the substrate at a relatively slower speed.
Kariyazaki teaches that relatively low speed signals having a relatively lower speed than relatively high speed signals, can be exchanged through an electrical routing layer (Fig. 1, SGPR) in a substrate at a relatively slower speed (Paragraph 66 and 70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to exchange relatively low speed signals through the electrical routing layer in the substrate of Clegg as taught by Karayazaki in order to achieve predictable result of transmitting a one-way/single-ended signal (Paragraph 70).
With respect to claim 2, Karayazaki teaches that the speed of the signal is defined by the frequency (Paragraphs 69, 345-346, etc.), hence that the first type of signals are relatively low frequency signals and the second type of signals are relatively high frequency signals having a higher frequency than the relatively low frequency signals.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed configure the first type signals as low frequency and the second type signals as high frequency as taught by Karayazaki in order to achieve predictable result of transmitting a high speed signal at 60 Gbps (Paragraph 65-66)
With respect to claim 4, Leobandung teaches a molding material (Fig. 6, 36 and Paragraph 36) molding the first semiconductor structure, the second semiconductor structure, and the plurality of bonding wires on the substrate.
With respect to claim 5, Leobandung teaches that the plurality of bonding wires include first to N-th sets of bonding wires (where N is a natural number of 2 or more) (Fig. 5, i.e. three sets of wires 34 are depicted), and the first to N-th sets of bonding wires are sequentially disposed from lower to higher heights above the substrate (Fig. 5, i.e. inner wires 34 are lowest; outer wires 34 are highest).
With respect to claim 6, Leobandung teaches that the plurality of bonding wires (Fig. 5, 34) connect a back side of the first semiconductor die (Fig. 5, i.e. the side away from the active regions 12), and a back side of the second semiconductor die.
With respect to claim 7, Leobandung teaches a front side of the first semiconductor die (Fig. 5, i.e. the side of 10 comprising active region 12) contacts an upper surface of the first redistribution layer structure (Fig. 5, i.e. top surface of 16+18), and a front side of the second semiconductor die contacts an upper surface of the second redistribution layer structure.
With respect to claim 9, Leobandung teaches that the plurality of bonding wires include at least one of gold, silver, copper, and an alloy thereof (Paragraph 34).
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Leobandung, Clegg, and Kariyazaki, in view of Song et al (U.S. Pub #2012/0068306).
With respect to claim 3, Leobandung, Clegg, and Kariyazaki does not teach that the first type of signals are wireless communication signals, and the second type of signals are processing signals.
Clegg teaches that the second type of signals are processing signals can be processing signals (Paragraph 27).
Song teaches that the first type of signals (i.e. high speed signals between chips) can be wireless communication signals (Paragraph 136, i.e. high speed signals operating in a wireless device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the first type of signal as wireless communication signals, and the second type as processing signals as taught by Clegg and Song in order to achieve the predictable result of implement a wireless device (Paragraph 136 of Song).
Claim 10-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Leobandung, in view of Clegg et al (U.S. Pub #2018/0068980), Kariyazaki et al (U.S. Pub #2019/0363050), in view of Yim et al (U.S. Pub #2021/0257305).
With respect to claim 10, Leobandung does not teach that the substrate is an Ajinomoto build-up film (ABF) substrate.
Yim teaches a substrate (Fig. 1A, 140) for a chip structure (Fig. 1A, 112), wherein the substrate is an Ajinomoto build-up film (ABF) substrate (Paragraph 28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the substrate of Leobandung as an ABF structure as taught by Yim in order to achieve the predictable result of supporting the chip and routing signals/connections to lower substrate contacts (Fig. 1A, 190).
With respect to claim 11, Leobandung teaches a semiconductor package comprising:
a substrate (Fig. 5, 30);
a first semiconductor structure (Fig. 5, 100) on the substrate, wherein the first semiconductor structure includes:
a first redistribution layer structure (see Fig. 3, 16+18; Paragraph 19),
a plurality of first connection terminals (Fig. 5, 28’ and Paragraph 30) electrically connecting the first redistribution layer structure to the substrate, and
a first semiconductor die (Fig. 3, 10 and Paragraph 21-23) that is disposed on the first redistribution layer structure and includes a plurality of first through-semiconductor vias (Fig. 3, 22) extending between a bottom surface of the first semiconductor die facing the substrate and a top surface of the first semiconductor die facing away from the substrate;
a second semiconductor structure (Fig. 5, 102) disposed side by side with the first semiconductor structure on the substrate, wherein the second semiconductor structure includes:
a second redistribution layer structure, a plurality of second connection terminals electrically connecting the second redistribution layer structure to the substrate, and
a second semiconductor die that is disposed on the second redistribution layer structure and includes a plurality of second through-semiconductor vias extending between a bottom surface of the second semiconductor die facing the substrate and a top surface of the second semiconductor die facing away from the substrate; and
a plurality of bonding wires (Fig. 5, 34 and Paragraph 34) electrically connecting the first semiconductor die and the second semiconductor die on the first semiconductor die and the second semiconductor die, the plurality of bonding wires on the top surface of the first semiconductor die and on the top surface of the second semiconductor die.
Leobandung does not teach
a first insulating member surrounding the plurality of first connection terminals between the substrate and the first redistribution layer structure,
a second insulating member surrounding the plurality of second connection terminals between the substrate and the second redistribution layer structure.
Yim teaches a first insulating member (Fig. 1A, 135 and Paragraph 34) surrounding the plurality of first connection terminals between a substrate and a chip structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide first and second insulating members in Leobandung as taught by Yim in order to provide an underfill between the chip structure and the substrate (Paragraph 34).
Leobandung and Clegg teach the first semiconductor die and the second semiconductor die are connected to exchange a second type of signal through the plurality of bonding wires (Paragraph 43 and 71 of Clegg);
wherein the second type of signals are relatively high speed signals exchanged through the plurality of bonding wires at a relatively faster speed than the first type of signals (Paragraph 43 and 71 of Clegg).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to exchange a signal through the substrate and to exchange a signal through the plurality of bonding wires as taught by Clegg in order to provide high speed connections using the bonding wires (Paragraph 43).
Leobandung and Clegg do not teach wherein the first semiconductor die and the second semiconductor die are connected to exchange a first type of signal through the substrate between bottom surfaces of the first semiconductor die and second semiconductor die,
the first type of signals, which are relatively low speed signals having a relatively lower speed than the relatively high speed signals, and are exchanged through the electrical routing layer in the substrate at a relatively slower speed.
Kariyazaki teaches that relatively low speed signals having a relatively lower speed than relatively high speed signals, can be exchanged through an electrical routing layer (Fig. 1, SGPR) in a substrate at a relatively slower speed (Paragraph 66 and 70).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to exchange relatively low speed signals through the electrical routing layer in the substrate of Clegg as taught by Karayazaki in order to achieve predictable result of transmitting a one-way/single-ended signal (Paragraph 70).
With respect to claim 12, Leobandung teaches that
the first semiconductor die includes a plurality of first upper connection pads (Fig. 5, 26);
a lower surface of each of the plurality of first upper connection pads contacts a respective first through-semiconductor via (Fig. 5, 22) of the plurality of first through-semiconductor vias, and an upper surface of each of the first upper connection pads is exposed from an upper surface of the first semiconductor die;
the second semiconductor die includes a plurality of second upper connection pads (Fig. 5, 26); and a lower surface of each of the plurality of second upper connection pads contacts a respective second through-semiconductor via (Fig. 5, 22) of the plurality of second through-semiconductor vias, and an upper surface of each of the second upper connection pads is exposed from an upper surface of the second semiconductor die.
With respect to claim 13, Leobandung teaches that a first end of each of the plurality of bonding wires is connected to the upper surface of a respective first upper connection pad (Fig. 5, 26 and Paragraph 34), and a second end of each of the plurality of bonding wires is connected to the upper surface of a respective second upper connection pad (Fig. 5, 26).
With respect to claim 14, Leobandung teaches that the plurality of first connection terminals and the plurality of second connection terminals include micro bumps (Fig. 5, 28’ and Paragraph 30).
With respect to claim 16, Leobandung does not teach that the first insulating member and the second insulating member include a non- conductive film (NCF).
Yim teaches a first insulating member includes a non-conductive film (NCF) (Fig. 1A, 135 and Paragraph 34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide first and second insulating members in Leobandung as taught by Yim in order to provide an underfill between the chip structure and the substrate (Paragraph 34).
With respect to claim 17, Leobandung teaches a molding material (Fig. 6, 36 and Paragraph 36) surrounding the plurality of bonding wires and through which the plurality of bonding wires pass.
With respect to claim 18, Leobandung does not teach that adjacent first connection terminals (Fig. 5, 28’) among the plurality of first connection terminals and adjacent second connection terminals among the plurality of second connection terminals have first pitches;
adjacent first through-semiconductor vias (Fig. 5, e.g. vias on left side of structure 10) among the plurality of first through- semiconductor vias and adjacent second through-semiconductor vias among the plurality of second through-semiconductor vias have second pitches; and
the first pitch is greater than the second pitch.
With respect to claim 19, Leobandung teaches that the plurality of bonding wires include a first set of bonding wires (Fig. 5, e.g. lower wire 34) that reaches a first height above a top surface of the substrate, and a second set of bonding wires (Fig. 5, e.g. top wire 34) that reaches a second height above the top surface of the substrate, the second height being higher than the first height.
With respect to claim 20, Leobandung teaches
the first set of bonding wires (Fig. 5, e.g. lower wire 34) include first bonding wires each having a first length and the second set of bonding wires (Fig. 5, e.g. top wire 34) include second bonding wires each having a second length greater than the first length.
Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over Leobandung, Clegg, and Kariyazaki, in view of Lo et al (U.S. Pub #2021/0118846).
With respect to claim 8, Leobandung does not teach that at least one of the first semiconductor die and the second semiconductor die includes a system on chip (SOC).
Lo teaches a first semiconductor die that includes a system on chip (Paragraph 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure one of the first and second dies of Leobandung to include a SoC as taught by Lo in order to implement a system in package device (Paragraph 24).
Claim 15 rejected under 35 U.S.C. 103 as being unpatentable over Leobandung, Clegg, Kariyazaki, and Yim, in view of Sun et al (U.S. Pub #2022/0320026).
With respect to claim 15, Leobandung does not teach that the first insulating member and the second insulating member include a molded underfill (MUF).
Sun teaches a first insulating member including a molded underfill (MUF) (Paragraph 49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide first and second insulating members including a MUF in the structure of Leobandung as taught by Sun in order to achieve the predictable result of simultaneously providing an underfill and encapsulation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812
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