DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on Jan. 08, 2024 and Dec. 20, 2024 were filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner suggests the following title “SEMICONDUCTOR STRUCTURE WITH BACKSIDE THROUGH SUBSTRATE THERMAL CONDUCTIVE VIAS, AND HEAT DISSIPATION LAYER WITH PLURALITY OF OPENINGS.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0066284 A1; hereinafter referred to as Huang) in view of Lin (US 2018/0145011 A1; hereinafter referred to as Lin).
Regarding claim 1, Huang discloses a method (fig. 4-12), comprising:
receiving a workpiece (fig 5, 500) including a device layer (110) disposed on a first side of the workpiece (500);
forming a first interconnect structure (108) over the device layer (110);
attaching a substrate (fig 8, carrier substrate 102) over the first interconnect structure (108);
etching from a second side (Fig. 10 annotated below, Back side 112b) of the workpiece to form at least one first trench (1004-T1) and at least one second trench (1004-T2), …
forming a first conductive feature (annotated fig 12 below, 122-V1) in the first trench (1004-T1) and a second conductive feature (122-V2) in the second trench (1004-T2);
forming a second interconnect structure (114) over the first conductive feature (122-V1) and the second conductive feature (122-V2); and
Huang does not disclose
wherein the first trench extends partially into the substrate for a first distance, the second trench extends partially into the substrate for a second distance, and the first distance is smaller than the second distance;
thinning the substrate from the first side of the workpiece to expose the second conductive feature, wherein the first conductive feature remains partially embedded in the substrate.
Lin teaches a three-dimensional semiconductor structure including through-substrate vias, and is therefore analogous art, specifically Lin teaches (fig. 2A, 2B, 2C) a workpiece (300’) with at least one first trench (400) and at least one second trench (400b)
wherein the first trench (400) extends partially into the substrate (combination of wafers 100- 200) for a first distance (fig 2A, D1), the second trench (400b) extends partially into the substrate (combination of wafers 100-200) for a second distance (fig 2A, D2), and the first distance (D1) is smaller (D1<D2) than the second distance (D2);
thinning the substrate (combination of wafers 100-200) from the first side (Examiner note: instant application has thinning from the front side, Lin teaches thinning from both front and back sides, see “thinning a front side of … wafer” [Abstract] and in fig. 2D “wafer … is thinned from bottom surface” [0040] ln 01-02) of the workpiece (300’) to expose the second conductive feature (430b), wherein the first conductive feature (430) remains partially embedded in the substrate (combination of wafers 100-200).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ interconnects and a device layer as disclosed by Huang, and to include conductive vias of different lengths as disclosed by Lin because conductive vias of different lengths enable vertical connections between stacked layers, tailoring interconnect lengths for better performance (for example, shorter vias minimize parasitic effects such as capacitance/inductance) which is crucial for high-speed signals and compact designs. Also, conductive vias of different lengths enable specialized routing such as thermal dissipation (for example, a blind via is a semiconductor manufacturing term used for a conductive via that assists with heat dissipation).
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Regarding claim 2, Huang in view of Lin disclose the method of claim 1. Huang does not disclose
wherein the first trench includes a first trench width, the second trench includes a second trench width, and the first trench width is smaller than the second trench width.
Lin further discloses (fig 2A, 2B, 2C)
wherein the first trench (400) includes a first trench width (W1), the second trench (400b) includes a second trench width (W3), and the first trench width (W1, “W1 in a range from 0.025 microns to about 4 microns” [0030] ln 01-02) is smaller (W1<W3) than the second trench width (W3, “W3 in a range from about 0.3 microns to about 10 microns” [0038] ln 01-02). Examiner interprets W1<W3 using endpoints of W1 and W3, namely 0.025 < 0.3 at lower end or 4 < 10 microns at upper end. Examiner note: in addition, the width W3 of 400b is necessarily wider than the width of W1 of 400 because deeper vias have a larger diameter than shallower vias in order to maintain manageable aspect ratios during manufacturing.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ vias as disclosed by Huang, and to include vias of different depths (and widths to maintain manageable aspect ratios) as disclosed by Lin because vias of different depths enable vertical connections between stacked layers, tailoring interconnect lengths for better performance. Vias of different depths also enable specialized routing such as thermal dissipation (for example, a blind via is a semiconductor manufacturing term used for a via that assists with heat dissipation.
Regarding claim 3, Huang in view of Lin disclose the method of claim 1. Huang further discloses
wherein the first trench and the second trench are formed simultaneously (“a patterning process is performed … thereby defining a plurality of openings 1004” [0047] ln 08-09, also see fig 10.)
Regarding claim 4, Huang in view of Lin disclose the method of claim 1. Huang does not disclose
wherein the first trench and the second trench are formed separately.
Lin further discloses
wherein the first trench and the second trench are formed separately (“after the first TSV opening is formed, a second TSV opening is formed” [0037] ln 08-09).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ via trenches as disclosed by Huang, and to include via trenches that are etched separately as taught by Lin because vias of different depths as taught by Lin have to be etched separately because the dry etching process that is primarily used to etch via trenches produces a constant etch rate, therefore a deeper trench and a narrower trench have to be etched separately in order to ensure that vias of different depths are produced.
Regarding claim 7, Huang in view of Lin disclose the method of claim 1. Huang further discloses (see annotated fig 10 above in claim 1)
wherein each of the first (1004-T1) and second trenches (1004-T2) extends through the device layer (110) and the first interconnect structure (108, examiner interprets that 1004-T1 and 1004-T2 extend a certain distance through 108).
Claims 5-6 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0066284 A1; hereinafter referred to as Huang) in view of Lin (US 2018/0145011 A1; hereinafter referred to as Lin).
Regarding claim 5, Huang in view of Lin discloses the method of claim 1. Huang further discloses
wherein the forming of the second interconnect structure (114) includes:
prior to the forming of the first trench (1004-T1, see above claim 1 annotated fig. 10) and the second trench (1004-T2), forming a first portion of the second interconnect structure (1002, “1002 … is part of the second interconnect structure 114” [0049] ln 06-07); and
after the forming of the first conductive feature (122-V1, see above in claim 1 annotated fig. 12) and the second conductive feature (122-V2), forming a second portion of the second interconnect structure (the rest of 114), wherein the second portion of the second interconnect structure (the rest of 114) covers the first conductive feature (122-V1) and the second conductive feature (122-V2).
Regarding claim 6, Huang in view of Lin discloses the method of claim 1. Huang does not disclose
wherein the forming of the second interconnect structure (114) includes:
after the forming of the first conductive feature (122-V1, see above in claim 1 annotated fig. 12), forming a first portion of the second interconnect structure (116, “interconnect structure 114 comprises … vias 118, and … wires 116” [0018] ln 01-04); and
after the forming of the second conductive feature (122-V2), forming a second portion (118) of the second interconnect structure (114), wherein the first (116) and second portions (118) of the second interconnect structure (114) cover the first conductive feature (122-V1), and the second portion (118) of the second interconnect structure (114) covers the second conductive feature (122-V2).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0066284 A1; hereinafter referred to as Huang) in view of Lin (US 2018/0145011 A1; hereinafter referred to as Lin) further in view of Cheng et al. (US 2021/0082784 A1; hereinafter referred to as Cheng).
Regarding claim 8, Huang in view of Lin disclose the method of claim 1. Huang in view of Lin does not disclose
wherein the first conductive feature is configured to dissipate heat from the device layer, and the second conductive feature is configured to transmit power or signal.
Cheng teaches a three-dimensional semiconductor structure including through-substrate vias, and is therefore analogous art, specifically Cheng teaches (fig. 1)
wherein the first conductive feature (148A) is configured to dissipate heat from the device layer (Thermally conductive TSV 148A dissipates heat” [0028] ln 20-22), and the second conductive feature (148B) is configured to transmit power or signal (“electrically conductive TSV 148B propagates electrical signals” [0028] ln 20-22).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ interconnects, a device layer, and trenches of different depths as disclosed by Huang in view of Lin, and to utilize different vias for dissipating heat and transmitting signals as taught by Cheng because heat dissipation structures such as vias assist in the reduction of thermo-mechanical stress leading to increases reliability of 3D semiconductor structures [0016, 0017]. Examiner note: Cheng’s thermally conductive vias (148A) and electrically conductive vias (148B) are structurally the same except that the thermally conductive vias are connected to heat dissipation layers as alluded by Cheng in “thermally conductive TOV and/or TSV 148A represented with a cross hatched pattern is similar to an electrically conductive TOV and/or TSV 148B shaded gray but has a different function” [0028] ln 22-25.
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0066284 A1; hereinafter referred to as Huang) in view of Lin (US 2018/0145011 A1; hereinafter referred to as Lin) further in view of Huang et al. (US 2023/0079072 A1; hereinafter referred to as Huang_072).
Regarding claim 9, Huang in view of Lin disclose the method of claim 1. Huang in view of Lin does not disclose
wherein the workpiece is a first workpiece, the method further comprising:
bonding a second workpiece to the first side of the first workpiece, wherein the second conductive feature electrically connects to circuitries formed in the second workpiece.
Huang_072 teaches a 3D semiconductor structure containing vias, and is therefore analogous art, specifically Huang_072 teaches (fig. 10)
wherein the workpiece is a first workpiece (semiconductor die 100), the method further comprising:
bonding (“bonding between first semiconductor die 100 and second semiconductor die 200” [0099] ln 06) a second workpiece (semiconductor die 200) to the first side of the first workpiece (semiconductor die 100), wherein the second conductive feature (via 119) electrically connects (using 211-3) to circuitries formed in the second workpiece (semiconductor die 200).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ interconnects, a device layer, and trenches of different depths as disclosed by Huang in view of Lin, and to bond a second workpiece to the first workpiece in order to electrically connect them as taught by Huang_072 because “the electrical paths between different dies may be significantly reduced … the power consumption … may be reduced. In addition, separating the control circuit from the memory dies may reduce the complexity of manufacturing” [0127] ln 01-06.
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0066284 A1; hereinafter referred to as Huang) in view of Lin (US 2018/0145011 A1; hereinafter referred to as Lin) further in view of Tai et al. (US 2021/0098636 A1; hereinafter referred to as Tai).
Regarding claim 10, Huang in view of Lin discloses the method of claim 1. Huang in view of Lin does not disclose
wherein the substrate is a carrier wafer.
Tai teaches a three-dimensional semiconductor structure including through-substrate vias and substrate thinning, and is therefore analogous art, specifically Tai teaches (fig 4-5)
wherein the substrate is a carrier wafer (“carrier C is glass substrate” [0014] ln 03-04).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ interconnects, a device layer, and trenches of different depths as disclosed by Huang in view of Lin, and to utilize a carrier substrate as taught by Tai because a carrier substrate can withstand various “manufacturing processes while supporting the elements formed thereon” ([0014] ln 04-05).
Claims 17, and 19-20 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0066284 A1; hereinafter referred to as Huang) in view of Takahashi et al. (US 2011/0233702 A1).
Regarding claim 17, Huang discloses a semiconductor device (annotated fig. 1 below), comprising:
a device layer (110) including transistors (120);
a frontside interconnect structure (108) disposed on the device layer and electrically coupled to the transistors (using 118);
a semiconductor layer (106, [0020] indicates that 106 may comprise silicon carbide, examiner interprets SiC as well-known wide-bandgap semiconductor) disposed on the frontside interconnect structure;
a backside interconnect structure (114) disposed under the device layer (110) and electrically coupled to the transistors (using 118);
a plurality of first vias (V1A, V1B, see annotated fig 1 below showing repeating structure necessarily present on a full sized wafer) extending through the device layer (110) and the frontside interconnect structure (108, examiner interprets that V1 extends a certain distance through 108), … ; and
a plurality of second vias (V2) extending through the device layer (110), the frontside interconnect structure (108, examiner interprets that V2 extends a certain distance through 108), …
Huang does not disclose
… wherein the first vias are covered by the semiconductor layer (106);
a plurality of second vias extending through … the semiconductor layer.
Huang’s embodiment (annotated fig 3 below) discloses
… wherein the first vias (V1) are covered by the semiconductor layer (302);
It would have been obvious to one ordinary skill in the art before the effective filling date of the claimed invention to employ first vias as disclosed by Huang’s first embodiment, and to utilize first vias covered by a semiconductor layer as taught by Huang’s second embodiment because a semiconductor layers covering vias are utilized to create the upper input/output structure of three-dimensional integrated circuits as alluded to by Huang in “an upper I/O structure 304 overlies the upper semiconductor wafer 302. The upper I/O structure 304 may be electrically coupled to the upper IC structure 308 and/or the lower IC structure 306” [0032] ln 12-15.
Huang’s first embodiment in view of Huang’s secondary embodiment does not disclose
a plurality of second vias extending through … the semiconductor layer.
Takahashi teaches a semiconductor structure including vias of different dimensions, and is therefore analogous art, specifically Takahashi teaches (annotated fig. 4 below)
Plurality of second vias (V2) extending through … the semiconductor layer (32, Note: Takahashi teaches V2 passing through device layer consisting of Tr1-Tr4, through interconnect structure 41, and through semiconductor layer 32)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ interconnects, a device layer, and vias extending through a device layer and interconnect structure as disclosed by Huang, and to utilize a via that also extends through a semiconductor layer as taught by Takahashi because a via that extends through a device layer, interconnect structure, and semiconductor layer enables high-density vertical three-dimensional integration, increased connectivity and bandwidth between different functional layers, and reduced overall footprint due to reduced number of lateral connections.
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Regarding claim 19, Huang in view of Takahashi discloses the semiconductor device of claim 17. Huang further discloses (see annotated fig. 1 shown in claim 17 above)
wherein the second vias (V2) are partially embedded in the backside interconnect structure (114).
Regarding claim 20. Huang in view of Takahashi discloses the semiconductor device of claim 17. Huang does not disclose
wherein the first vias have a width smaller than the second vias.
Takahashi further discloses (see annotated fig. 4 shown in claim 17 above)
wherein the first vias (V1) have a width smaller (Abstract refers to different sizes of via cross sections, see also [0016] ln 06-07) than the second vias (V2).
It would have been obvious to one ordinary skill in the art before the effective filling date of the claimed invention to employ vias as disclosed by Huang and to utilize vias of different widths as taught by Takahashi because Takahashi discloses that as the via width becomes larger, “for the same exposure to the etching process, the etched depth will be greater” [0135] ln 04-05, which is beneficial for etching deeper vias in a reduced amount of time.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0066284 A1; hereinafter referred to as Huang) in view of Takahashi et al. (US 2011/0233702 A1; hereinafter referred to as Takahashi) further in view of Fisch et al. (US 2013/0032934 A1); hereinafter referred to as Fisch).
Regarding claim 18, Huang in view of Takahashi discloses the semiconductor device of claim 17. Huang in view of Takahashi does not disclose
wherein the first vias are partially embedded in the semiconductor layer.
Fisch teaches blind vias for the purpose of heat dissipation in a semiconductor structure, and is therefore analogous art, specifically Fisch teaches (fig. 1A)
wherein the first vias (150, “blind vias 150” [0038] ln 01) are partially embedded in the semiconductor layer (130, “semiconductor … 130” [0038] ln 01).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ vias extending through a device layer, interconnect structure, and semiconductor layer as taught by Huang in view of Takahashi, and to include vias that are partially embedded in the semiconductor layer as taught by Fisch because “blind vias … actively and conductively distribute, transfer, and/or dissipate the heat generated by the semiconductor device” [Fisch, 0038] ln 01-02.
Allowable Subject Matter
Claims 11-16 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method comprising:
etching from the backside of the workpiece to form a plurality of first trenches and a plurality of second trenches, wherein the first trenches extend through the device layer and the frontside interconnect structure and stop at the heat dissipation layer, and the second trenches extend through the device layer, the frontside interconnect structure, and the openings in the heat dissipation layer, and partially into the semiconductor layer;
Claims 12-16 depend from claim 11, and therefore, are allowable for the same reason as claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN OSCAR RIVAS whose telephone number is (571)272-5529. The examiner can normally be reached M-F 0900-0500.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached on (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R./
Examiner, Art Unit 2812
03 Mar. 2026
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812