Detailed Correspondence
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicants’ submission, filed on 06/03/2026, addressing rejection of claims 1-20 from the non-final office action (04/08/2026), by amending claims 1-2, 6-16, and 19-20 and cancelling claim 5 is entered and will be addressed below.
Claim Interpretations
The following is considered an intended use of the apparatus:
The “A semiconductor processing apparatus” of claims 1, 14, and 19,
“wherein the cycle comprises a first time at which the bias voltage has a voltage level, different from a ground level, and a second time at which the bias voltage has the ground level, and wherein the voltage supply is configured to determine the voltage level based on the process gas” of claim 17,
It has been held that claim language that simply specifies an intended use or field of use for the invention generally will not limit the scope of a claim (Walter, 618 F.2d at 769, 205 USPQ at 409; MPEP 2106). Additionally, in apparatus claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim (In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963); MPEP2111.02). When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent (In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977); MPEP 2112.01).
The “wherein the at least one voltage supply is configured to output the first bias voltage as a voltage having a first cycle, and to output the second bias voltage as a voltage having a second cycle” of claim 11, the first cycle and the second cycle may or may not be the same. If the first cycle and the second cycle are different, they may differ in the voltage level, the repeating rate (frequency), or differ in waveform.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ventzek et al. (US 20200058470, hereafter ‘470), in view of Paterson et al. (US 20140302678, hereafter ‘678) and Libby et al. (US 20020170675, hereafter ‘675).
‘470 also teaches some limitations of:
Claim 14: plasma etching and plasma deposition are common process steps during semiconductor device fabrication ([0004], 2nd sentence, includes the claimed “A semiconductor processing apparatus, comprising”):
a plasma processing chamber 1210 (Fig. 12, [0102]), the BP coupling element 19 is a substrate holder and is an electrostatic chuck ([0053], last sentence, includes the claimed “a chamber; an electrostatic chuck included in the internal space of the chamber”);
a plasma processing system 200 includes an SP coupling element 15 coupled to a plasma processing chamber 210 ([0052], description of Fig. 2 applicable to Fig. 12), FIG. 4 illustrates a schematic timing diagram of an example method of control for plasma processing including a high frequency radio frequency (RF) source power pulse and a low frequency RF bias power pulse in accordance with an embodiment of the invention ([0012], includes the claimed “a beam source including a head defining a plasma space, a bias electrode on the head and configured to receive radio frequency (RF) power”),
The GCP control path 1205 provides power to the plasma 60 using an electrically conductive grid 1218 ([0102], last sentence), the electrically conductive grid 1218 may be positioned between the plasma 60 and the workpiece surface ([0106], includes the claimed “and at least one grid electrode below the head, the at least one grid electrode each having a plurality of through-holes” and as shown in Fig. 12 and “wherein the at least one grid electrode includes a base plate comprising a first material having conductivity”).
‘470 is silent on other details of the SP coupling element 15. ‘470 does not expressly teaches the other limitations of:
Claim 14: (14A) (a beam source including a head defining a plasma space) configured for process gas to be supplied thereto, (a bias electrode on the head and configured to receive radio frequency (RF) power);
a gas supply configured to supply the process gas to the beam source,
and a cover layer covering a surface of the base plate and comprising a second material, different from the first material, and
(14B) wherein the beam source is configured such that an angle of an emission from the beam source to the electrostatic chuck is adjustable.
Claim 18: wherein the second material contains a metal oxide dielectric.
‘470 also teaches The optional SP impedance matching network 25 may be omitted in certain plasma processing systems such as when the SP coupling element 15 is a resonant structure inductively coupled to the plasma 60 ([0056], 3rd sentence).
‘678 is analogous art in the field of INTERNAL PLASMA GRID APPLICATIONS FOR SEMICONDUCTOR FABRICATION (title), The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio (abstract), an inductively coupled plasma source ([0003]). ‘678 teaches that A coil 133 is positioned above the window 111 (Fig. 1, [0156]), Process gases may be supplied through a main injection port 160 positioned in the upper chamber ([0157]), Non-limiting examples of grid structures are shown in FIGS. 2A, 2B and 3A-3D … the grid contains one or more materials including, but not limited to, metals, metallic alloys such as stainless steel, aluminum, titanium, ... The material may or may not be anodized or otherwise passivated for, e.g., corrosion resistance … a grid may be coated with a pure coating including, but not limited to, coatings of Y2O3 … the grid may be grounded, floating or biased ([0049]).
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have adopted coil 133, window 111, and gas injection port 160 of ‘678 as inductive coupled plasma and an anodized aluminum or metal coated Y2O3, as taught by ‘678, as the grid 1218 of ‘470 (the limitations of 14A and 18), for the purpose of corrosion resistance, as taught by ‘678 ([0049]).
‘675 is analogous art in the field of Focused Particle Beam Systems And Methods Using A Tilt Column (title), for semiconductor ([0016]), Present focused ion beam (FIB) systems typically include an ion beam column oriented normal to the workpiece and a tilting work stage ([0002]). ‘675 teaches that The system 10 illustrated in FIG. 1 with a tilted ion beam column 12 can etch a cavity in a sample to create a vertical cross-section and then image the vertical cross-section without tilting the work stage assembly 25 ([0049]), The work stage assembly is much smaller when it does not include a tilt assembly. A smaller stage assembly results in a smaller footprint, shown schematically in FIG. 5, for the particle beam system. A smaller footprint results in considerable savings because cleanroom fabrication space is expensive ([0057]).
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have added tilting capability of ‘675, to the SP coupling element 15 of ‘470 (the limitation of 14B), for the purpose of etching a cavity with a vertical cross-section, as taught by ‘675 ([0049]) and smaller foot print ([0057]).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over ‘470, ‘678, and ‘675, as been applied to claim 14 rejection above, further in view of DIVERGILIO et al. (US 20150255242, hereafter ‘242).
The combination of ‘470, ‘678, and ‘675 further teaches some limitations of:
Claim 15: Referring to FIG. 13, a timing diagram 1300 includes a source power 1, a bias power 2, and a grid control power 1305 which are pulsed to generate and deliver ions to a microelectronic workpiece. Timing diagram 1300 includes an additional pulse sequence including SP GCP pulses 1311 and BP GCP pulses 1312 (‘470, [0108], includes the claimed “further comprising: a voltage supply”),
one or more of the SP pulse modulation circuit 51, the BP timing circuit 52, an optional BP pulse modulation circuit 53, the optional GCP timing circuit 1258, and the optional GCP pulse modulation circuit 1259 may be included in a controller 1250. As with previously described controllers, controller 1250 may be positioned locally or remotely relative to the plasma processing chamber 1210 (Fig. 12, [0105], includes the claimed “processing circuitry configured to control the voltage supply“).
The combination of ‘470 and ‘678 does not teach the other limitations of:
Claim 15: wherein the at least one grid electrode comprises a plurality of grid electrodes, and
the processing circuitry is configured to control the voltage supply to supply a bias voltage having a cycle to at least one grid electrode, from among the plurality of grid electrodes, and to supply a DC voltage having a constant voltage level to another grid electrode, from among the plurality of grid electrodes.
Claim 16: wherein the another grid electrode is between the electrostatic chuck and the at least one grid electrode.
Claim 17: wherein the cycle comprises a first time at which the bias voltage has a voltage level, different from a ground level, and a second time at which the bias voltage has the ground level, and
wherein the voltage supply is configured to determine the voltage level based on the process gas.
‘242 is analogous art in the field of PLASMA-BASED MATERIAL MODIFICATION USING A PLASMA SOURCE WITH MAGNETIC CONFINEMENT (title), A plasma-based material modification system for material modification of a work piece may include a plasma source chamber coupled to a process chamber (abstract). ‘242 teaches that A series of optional grids 224 are positioned between plasma source chamber 202 and support structure 208 to extract ion beam 234 from plasma 220 and accelerate ion beam 234 towards work piece 206, thereby causing material modification of work piece 206 (Fig. 2, [0021]), One or more grids of grids 224 may be coupled to one or more bias power sources 248 to apply a bias voltage to grids 224. Bias power source 248 may be, for example, a DC power source, a pulsed DC power source, an RF power source, or a combination thereof ([0025], 2nd sentence, note pulsed DC has cycle, on the other hand, non-pulsed DC power source has a constant bias), In one example, the first grid may function as an extraction grid and be biased at approximately ±100 V with respect to the potential of end wall 216 and sidewall 218 of plasma source chamber 202. The second grid may be an acceleration grid that is biased at a negative extraction voltage of up to -20 kV with respect to the first grid to extract ion beam 234 from plasma 220. It should be appreciated that the extraction voltage applied to the second grid with respect to the first grid must be approximately in accordance with the Child-Langmuir law, where the current density extracted is a function of the potential difference between the grids and the distance between the grids. The fifth grid may be biased at approximately ground while the fourth grid may be biased at a negative voltage (e.g., -200 V to 0 V) relative to the fifth grid to suppress electron back-acceleration into plasma source chamber 202. The bias voltage applied to the third and the fourth grid may be selected to achieve the desired energy and profile of ion beam 234 ([0071]). Note the extraction voltage applied to the second grid with respect to the first grid must be approximately in accordance with the Child-Langmuir law Child-Langmuir law described in [0071] means the voltage applied is according to the charge species to be extracted, which in terms is a function of the feed gas (part of claim 17). Note it is obvious to pulse DC between peak voltage and ground level (another part of claim 17).
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have added a series of grid of ‘242 operating with either pulsed or non-pulsed mode, at level of various positive or negative voltage or ground as taught by ‘242, to the grid 1218 of ‘470, for the purpose of desired energy and profile of ion beam, as taught by ‘242 ([0071]).
Claims 1-2, 4, and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over ‘470, in view of Yeom et al. (KR 100866902, from IDS, hereafter ‘902) and ‘678.
‘470 teaches some limitations of:
Claim 1: plasma etching and plasma deposition are common process steps during semiconductor device fabrication ([0004], 2nd sentence, includes the claimed “A semiconductor processing apparatus, comprising”):
a plasma processing chamber 1210 (Fig. 12, [0102], includes the claimed “a chamber defining an internal space”);
the BP coupling element 19 is a substrate holder and is an electrostatic chuck ([0053], last sentence, includes the claimed “an electrostatic chuck included in the internal space of the chamber”);
The GCP control path 1205 provides power to the plasma 60 using an electrically conductive grid 1218 ([0102], last sentence, includes the claimed “a grid electrode between the chamber and the electrostatic chuck, having a plurality of through-holes” and “a base plate comprising a conductive material”);
Referring to FIG. 13, a timing diagram 1300 includes a source power 1, a bias power 2, and a grid control power 1305 which are pulsed to generate and deliver ions to a microelectronic workpiece. Timing diagram 1300 includes an additional pulse sequence including SP GCP pulses 1311 and BP GCP pulses 1312 ([0108], includes the claimed “and at least one voltage supply configured to output a bias voltage having a cycle to the grid electrode”);
one or more of the SP pulse modulation circuit 51, the BP timing circuit 52, an optional BP pulse modulation circuit 53, the optional GCP timing circuit 1258, and the optional GCP pulse modulation circuit 1259 may be included in a controller 1250. As with previously described controllers, controller 1250 may be positioned locally or remotely relative to the plasma processing chamber 1210 ([0105], includes the claimed “processing circuitry configured to control at least a timing of the at least one voltage supply“),
Referring to FIG. 13, a timing diagram 1300 includes a source power 1, a bias power 2, and a grid control power 1305 which are pulsed to generate and deliver ions to a microelectronic workpiece. Timing diagram 1300 includes an additional pulse sequence including SP GCP pulses 1311 and BP GCP pulses 1312 ([0108]), The SP GCP pulses 1311 include an SP GCP pulse amplitude 1304 while the BP GCP pulses 1312 include a BP GCP pulse amplitude 1314. The SP GCP pulse amplitude 1304 and the BP GCP pulse amplitude 1314 may be positive or negative relative to a reference potential ([0109], includes the claimed “wherein the processing circuitry is configured to control the at least one voltage supply to
output the bias voltage such that the bias voltage has a positive voltage level during a first time in the cycle and such that a capacitance charge accumulates in the base plate during the first time, and output the bias voltage during a second time, different from the first time, in the cycle such that the ions are accelerated and such that the capacitance charge is discharged“, see also [0127]-[0129], i.e. GCP is employed in various ways).
‘470 does not teaches the other limitations of:
Claim 1: (1A) a plurality of grid electrodes between the chamber and the electrostatic chuck, the plurality of grid electrodes spaced apart from each other in a vertical direction and respectively having a plurality of through-holes,
a plurality of reflectors between the plurality of grid electrodes and the electrostatic chuck, the plurality of reflectors configured to reflect ions passing through the plurality of through-holes of each of the plurality of grid electrodes;
(and at least one voltage supply configured to output a bias voltage having a cycle) to at least one of the plurality of grid electrodes;
wherein each of the plurality of grid electrodes includes (a base plate comprising a conductive material), and
(1B) a cover layer covering a surface of the base plate and comprising a metal oxide.
Claim 2: wherein the metal oxide of the cover layer comprises at least one of Y2O3 and Al2O3.
‘902 is analogous art in the field of Neutral Beam Grid Structure (title), semiconductor integrated circuits (English translation, P2, 2nd paragraph). ‘902 teaches that a plurality of grids positioned on the traveling path of the ion beam generated from the control to control the direction of the ion beam, by providing a grid structure in which a plurality of slots are formed on the surface of the plurality of grids, respectively, It is possible to extract ions of high density, not to be easily broken by considering the mechanical strength of the grid, and to maintain the straightness of the converted neutral beam, thereby enabling fine pattern processing (Fig. 3, abstract), As shown in FIG. 4, the ion beam passing through the plurality of slits 300 is reflected by the reflector 400, converted into a neutral beam, and then incident on a wafer (not shown) to etch a target film of the wafer. The reflector 400 is positioned perpendicular to the longitudinal direction of the grid 200 to maintain the straightness of the neutral beam (bridging paragraph between P3-4).
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have added a plurality of grids and reflectors of ‘902, to the grid 1218 of ‘470 (the limitation of 1A), for the purpose of extract ions of high density, as taught by ‘902 (abstract).
‘678 is analogous art in the field of INTERNAL PLASMA GRID APPLICATIONS FOR SEMICONDUCTOR FABRICATION (title), The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio (abstract), The grid assembly can be biased using DC or RF sources ([0076]). ‘678 teaches that Non-limiting examples of grid structures are shown in FIGS. 2A, 2B and 3A-3D … the grid contains one or more materials including, but not limited to, metals, metallic alloys such as stainless steel, aluminum, titanium, ... The material may or may not be anodized or otherwise passivated for, e.g., corrosion resistance … a grid may be coated with a pure coating including, but not limited to, coatings of Y2O3 … the grid may be grounded, floating or biased ([0049]).
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have adopted anodized aluminum or metal coated Y2O3 (the limitations of 1B and 2), as taught by ‘678, as the grids 300 of ‘902, for the purpose of corrosion resistance, as taught by ‘678 ([0049]).
‘470 further teaches the limitations of:
Claims 6-7: Referring to FIG. 13, a timing diagram 1300 includes a source power 1, a bias power 2, and a grid control power 1305 which are pulsed to generate and deliver ions to a microelectronic workpiece. Timing diagram 1300 includes an additional pulse sequence including SP GCP pulses 1311 and BP GCP pulses 1312 ([0108]), The SP GCP pulses 1311 include an SP GCP pulse amplitude 1304 while the BP GCP pulses 1312 include a BP GCP pulse amplitude 1314. The SP GCP pulse amplitude 1304 and the BP GCP pulse amplitude 1314 may be positive or negative relative to a reference potential ([0109], includes the claimed “wherein the bias voltage has a waveform of at least one of a square wave or a saw wave” of claim 6, and “wherein the processing circuitry is configured to control the at least one voltage supply to output the bias voltage such that the bias voltage has the positive voltage level during the first time in the cycle, a negative voltage level during a third time, different from the first time and the second time in the cycle, and a ground level during the second time, different from the first time and the third time in the cycle” of claim 7, see Fig. 7, [0082], reference potential is 0 V).
The combination of ‘470, ‘902, and ‘678 further teaches the limitations of:
Claim 4: The grid may on average be between about 1-50 mm thick, preferably between about 5-20 mm thick (‘678, [0051], coating means a very thin layer, includes the claimed “wherein a thickness of the cover layer, as measured from one surface of the base plate is smaller than a corresponding thickness of the base plate”).
Claim 8: As illustrated in FIG. 2, a plurality of grids 21 and 22 having slit 21a are stacked to adjust the voltage applied to each grid to adjust the direction of the ion beam (‘902, P2, 2nd last complete paragraph, description clearly applicable to Fig. 3, includes the claimed “wherein the plurality of grid electrodes comprises at least a first grid electrode and a second grid electrode between the first grid electrode and the electrostatic chuck, and the processing circuitry is configured to control the at least one voltage supply is configured to output a first bias voltage to the first grid electrode and output a second bias voltage, different from the first bias voltage, to the second grid electrode”).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over ‘470, ‘902, and ‘678, as being applied to claim 1 rejection above, further in view of O'Donnell et al. (US 20040002221, hereafter ‘221).
The combination of ‘470, ‘902, and ‘678 does not teach the limitations of:
Claim 3: wherein the cover layer comprises at least a first cover layer and a second cover layer.
‘221 is analogous art in the field of Productivity Enhancing Thermal Sprayed Yttria-containing Coating For Plasma Reactor (title), Components of semiconductor processing apparatus comprise thermal sprayed yttria-containing coatings that provide erosion, corrosion and/or corrosion-erosion resistance in plasma atmospheres. The coatings can protect substrates from physical and/or chemical attack (abstract). ‘221 teaches that If desired, one or more intermediate layers of material can be provided between the surface of the component that is coated and the yttria-containing coating. FIG. 5 shows a coated component according to an exemplary preferred embodiment. A first intermediate coating 80 is optionally coated on a substrate 70 by a conventional technique. The optional first intermediate coating 80 is sufficiently thick to adhere to the substrate and to further allow it to be processed prior to forming an optional second intermediate coating 90, or the yttria-containing coating 100 ([0062]), for the purpose of promoting adhesion ([0041]).
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have added intermediate layer or layers of ‘221, below the Y2O3 coating imported from ‘678 and then combined with ‘470 and ‘902, for the purpose of promoting adhesion, as taught by ‘221 ([0041]).
Claim 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over ‘470, ‘902, and ‘678, as being applied to claim 8 rejection above, further in view of ‘242. Alternatively, claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over ‘470, ‘902, ‘678, and ‘242.
The combination of ‘470, ‘902, and ‘678 does not teach the limitations of:
Claim 9: wherein the processing circuitry is configured to control the at least one voltage supply is configured to output the first bias voltage as the bias voltage having the cycle, and to output the second bias voltage as a constant voltage less than a ground level.
Claim 10: wherein the processing circuitry is configured to control the at least one voltage supply is configured to output the first bias voltage as a constant voltage, higher than a ground level, and to output the second bias voltage as the bias voltage having the cycle.
Claim 11: wherein the processing circuitry is configured to control the at least one voltage supply is configured to output the first bias voltage as a voltage having a first cycle, and to output the second bias voltage as a voltage having a second cycle.
Claim 12: wherein the first bias voltage has the positive voltage level in at least a portion of the first cycle, and the second bias voltage has a negative voltage level in at least a portion of the second cycle.
Claim 13: wherein the plurality of grid electrodes further comprises a third grid electrode between the second grid electrode and the electrostatic chuck, and
the processing circuitry is configured to control the at least one voltage supply is configured to output at least one of a third bias voltage or a ground voltage to the third grid electrode.
‘242 is analogous art as discussed above.
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have adopted the series of grid of ‘242 operating with either pulsed or non-pulsed mode, at level of various positive or negative voltage or ground as taught by ‘242, as the grids of ‘902 and then combined with ‘470 and ‘678, for the purpose of desired energy and profile of ion beam, as taught by ‘242 ([0071]). Note ‘242 also teaches the limitations of claim 8.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over ‘470 in view of ‘242.
‘470 teaches some limitations of:
Claim 19: plasma etching and plasma deposition are common process steps during semiconductor device fabrication ([0004], 2nd sentence, includes the claimed “A semiconductor processing apparatus, comprising”):
a plasma processing chamber 1210 (Fig. 12, [0102]), the BP coupling element 19 is a substrate holder and is an electrostatic chuck ([0053], last sentence, includes the claimed “a chamber; an electrostatic chuck included in the internal space of the chamber”);
a plasma processing system 200 includes an SP coupling element 15 coupled to a plasma processing chamber 210 ([0052], description of Fig. 2 applicable to Fig. 12), FIG. 4 illustrates a schematic timing diagram of an example method of control for plasma processing including a high frequency radio frequency (RF) source power pulse and a low frequency RF bias power pulse in accordance with an embodiment of the invention ([0012], includes the claimed “a beam source including a head defining a plasma space, a bias electrode on the head and configured to receive radio frequency (RF) power”),
The GCP control path 1205 provides power to the plasma 60 using an electrically conductive grid 1218 ([0102], last sentence), the electrically conductive grid 1218 may be positioned between the plasma 60 and the workpiece surface ([0106], includes the claimed “and at least one grid electrode below the head, the at least one grid electrode each having a plurality of through-holes” instead of a plurality of grid electrodes);
one or more of the SP pulse modulation circuit 51, the BP timing circuit 52, an optional BP pulse modulation circuit 53, the optional GCP timing circuit 1258, and the optional GCP pulse modulation circuit 1259 may be included in a controller 1250. As with previously described controllers, controller 1250 may be positioned locally or remotely relative to the plasma processing chamber 1210 ([0105], includes the claimed “processing circuitry configured to control a timing of the at least one voltage supply“),
Referring to FIG. 13, a timing diagram 1300 includes a source power 1, a bias power 2, and a grid control power 1305 which are pulsed to generate and deliver ions to a microelectronic workpiece. Timing diagram 1300 includes an additional pulse sequence including SP GCP pulses 1311 and BP GCP pulses 1312 ([0108]), The SP GCP pulses 1311 include an SP GCP pulse amplitude 1304 while the BP GCP pulses 1312 include a BP GCP pulse amplitude 1314. The SP GCP pulse amplitude 1304 and the BP GCP pulse amplitude 1314 may be positive or negative relative to a reference potential ([0109], includes the claimed “wherein the processing circuitry is configured to control the at least one voltage supply to supply the voltage having the cycle such that the voltage having the cycle
has a positive voltage level during a first time in the cycle such that a capacitance charge accumulates in the at least one of the plurality of grid electrodes, and
has a ground level during a second time, different from the first time, in the cycle such that the process gas is accelerated and such that the capacitance charge is discharged “, see also [0127]-[0129], i.e. GCP is employed in various ways).
‘470 is silent on other details of the SP coupling element 15. ‘470 does not expressly teaches the other limitations of:
Claim 19: (a beam source including a head defining a plasma space) configured for process gas to be supplied to, (a bias electrode on the head and configured to receive radio frequency (RF) power);
a plurality of grid electrodes below the head, the plurality of grid electrodes each respectively including a plurality of through-holes;
a gas supply configured to supply the process gas to the beam source,
at least one voltage supply configured to supply to each of the plurality of grid electrodes, a bias voltage,
wherein the at least one voltage supply is configured to supply a voltage having a cycle to at least one of the plurality of grid electrodes, and to supply a constant voltage to another of the plurality of grid electrodes.
Claim 20: wherein the plurality of grid electrodes comprises a first grid electrode, and a second grid electrode between the first grid electrode and the electrostatic chuck, and the at least one voltage supply is configured to supply the voltage having the cycle to the first grid electrode, and (the processing circuitry is configured to control) to supply the constant voltage to the second grid electrode.
‘242 is analogous art as discussed above. ‘242 also teaches that Plasma 220 may be generated by supplying a process gas from gas source 244 into plasma source chamber 202 and introducing power from a power source into plasma source chamber 202 to ionize and dissociate the process gas ([0063], 4th sentence).
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have added a gas supply and a series of grid of ‘242 operating with either pulsed or non-pulsed mode, at level of various positive or negative voltage or ground as taught by ‘242, to the grid 1218 of ‘470, for the purpose of desired energy and profile of ion beam, as taught by ‘242 ([0071]).
Note ‘242 can also be applied as the primary reference for various rejections.
Response to Arguments
Applicant's arguments filed 06/03/2026 have been fully considered but they are not persuasive or not convincing in light of the new ground of rejection above.
In regarding 35 USC 112(b) rejection, see the middle of page 10, Applicants’ amendment overcomes the rejection.
In regarding to 35 USC 103 rejection claims 14-18 rejection, see the bottom of page 12, this argument is moot in light of the new ground of rejection above.
In regarding to 35 USC 103 rejection claims 1-2 and 4-8, Applicants argue that ‘470 uses the conductive grid 1218 to “increase the verticality of the ions deliver to the workpiece surface”, further provides pulses during different operations, because ‘470 does not teach a cover layer, does not consider complication from accumulation of capacitance charges, the timing would not be applicable to the modified structure, therefore, unfit for its intended purpose, see the middle of page 13 to page 14.
This argument is found not persuasive.
As Applicants’ acknowledged, ‘470 provides many different operations. For example, see [0127]-[0129]. While ‘470 is silent on accumulation of charges, it is far away from teaching away from applying a protective coating using the various different operations.
The OC has clearly set forth that the purpose of adding an anodized aluminum or metal coated Y2O3 is for the purpose of corrosion resistance, as taught by ‘678 ([0049]).
It appears Applicants are arguing the magnitude of the SP GCP pulse and BP CGP pulse (1304 and 1314 in Fig. 13) affecting the accumulation of charges.
However, ‘470 clearly teaches that “Alternatively, the SP GCP pulse amplitude 1304 is negative and the BP GCP pulse amplitude 1314 is positive” ([0109], last sentence).
In short, Applicants merely disclosed an effect of the operation that is silent from ‘470. When the combined apparatus has the same structure, including the magnitude of the pulses, it would have the same property.
When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent (In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977); MPEP 2112.01).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20050211170 is cited for DC pulses return to ground (Figs. 12A-E). US 20190131113 is cited for two layers plasma protective coatings (Fig. 8).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEATH T CHEN whose telephone number is (571)270-1870. The examiner can normally be reached 8:30am-5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Parviz Hassanzadeh can be reached at 571-272-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEATH T CHEN/Primary Examiner, Art Unit 1716
Prosecution Insights