DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
¶[00184] begins with two extra paragraph numbers that should be deleted: “[00184] [00179][00191] According to some embodiments of the present disclosure …”.
Also, in ¶[0050], “array test (ART)t” appears to include a typographical error (i.e., the extra “t”) and should most likely be changed to “array test (ART)”.
Also, ¶[0039] states: “Each of the sub-pixels SP includes a transistor connected to a gate line and a data line, a capacitor configured to store a data signal DATA supplied through the transistor in the form of a data voltage, and a pixel circuit configured to operate in response to the data voltage stored in the capacitor.” The capitalization of “DATA” suggests that this may be a drawing reference label; however there is no item labeled as “DATA” in any of the drawings. It appears that the capitalized “DATA” could be deleted from the paragraph without any loss of meaning.
Also, the last sentence of ¶[0047] states: “the output pads located in each of the COG areas in which the data drive ICs 108 are respectively mounted may be connected to the data lines DL via link lines to supply a data signal to the sub-pixels SP of the active area AA.” However, there is no item labeled as “DL” in any of the drawings; FIG. 1 shows the data drive ICs 108.
Once in lines 1–2 of ¶[0053] and twice in lines 1 and 5 of ¶[0054], the following item is mentioned: “COG area COG Area_A”. This is somewhat confusing because the label in FIG. 2 is “COG Area A”, not “COG Area_A”. The examiner recommends to change all three mentions of “COG area COG Area_A” in ¶[0053–0054] to simply “COG area A” to avoid redundancy and improve clarity.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore,
the “plurality of gate lines” and “plurality of data lines that cross the plurality of gate lines” of claims 1 and 7 and
the “plurality of gate lines” and the “plurality of data lines disposed in different directions” of claims 13 and 16
must be shown or the features canceled from the claims. No new matter should be entered. The examiner notes that in the applicant’s specification, there are no drawing reference numbers associated with gate lines. “Data lines DL” are mentioned in ¶[0047] but do not appear in the drawings. A “data
line DL1” is mentioned in ¶[0070] and appears in the circuit diagram of FIG. 3, but a circuit diagram only describes electrical interconnections and cannot be viewed as a geometric layout / schematic of the actual physical structures of the electrical interconnections; thus, the data line DL1 in FIG. 3 does not show the features of claims 1, 7, 13, and 16 of data lines that cross gate lines or are disposed in different directions from gate lines.
Similarly, the drawings must also show the following structure from claims 1, 7, 13, and 16:
“a shorting bar to which the plurality of gate lines are electrically connected” from line 4 of claim 1 and claim 7
“A method of manufacturing a display device comprising … a shorting bar electrically connected to the plurality of gate lines to temporarily form an equipotential between the plurality of gate lines” from lines 1–4 of claim 13 and claim 16
As explained in objection #1 above, there are no drawing reference numbers associated with gate lines. A shorting bar is shown in FIG. 2. In ¶[0057] the specification states: “In the organic light-emitting display device 100 including the COG-type driving unit, an equipotential may be temporarily formed between the output pad 114, the link lines 112, and the gate lines in each COG block using the shorting bar, as shown in FIG. 2.” This description suggests that the gate lines in FIG. 2 are the unlabeled lines on the left sides of the output pads 114, but this is not clear because there are no labels for the gate lines. FIGS. 1, 4A–4C, and 5A–5C do not show features that are labeled as gate lines.
Similarly, the drawings must also show the following aspects of the method of claim 16: “forming an encapsulation layer on the first protective film and exposing a predetermined portion of the first protective film; and removing the exposed predetermined portion of the first protective film.” FIG. 5A shows the encapsulation layer 180 on top of the first protective film 170. A hole in the encapsulation layer 180 exposes a “predetermined portion” of the first protective film 170, as circled by the examiner in FIG. 5A below:
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Referring to the examiner’s annotations in FIG. 5B below, the entirety of the predetermined portion of the first protective film 170 has not been removed. Specifically, only Region 2 of the first protective film 170 has been removed. Region 1 of the first protective film 170 has not been removed. In order for the drawings to agree with claim 16, FIGS. 5B and 5C should show that the entirety of the exposed portion of the first protective layer 170 in FIG. 5A has been removed in FIGS. 5B and 5C.
Similarly, FIGS. 4B and 4C should show that the entirety of the exposed portion of the first protective layer 170 in FIG. 4A has been removed in FIGS. 4B and 4C because it appears that claim 16 also reads on FIGS. 4A and 4B.
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Alternatively, without modifying the drawings, claim 16 could be amended to be in agreement with FIGS. 5B–5C and FIGS. 4B–4C and in agreement with the following statements from the specification (to make it clear that rather than removing the entirety of the exposed portion of the protective film 170, only the part of the exposed portion of the protective film 170 that is in the shorting bar area is removed):
“[00169] As shown in FIG. 5B, in the shorting bar area, the first protective film 170 exposed by the encapsulation layer 180 may be selectively removed.”
“[00118] As shown in FIG. 4B, the first protective film 170 in the shorting bar area may be selectively removed.”
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because FIGS. 4A, 4B, 4C, 5A, 5B, and 5C include the following reference character not mentioned in the description: DT. For example, in ¶[0090] the specification states: “The thin-film transistor may be the driving transistor DR described with reference to FIG. 3”, apparently in reference to FIGS. 4A–4C (see ¶[0075—0076]). However, the label “DR” does not appear in FIGS. 4A–4C. A thin-film transistor is labeled as “DT” in FIGS. 4A–4C and 5A–5C. This objection will be overcome by editing the specification to refer to the “thin-film transistor DT” in all places in the specification where a/the thin-film transistor is mentioned specifically in reference to FIGS. 4A–4C or FIGS. 5A–5C.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because FIG. 2 includes the following reference character not mentioned in the description: VCOM.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign mentioned in the description: “The shorting line between the shorting bar and the equipotential line EQ_L forming an equipotential between the COG blocks may be cut simultaneously with a process of cutting a portion of the shorting line between the output pads and the shorting bar in each COG area” ¶[0052]. This sentence is difficult to understand because FIG. 2 does not have a label EQ_L, so it is not clear where is the equipotential line EQ_L and where is the “shorting line between the shorting bar and the equipotential line EQ_L. Of the items mentioned in the aforementioned sentence from ¶[0052], only the “Shorting Bar” has a label in FIG. 2.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because FIG. 2 does not include the reference sign 104 mentioned in lines 4–6 of ¶[0054]: “Accordingly, gate signals output from the gate drive ICs 104 mounted on the COG area COG Area_A may be applied to the transistors connected to the sub-pixels SP of the active area AA via the output pads 114, the link lines 112, and the gate lines.” This sentence is difficult to understand because FIG. 2 does not show gate drive ICs 104 mounted on the COG area A. FIG. 1 shows gate drive ICs 104 mounted in the inactive area IA on the left and right sides of the active area AA of the display device 100. However, the correspondence between the COG area A of FIG. 2 and the inactive area IA of FIG. 1 is not made entirely clear. ¶[0025] states that “FIG. 2 is a diagram showing a shorting bar extending in a COG area disposed in one side of an inactive area in the organic light-emitting display device in order to temporarily form an equipotential”. From this, the examiner understands that the COG area A of FIG. 2 is located in one side of the inactive area IA of FIG. 1, such as the left side of the inactive area IA where gate drive ICs 104 are located.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because FIGS. 5A, 5B, and 5C do not include the reference sign 225c mentioned in ¶[00143]: “The fourth to sixth conductive material patterns 225a, 225b, and 225c may be formed in the bezel area Bezel”. This objection will be overcome by adding the label 225c in FIGS. 5A–5C in the same way that 225c is labeled in FIGS. 4A–4C.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 13–18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation “the first and second conductive material patterns” in lines 1–2. There is insufficient antecedent basis for this limitation in the claim because claim 4 depends on claim 1, and “first and second conductive material patterns” were introduced in claim 3, not in claim 1.
Claim 13 recites the limitations “a plurality of gate lines and a plurality of data lines disposed in different directions to define a plurality of pixel areas” in lines 1–2. The examiner finds this language indefinite because it could reasonably be interpreted to mean that the data lines are disposed in different directions from each other, whereas the examiner believes that the intended meaning is that the data lines are disposed in different directions from the gate lines. The examiner suggests to use similar language for this part of claim 13 as was used in claims 1 and 7; for example, claim 13 could be amended to recite “a plurality of gate lines and a plurality of data lines that cross the plurality of gate lines to define a plurality of pixel areas”.
Claim 14 includes all the limitations of claim 13 by reference. Thus, claim 14 inherits the indefiniteness of claim 13 described above.
Claim 15 recites the limitations “a thin-film transistor disposed in the plurality of pixel areas” (lines 4–5) and “a light-emitting diode disposed in the plurality of pixel areas” (last two lines). As presently written, it is unclear whether there is a single thin-film transistor and a single light-emitting diode for the plurality of pixel areas, or there is a plurality of thin-film transistors and a plurality of light-emitting diodes, each corresponding on a 1:1 basis to the plurality of pixel areas. The examiner suggests the following amendment to claim 15:
“15. The method according to claim 13, wherein the forming of the multi-layered conductive pattern structure includes:
forming first and second conductive material patterns on the substrate using a same material as a gate electrode of a thin-film transistor disposed in each pixel area of the plurality of pixel areas;
forming an interlayer insulating film having first and second contact holes formed therein on the first and second conductive material patterns;
forming third and fourth conductive material patterns on the interlayer insulating film to be electrically connected to the first and second conductive material patterns through the first and second contact holes, respectively, using a same material as source and drain electrodes of the thin-film transistor disposed in each pixel area of the plurality of pixel areas;
forming a planarization film having third and fourth contact holes formed therein on the third and fourth conductive material patterns to cover the third and fourth conductive material patterns; and
forming a fifth conductive material pattern on the planarization film to be electrically connected to the third and fourth conductive material patterns through the third and fourth contact holes using a same material as a first electrode of a light-emitting diode disposed in each pixel area of the plurality of pixel areas.”
Claim 16 recites the limitations “a plurality of gate lines and a plurality of data lines disposed in different directions to define a plurality of pixel areas” in lines 1–2. The examiner finds this language indefinite because it could reasonably be interpreted to mean that the data lines are disposed in different directions from each other, whereas the examiner believes that the intended meaning is that the data lines are disposed in different directions from the gate lines. The examiner suggests to use similar language for this part of claim 16 as was used in claims 1 and 7; for example, claim 16 could be amended to recite “a plurality of gate lines and a plurality of data lines that cross the plurality of gate lines to define a plurality of pixel areas”.
Claim 17 includes all the limitations of claim 16 by reference. Thus, claim 17 inherits the indefiniteness of claim 16 described above.
Claim 18 recites the limitation “the same material as source and drain electrodes of the thin-film transistor disposed in the plurality of pixel areas” in the first paragraph on page 44 (i.e., the last page of the claims), on the third line of said paragraph. There is insufficient antecedent basis for this limitation in the claim. That is, since “source and drain electrodes of the thin-film transistor” are being introduced in this same line, there is no antecedent basis for “the same material as source and drain electrodes of the thin-film transistor”.
Claim 18 also recites the limitations “a thin-film transistor disposed in the plurality of pixel areas” (lines 4–5) and “a light-emitting diode disposed in the plurality of pixel areas” (last two lines). As presently written, it is unclear whether there is a single thin-film transistor and a single light-emitting diode for the plurality of pixel areas, or there is a plurality of thin-film transistors and a plurality of light-emitting diodes, each corresponding on a 1:1 basis to the plurality of pixel areas.
The examiner suggests the following amendment to claim 18 to correct the problems identified above:
“18. The method according to claim 16, wherein the forming of the multi-layered conductive pattern structure includes:
forming first and second conductive material patterns on the substrate using a same material as a gate electrode of a thin-film transistor disposed in each pixel area of the plurality of pixel areas;
forming an interlayer insulating film having first and second contact holes formed therein on the first and second conductive material patterns;
forming third and fourth conductive material patterns on the interlayer insulating film to be electrically connected to the first and second conductive material patterns through the first and second contact holes, respectively, using a same material as source and drain electrodes of the thin-film transistor disposed in each pixel area of the plurality of pixel areas;
forming a planarization film having third and fourth contact holes formed therein on the third and fourth conductive material patterns to cover the third and fourth conductive material patterns; and
forming a fifth conductive material pattern on the planarization film to be electrically connected to the third and fourth conductive material patterns through the third and fourth contact holes using a same material as a first electrode of a light-emitting diode disposed in each pixel area of the plurality of pixel areas.”
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 would be allowed if the associated drawing objections were resolved (see Drawings section above). The closest prior art of
KR 20030058085 A by Lee and Yang (“Lee” hereinafter) and
US 2007/0164289 A1 by Jung (“Jung” hereinafter),
either singularly or in combination fails to anticipate or render obvious
“a shorting bar to which the plurality of gate lines are electrically connected to temporarily form an equipotential therebetween,
wherein the shorting bar comprises:
a multi-layered conductive pattern structure disposed on a substrate and including two or more layers of conductive material patterns with at least one insulating film interposed therebetween; and
a bank-spacer layer covering the multi-layered conductive pattern structure”
in combination with all other limitations in the claim as claimed and defined by applicant.
In interpreting claim 1, the examiner understands “a shorting bar” to mean that there is a single shorting bar, and that the single shorting bar comprises multiple conductive parts (i.e., the “two or more layers of conductive material patterns”) with the multiple conductive parts being electrically connected to each other so that an equipotential, understood to mean a single voltage, is applied to all the multiple conductive parts through contact of any part of the shorting bar to the single voltage source. The examiner also understands “the plurality of gate lines” to refer to all the gate lines in the display device, not to only a subset of the gate lines such as the odd-numbered or even-numbered gate lines. Thus, the examiner understands that claim 1 requires that a single shorting bar is electrically connected to all of the gate lines so that all of the gate lines are temporarily held at the same voltage. “Temporarily” is understood in view of the specification to mean during the manufacturing and testing of the display device, up until the time when the shorting bar is disconnected from the gate lines (e.g., by cutting along the ‘Trimming Line’ in FIG. 2).
The following is an explanation of why the prior art of Lee and Jung fails to teach aspects of claim 1.
Regarding claim 1, Lee teaches:
A display device (FIG. 1) comprising:
a plurality of gate lines 11 (“gate wiring 11”);
a plurality of data lines 13 (“data wiring 13”) that cross the plurality of gate lines 11 to define a pixel area (“A thin film array substrate includes gate and data wires defining pixel areas on a glass substrate”, from the abstract); and
two shorting bars (31c and 31d) to which the plurality of gate lines 13 are electrically connected (“the third shorting bar 31c is connected to the odd-numbered gate lines, and the fourth shorting bar 31d is connected to the even-numbered gate lines”) to temporarily form an equipotential therebetween,
wherein the two shorting bars (31c and 31d) comprise:
a multi-layered conductive pattern structure 31c+15+31d (see FIG. 2) disposed on a substrate and including two or more layers of conductive material patterns (31c and 31d) with at least one insulating film 15 (“gate insulating film 15”) interposed therebetween (as shown in FIG. 2); and
a bank-spacer layer 16 (“protective layer 16”, labeled in FIG. 3) covering the multi-layered conductive pattern structure 31c+15+31d.
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However, Lee does not teach that the two shorting bars 31c and 31d are to be electrically connected to each other. In fact, the two shorting bars 31c and 31d are electrically isolated from each other by the gate insulating layer 15. Instead of a single shorting bar being electrically connected to all of the gate lines, one shorting bar 31c is connected to the odd-numbered gate lines, and another shorting bar 31d is connected to the even-numbered gate lines. Thus, the two shorting bars 31c and 31d cannot be considered together as a single shorting bar to satisfy the limitations of claim 1 of there being “a shorting bar to which the plurality of gate lines are electrically connected to form an equipotential therebetween”, wherein the examiner understands “a shorting bar” to refer to a single shorting bar, “the plurality of gate lines” to refer to all the gate lines (i.e., not only the odd gate lines or the even gate lines), and “an equipotential” to refer to a single voltage.
That is, the shorting bar 31c can form a first equipotential among the odd-numbered gate lines, and the shorting bar 31d can form a second equipotential among the even-numbered gate lines, but there is no way to form an equipotential among all the gate lines without electrically connecting the two shorting bars 31c and 31d, which is not taught by Lee.
Considered alone, neither one of the shorting bar 31c or the shorting bar 31d can meet the requirement of claim 1 of “a multi-layered conductive pattern structure … including two or more layers of conductive material patterns” because each of 31c and 31d only comprises a single layer of a conductive material pattern.
Regarding claim 1, Jung teaches:
A display device (FIG. 3) comprising:
a plurality of gate lines 120 (“gate line 120” ¶[0048]);
a plurality of data lines 130 (“data line 130” ¶[0048]) that cross the plurality of gate lines 120 to define a pixel area 161 (“pixel area 161” ¶[0058]); and
a shorting bar 184 (“gate shorting bar 184” ¶[0049] consisting of a “first gate shorting bar 186” and “a second gate shorting bar 187” ¶[0067]) to which the plurality of gate lines 120 are electrically connected to temporarily form an equipotential therebetween,
wherein the shorting bar 184 comprises:
a multi-layered conductive pattern structure 186+125+187 (see cross section along line IV–IV′ in FIG. 4) disposed on a substrate 110 (“lower substrate 110” ¶[0069]) and including two or more layers of conductive material patterns 186 and 187 (“a first gate shorting bar 186 electrically connected to the odd shorting line 185a that extends from the gate pad 180 and a second gate shorting bar 187 electrically connected, via the fourth contact hole 154, to the even shorting line 185b extended from the gate pad 180” ¶[0067]) with at least one insulating film 125 (“gate insulating film 125”) interposed therebetween; and
a bank-spacer layer 150 (“protective film 150” ¶[0048]) covering the multi-layered conductive pattern structure.
However, the Jung has the same problem as Lee: the shorting bar 184 is not a single shorting bar in which all of its conductive parts are electrically connected to each other. Rather, the shorting bar 184 consists of a first shorting bar 186 and a second shorting bar 187. The first shorting bar 186 is electrically connected to odd-numbered gate lines 120, and the second shorting bar 187 is electrically connected to even-numbered gate lines 120. Therefore, Jung’s shorting bar 184 does not provide a means of holding all the gate lines at a single voltage as required by claim 1. Jung explains in ¶[0022–0023] that if the odd- and even-numbered gate lines are connected to a common shorting bar, then to inspect the liquid crystal display panel for shorts between gate lines requires applying an inspection signal to each gate pad “by a separate auto probe inspecting process” ¶[0024], and that is why Jung has provided separate shorting bars for the odd- and even-numbered gate lines.
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Claims 2–6 would be allowed at least for the reason that they depend on allowable claim 1, pending resolution of the drawing objections associated with claim 1 and if the rejection of claim 4 under 35 USC § 112(b) were overcome.
Claim 7 would be allowed if the associated drawing objections were resolved (see Drawings section above). The closest prior art of Lee and Jung, cited above, either singularly or in combination fails to anticipate or render obvious
“a shorting bar to which the plurality of gate lines are electrically connected to temporarily form an equipotential therebetween,
wherein the shorting bar comprises:
a multi-layered conductive pattern structure disposed on a substrate and including two or more layers of conductive material patterns with at least one insulating film interposed therebetween;
a bank layer covering the multi-layered conductive pattern structure;
a first protective film on the bank layer; and
an encapsulation layer on the first protective film”
in combination with all other limitations in the claim as claimed and defined by applicant.
That is, claim 7 includes all the limitations of claim 1, but the “bank-spacer layer” of claim 1 is called “a bank layer” in claim 7, and the bank layer is covered (from bottom to top) by a first protective film and an encapsulation layer. Thus, since Lee and Jung do not fully disclose the limitations of claim 1 as explained above, Lee and Jung also do not fully disclose the limitations of claim 7.
Claims 8–12 would be allowed at least for the reason that they depend on allowable claim 7, pending resolution of the drawing objections associated with claim 7.
Claim 13 would be allowed if the associated drawing objections were resolved (see Drawings section above) and if the rejection of claim 13 under 35 USC § 112(b) were overcome. The closest prior art of Lee and Jung, cited above, either singularly or in combination fails to anticipate or render obvious
“A method of manufacturing a display device comprising a plurality of gate lines and a plurality of data lines disposed in different directions to define a plurality of pixel areas and a shorting bar electrically connected to the plurality of gate lines to temporarily form an equipotential between the plurality of gate lines, the method comprising:
manufacturing the shorting bar by:
forming a multi-layered conductive pattern structure on a substrate, the multi-layered conductive pattern structure including two or more layers of conductive material patterns with at least one insulating film interposed therebetween; and
forming a bank-spacer layer on the multi-layered conductive pattern structure, the bank-spacer layer covering the multi-layered conductive pattern structure.”
in combination with all other limitations in the claim as claimed and defined by applicant.
That is, claim 13 describes a method of forming the same structure that was described in claim 1. Thus, since Lee and Jung do not fully disclose the structure defined by claim 1 as explained above, Lee and Jung also do not fully disclose the method of claim 13.
Claims 14–15 would be allowed at least for the reason that they depend on allowable claim 13, pending resolution of the drawing objections associated with claim 13, and if the rejections of claims 13 and 15 under 35 USC § 112(b) were overcome.
Claim 16 would be allowed if the associated drawing objections were resolved (see Drawings section above) and if the rejection of claim 16 under 35 USC § 112(b) were overcome. The closest prior art of Lee and Jung, cited above, either singularly or in combination fails to anticipate or render obvious
“A method of manufacturing a display device comprising a plurality of gate lines and a plurality of data lines disposed in different directions to define a plurality of pixel areas and a shorting bar electrically connected to the plurality of gate lines to temporarily form an equipotential between the plurality of gate lines, the method comprising:
manufacturing the shorting bar by:
forming a multi-layered conductive pattern structure on a substrate, the multi-layered conductive pattern structure including two or more layers of conductive material patterns with at least one insulating film interposed therebetween;
forming a bank layer on the multi-layered conductive pattern structure, the bank layer covering the multi-layered conductive pattern structure;
forming a first protective film on the bank layer;
forming an encapsulation layer on the first protective film and exposing a predetermined portion of the first protective film; and
removing the exposed predetermined portion of the first protective film”
in combination with all other limitations in the claim as claimed and defined by applicant.
That is, claim 16 includes all the limitations of claim 13, but the “bank-spacer layer” of claim 13 is called “a bank layer” in claim 16, and the bank layer is covered (from bottom to top) by a first protective film and an encapsulation layer. Thus, since Lee and Jung do not fully disclose the limitations of claim 13 as explained above, Lee and Jung also do not fully disclose the limitations of claim 16.
Claims 17–18 would be allowed at least for the reason that they depend on allowable claim 16, pending resolution of the drawing objections associated with claim 16, and if the rejections of claims 16 and 18 under 35 USC § 112(b) were overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (listed in order of publication date from oldest to newest):
KR 20010011323 A—see FIGS. 4 and 5; gate shorting bar 24 covered by gate insulating film 30 and protective film 70
KR 20020006748 A—see FIGS. 2 and 3a; “a first shorting bar 29 connecting all odd-numbered data lines and a second shorting bar 32 connecting both even-numbered data lines to one side of the liquid crystal panel”
KR 100926430 B1—see FIG. 6b; two separate shorting bars 31 and 33 are connected to odd- and even-numbered gate lines 13
US 2005/0078264 A1—see FIGS. 17A–17B; odd and even shorting bars 491 and 492 (FIG. 17A); even shorting bar 492 includes first even shorting bar 492B and second even shorting bar 492A in two different layers connected to each other by fourth contact electrode 498 and with gate insulating film 462 between 492B and 492A (FIG. 17B).
KR 20070072162 A—see FIGS. 2–3; the gate shorting bar 116a is only a single layer of conductive material.
CN 101060125 A—see FIGS. 17A–17B; appears to be substantially the same as US 2005/0078264 A1 listed above.
TW I387802 B—see FIGS. 2A–2B; shorting bars 292 are connected to electrode wiring 220 (FIG. 2A); FIG. 2B, which is a cross-section along line B–B′ of FIG. 2A, shows “a multi-layered conductive pattern structure disposed on a substrate and including two or more layers of conductive material patterns with at least one insulating film interposed therebetween” (quoting claim 1 of the present application); see in FIG. 2B the first conductive pattern 240, first dielectric layer 270, second dielectric layer 280, second conductive pattern 250, second dielectric layer 280, and transparent conductive pattern 260; however, based on the specification, the examiner does not believe that the cross-section shown in FIG. 2B describes a multilayered shorting bar as disclosed by the present application and claims; rather, the purpose of FIG. 2B is to show the multilayered structure of the first contact window opening H1 of the electrical connecting circuits 230.
US 2015/0155212 A1—see FIGS. 3–4; odd gate shorting bar OGS and even gate shorting bar EGS connected to odd and even gate lines GL, respectively (FIG. 3); cross-section in FIG. 4 shows “a multi-layered conductive pattern structure disposed on a substrate and including two or more layers of conductive material patterns with at least one insulating film interposed therebetween” (quoting claim 1 of the present application) in that the odd data shorting bar ODS is separated from the even data shorting bar EDS by the gate insulation film GI; however, since ODS and EDS are two separate shorting bars connected to the odd and even data link lines ODL and EDL, respectively, in the examiner’s view FIGS. 2–3 do not meet the requirements of, e.g., claim 1 (and the other independent claims) of a single shorting bar with a multilayered structure that is connected to all the gate lines, not only the odd gate lines or only the even gate lines.
KR 102403486 B1—see FIG. 14; single-layered shorting bar STB is topped by a bank 153, somewhat analogous to the “bank layer” of claims 7 and 16 of the present application.
KR 101710575 B1—see FIGS. 4 and 7; “The first and second shorting bars 120 and 122 are formed on the mother board 110 with an insulating layer interposed therebetween” (FIG. 7); however, FIG. 4 shows that the first and second shorting bars are separate from each other and cannot be considered as a single shorting bar, as disclosed in the present application and claims; i.e., FIG. 4 shows that the first shorting bar 120 is connected to first link wirings 125 and first pads 132, whereas the second shorting bar 122 is connected to second link wirings 127 and second pads 134.
US 2025/0044655 A1—see FIGS. 2b and 3; shorting bars 102 are part of a “multilayered conductive pattern structure” (quoting claim 1 of the present application) consisting of, from bottom to top, a signal line 101, an interlayer insulating layer 105, a shorting bar 102, a protective layer 108, and a conductive part 107 (FIG. 3); however, rather than the cross-section in FIG. 3 representing a multilayered shorting bar, FIG. 3 merely shows the interconnection between the signal line 101 and the shorting bar 102, which are shown to be at right angles with each other in FIG. 2b; also, unlike the present application, as shown in FIG. 2b there are separate shorting bars 102 for separate groups of signal lines 101 (e.g., odd and even signal lines).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam J Mott whose telephone number is (571)272-2367. The examiner can normally be reached Mon-Fri 8:30AM-5:00PM EST.
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/A.J.M./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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