DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed June 16, 2026. Claims 1, 11, and 14-16 have been amended. No claims have been added. Claim 12 has been canceled. Currently, claims 1-11, and 13-20 are pending.
Applicant’s revised drawings submitted June 16, 2026 overcome the drawing objection outlined in the previous Office Action. The drawing objection has been withdrawn.
Response to Arguments
Applicant’s arguments, see pages 10-11, filed June 16, 2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Malhotra et al. (US 20130115750 A1).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-11, and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Malhotra et al. (US 20130115750 A1) herein after “Malhotra”.
Regarding claim 1, Fig. 6 of Malhotra discloses a capacitor (Fig. 6, cell capacitor 600, ¶ [0044]) comprising:
a first electrode layer (Fig. 6, second electrode layer 610, ¶ [0045]);
a second electrode layer (Fig. 6, first electrode layer 604, ¶ [0045]);
a dielectric layer (Fig. 6, high k dielectric layer 606, ¶ [0045]) between the first electrode layer (610) and the second electrode layer (604); and
an interlayer (Fig. 6, blocking layer 608, ¶ [0045]) between the first electrode layer (610) and the dielectric layer (606),
wherein the interlayer (608) includes a first interface material and the first interface material includes at least one Group 13 element other than aluminum (“suitable blocking layer materials comprise…, Ga.sub.2O.sub.3”, ¶ [0036]), and
wherein the interlayer (608) includes a first mixed region (top portion of 608) and a second mixed region (bottom portion of 608),
the first mixed region (top portion of 608) between the first electrode layer (610) and a middle region of the interlayer (608),
the second mixed region (bottom portion of 608) between the dielectric layer (606) and the middle region of the interlayer (608),
the first mixed region (top portion of 608) including a mixture of the first interface material and at least one of a base element of the first electrode layer (610) or an oxide of the base element of the first electrode layer (610) (Malhotra discloses that the interlayer contains gallium oxide and can be doped with titanium, ¶ [0036]. Therefore, the top portion of 608 includes a mixture of the first interface material, gallium oxide, and the base element of the first electrode layer, titanium, ¶ [0038]), and
the second mixed region (bottom portion of 608) including a mixture of the first interface material and at least one of a base element of the dielectric layer (606) or an oxide of the base element of the dielectric layer (606) (Malhotra discloses that the interlayer contains gallium oxide and can be doped with titanium, ¶ [0036]. Therefore, the bottom portion of 608 includes a mixture of the first interface material, gallium oxide, and the base element of the dielectric layer, titanium, ¶ [0045]).
Regarding claim 2, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, and Fig. 6 of Malhotra further discloses wherein the at least one Group 13 element included in the first interface material is at least one of boron (B), gallium (Ga), indium (In), or thallium (Tl) (“suitable blocking layer materials comprise…, Ga.sub.2O.sub.3”, ¶ [0036]).
Regarding claim 3, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, and Fig. 6 of Malhotra further discloses wherein the first interface material includes an oxide of the at least one Group 13 element (“suitable blocking layer materials comprise…, Ga.sub.2O.sub.3”, ¶ [0036]).
Regarding claim 4, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, and Fig. 6 of Malhotra further discloses wherein
the at least one Group 13 element included in the first interface material is at least one of gallium (Ga) or indium (In) (“suitable blocking layer materials comprise…, Ga.sub.2O.sub.3”, ¶ [0036]), and
the first interface material includes at least one of gallium oxide, indium oxide, or a combination thereof (“suitable blocking layer materials comprise…, Ga.sub.2O.sub.3”, ¶ [0036]).
Regarding claim 5, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, and Fig. 6 of Malhotra further discloses wherein the interlayer (608) consists of a first layer including the first interface material (“suitable blocking layer materials comprise…, Ga.sub.2O.sub.3”, ¶ [0036]).
Regarding claim 8, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, and Fig. 6 of Malhotra further discloses wherein
the interlayer (608) is in direct contact with the first electrode layer (610), and
the interlayer (608) is in direct contact with the dielectric layer (606).
Regarding claim 9, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, and Fig. 6 of Malhotra further discloses wherein the interlayer (608) includes an amorphous structure (“Amorphous blocking layer, 608, is formed”, ¶ [0045]).
Regarding claim 10, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, and Fig. 6 of Malhotra further discloses wherein the interlayer (608) has a thickness of 15 Å or less (“the thickness of the blocking layer is in the range from about 0.7 nm to about 1.5 nm”, ¶ [0036]).
Regarding claim 11, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, and Fig. 6 of Malhotra further discloses wherein
the first electrode layer (610) includes a first electrode material (“the second electrode layer comprise…, TiN”, ¶ [0038]), and
the first electrode material includes at least one of a metal, an oxide, or a nitride, and includes at least one of titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), palladium (Pd), gold (Au), iridium (Ir), rhodium (Rh), molybdenum (Mo), vanadium (V), or niobium (Nb) as a base element of the first electrode layer (610) (“the second electrode layer comprise…, TiN”, ¶ [0038]).
Regarding claim 13, Fig. 6 of Malhotra discloses the capacitor of claim 11 as applied above, and Fig. 6 of Malhotra further discloses wherein the interlayer (608) includes a compound represented by the following formula
AxMyOz
wherein
A represents the Group 13 element other than aluminum (gallium),
M represents the base element included in the first electrode material (titanium),
O represents oxygen, and
0 < x ≤ 5; 0 ≤ y ≤ 5; and 0 < z ≤ 5 (“suitable blocking layer materials comprise…, Ga.sub.2O.sub.3”, ¶ [0036]. Malhotra discloses that the blocking layer may be doped with titanium. However, one of ordinary skill in the art could choose to use an undoped version of Ga.sub.2O.sub.3, such that y=0, to achieve a desired band gap and barrier height, ¶ [0036]).
Regarding claim 14, Fig. 6 of Malhotra discloses the capacitor of claim 11 as applied above, and Fig. 6 of Malhotra further discloses wherein
the first mixed region (top portion of 608) is in direct contact with the first electrode layer (610).
Regarding claim 15, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, and Fig. 6 of Malhotra further discloses wherein
the dielectric layer (606) includes a dielectric material (“suitable dielectric materials comprise…, TiO.sub.2”, ¶ [0034]), and
the dielectric material includes at least one of Zr, Hf, Ti, or Al as the base element of the dielectric layer (“suitable dielectric materials comprise…, TiO.sub.2”, ¶ [0034]).
Regarding claim 16, Fig. 6 of Malhotra discloses the capacitor of claim 15 as applied above, and Fig. 6 of Malhotra further discloses wherein
the second mixed region (bottom portion of 608) in direct contact with the dielectric layer (606).
Regarding claim 17, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, and Fig. 6 of Malhotra further discloses an electronic device (Fig. 6, DRAM cell, 620, ¶ [0044]) comprising:
a transistor (602); and
the capacitor (600), according to claim 1, electrically connected to the transistor (602).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Malhotra (US 20130115750 A1) in view of Rui et al. (US 20150228710 A1) herein after “Rui”.
Regarding claim 6, Fig. 6 of Malhotra discloses the capacitor of claim 1 as applied above, but Malhotra fails to disclose wherein
the interlayer includes at least a first layer and a second layer,
the first layer includes the first interface material,
the second layer includes a second interface material, and
the second interface material includes at least one Group 13 element.
In the similar field of endeavor of DRAM MIM capacitors, Fig. 5D of Rui discloses wherein
the interlayer (Fig. 5D, flash layer 504, dielectric layer 516, ¶ [0077] and [0087]) includes at least a first layer (504) and a second layer (516),
the first layer (504) includes the first interface material (“suitable dielectric materials for use as flash layers include…, gallium oxide”, ¶ [0085]),
the second layer (516) includes a second interface material (“the high band gap fourth dielectric layer includes one of aluminum oxide”, ¶ [0087]), and
the second interface material includes at least one Group 13 element (“the high band gap fourth dielectric layer includes one of aluminum oxide”, ¶ [0087]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the interlayer of Malhotra with the first and second layer as disclosed by Rui, to improve leakage current and breakdown voltage performance (see Rui, ¶ [0042]).
Regarding claim 7, Malhotra and Rui disclose the capacitor of claim 6 as applied above, but Malhotra fails to disclose wherein the first interface material and the second interface material are different from each other.
In the similar field of endeavor of DRAM MIM capacitors, Fig. 5D of Rui discloses wherein the first interface material and the second interface material are different from each other (“suitable dielectric materials for use as flash layers include…, gallium oxide”, ¶ [0085], “the high band gap fourth dielectric layer includes one of aluminum oxide”, ¶ [0087]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the interlayer of Malhotra with the first and second interface material as disclosed by Rui, to improve leakage current and breakdown voltage performance (see Rui, ¶ [0042]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Malhotra (US 20130115750 A1) in view of Lee et al. (US 20130052787 A1) herein after “Lee”.
Regarding claim 18, Fig. 6 of Malhotra discloses the electronic device of claim 17 as applied above, and Fig. 6 of Malhotra discloses a transistor (602) including a source region (Fig. 6, source 612, ¶ [0044]) and a drain region (Fig. 6, drain 614, ¶ [0044]), but fails to explicitly disclose wherein the transistor includes
a semiconductor substrate including a source region, a drain region, and a channel region between the source region and the drain region, and
a gate stack facing the channel region and including a gate insulating layer and a gate electrode.
In the similar field of endeavor of semiconductor devices, Fig. 2A of Lee discloses wherein the transistor includes
a semiconductor substrate (Fig. 2A, substrate 110, ¶ [0045]) including a source region (Fig. 2A, impurity regions 118, ¶ [0048]), a drain region (“The impurity regions 118 may serve as source and/or drain regions”, ¶ [0057]), and a channel region (Fig. 2A, active regions 114, ¶ [0045]) between the source region (118) and the drain region (118), and
a gate stack (Fig. 2A, gate insulating layer 124, buried word lines 126, ¶ [0046]) facing the channel region (114) and including a gate insulating layer (124) and a gate electrode (126).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Malhotra with the structure as disclosed by Lee, to increase device density and improve reliability (see Lee, ¶ [0004]) and/or because the claimed structure was known in the prior art and one skilled in the art could have combined the structures of Malhotra and Lee as claimed with no change in their respective functions, and the combination would have yielded the predictable result of creating a reliable transistor. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 19, Fig. 6 of Malhotra discloses the electronic device of claim 17 as applied above, and Fig. 6 of Malhotra discloses a transistor (602) including a source region (Fig. 6, source 612, ¶ [0044]) and a drain region (Fig. 6, drain 614, ¶ [0044]), but fails to explicitly disclose wherein the transistor includes
a semiconductor substrate including a source region, a drain region, and a channel region between the source region and the drain region; and
a gate stack in a trench defined by the semiconductor substrate such that the gate stack faces the channel region, the gate stack including a gate insulating layer and a gate electrode.
In the similar field of endeavor of semiconductor devices, Fig. 2A of Lee discloses wherein the transistor includes
a semiconductor substrate (110) including a source region (118), a drain region (118), and a channel region (114) between the source region (118) and the drain region (118); and
a gate stack (124, 126) in a trench (Fig. 2A, trenches 120T, ¶ [0046]) defined by the semiconductor substrate (110) such that the gate stack (124, 126) faces the channel region (114), the gate stack (124, 126) including a gate insulating layer (124) and a gate electrode (126).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Malhotra with the structure as disclosed by Lee, to increase device density and improve reliability (see Lee, ¶ [0004]) and/or because the claimed structure was known in the prior art and one skilled in the art could have combined the structures of Malhotra and Lee as claimed with no change in their respective functions, and the combination would have yielded the predictable result of creating a reliable transistor. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Malhotra (US 20130115750 A1) in view of Yamazaki et al. (US 20230380180 A1) herein after “Yamazaki”.
Regarding claim 20, Fig. 6 of Malhotra discloses the electronic device of claim 17 as applied above, but Malhotra fails to disclose a memory unit including the capacitor and the transistor, and
a control unit electrically connected to the memory unit, and configured to control the memory unit.
In the similar field of endeavor of semiconductor devices, Figs. 27B-28A of Yamazaki disclose a memory unit (Fig. 28A, memory cell array 1470, ¶ [0649]) including the capacitor (Fig. 27B, capacitor 100, ¶ [0087]) and the transistor (Fig. 27B, transistor 300, ¶ [0573]), and
a control unit (Fig. 28A, control logic circuit 1460, ¶ [0649]) electrically connected to the memory unit (1470), and configured to control the memory unit (1470).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Malhotra with the control unit as disclosed by Yamazaki, to control the memory cell (see Yamazaki, ¶ [00652]).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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