DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment
Acknowledgment is made of applicant's Amendment, filed 12-18-2025. The changes and remarks disclosed therein have been considered.
Claim(s) 2 and 10 has/have been amended, claim(s) 18-21 has/have been cancelled, and, claim(s) 2-17 remain(s) pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-8 and 10-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Konevecki, US 20160300885 A1, in view of Nardi, US 20190115391 A1.
As to claim 2, Konevecki discloses memory device (see Konevecki Fig 3) comprising:
a memory array of memory cells (see Konevecki Fig 4 Ref 10) structured as a vertical 3D memory (see Konevecki Fig 3) including a plurality of word lines (see Konevecki Fig 3 Refs WL1 and WL2) configured orthogonally (see Konevecki Fig 3) to a plurality of digit lines (see Konevecki Fig 3 Ref LBL1 and LBL2), wherein
each of the plurality of digit lines crosses least a couple of the plurality of word lines (see Konevecki Fig 3); and
a selection transistor (see Konevecki Fig 3 Ref 510) at one end of a corresponding digit line of the plurality of digit lines (see Konevecki Fig 3 Ref 510), wherein
the selection transistor is a thin film transistor (TFT) (see Konevecki Fig 7) for selecting the corresponding digit line and accessing at least a memory cell associated with the corresponding digit line (see Konevecki Fig 9 Ref 542).
Konevecki does not appear to explicitly disclose respective storage element materials of vertically adjacent memory cells, of the memory array, are physically isolated from each other.
Nardi discloses respective storage element materials of vertically adjacent memory cells, of the memory array, are physically isolated from each other (see Nardi Fig 11I Ref PCM).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a memory device, as disclosed by Konevecki, may incorporate isolated storage element materials, as disclosed by Nardi. The inventions are well known variants of 3D memory structures, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is their Nardi’s attempt to improve memory stability (see Nardi Para [0022]).
As to claim 3, Konevecki and Nardi disclose the memory device of claim 2, wherein
a matrix of TFTs (see Konevecki Fig 3 Ref 510) is provided under or above the plurality of digit lines with one transistor for each of the plurality of digit lines (see Konevecki Fig 3 Ref 510).
As to claim 4, Konevecki and Nardi discloses the memory device of claim 3, wherein
a peripheral circuitry (see Konevecki Fig 3 Ref CMOS Substrate) is formed under (see Konevecki Fig 3 Ref CMOS Substrate) the matrix with decoding circuitry for word lines and bit lines (see Konevecki Fig 3 Ref Row Select Gate Driver).
Konevecki does not appear to explicitly disclose sense amplifiers.
However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that the disclosed sense amplifiers of Konevecki would be place in the CMOS section as well (see Konevecki Paras [0044] and [0056], Fig 3 Ref GBL1, and Fig 4 Ref GBL). Placing sense amplifiers under arrays allows the integrated circuit to be smaller (see Konevecki Para [0056]).
As to claim 5, Konevecki and Nardi disclose the memory device of claim 3, wherein
the TFTs are formed in a polysilicon layer (see Konevecki Para [0060]).
As to claim 6, Konevecki and Nardi disclose the memory device of claim 2, further comprising
a peripheral circuit layer (see Konevecki Fig 3 Ref CMOS Substrate) having sense amplifiers (see Konevecki Paras [0044] and [0056], Fig 3 Ref GBL1, and Fig 4 Ref GBL) and decoding circuitry (see Konevecki Fig 3 Ref Row Select Gate Driver) realized in a silicon substrate (see Konevecki Fig 3 Ref CMOS Substrate; CMOS without mentioning an exotic substrate is commonly understood to be a silicon substrate.).
As to claim 7, Konevecki and Nardi disclose the memory device of claim 2, wherein:
the TFT is an n-metal-oxide-semiconductor (NMOS) transistor with a drain region coupled to the corresponding digit line (see Konevecki Fig 8 Ref 506 and Fig 3 Ref 510).
As to claim 8, Konevecki and Nardi disclose the memory device of claim 2, wherein
the TFT comprises two gate regions (see Konevecki Fig 7 Ref 507) in parallel (see Konevecki Fig 3 Ref 510) with a gate oxide at one side of a channel region and another gate oxide at another side of the channel region (see Konevecki Fig 7 Ref 505).
As to claim 10, Konevecki and Nardi disclose a memory device (see Konevecki Fig 3) comprising:
a memory array (see Konevecki Fig 4 Ref 10) structured as vertical 3D memory (see Konevecki Fig 3), the memory array comprising: a plurality of memory cells (see Konevecki Fig 4 Ref 10) wherein
respective storage element materials of vertically adjacent memory cells, of the plurality of memory cells, are physically isolated from each other (see Nardi Fig 11I Ref PCM); a plurality of digit lines (see Konevecki Fig 3 Ref LBL1 and LBL2); a plurality of word lines (see Konevecki Fig 3 Refs WL1 and WL2) orthogonal (see Konevecki Fig 3) to the plurality of digit lines, each of the plurality of digit lines crossing one or more of the plurality of word lines (see Konevecki Fig 3); and a plurality of selection transistors each coupled with a respective digit line of the plurality of digit lines (see Konevecki Fig 3 Ref 510), each selection transistor being a thin film transistor (TFT) (see Konevecki Fig 7) configured to select the respective digit line and access one or more memory cells associated with the respective digit line (see Konevecki Fig 9 Ref 542).
As to claim 11, Konevecki and Nardi disclose the memory device of claim 10, wherein
the plurality of selection transistors comprises a matrix of TFTs (see Konevecki Fig 3 Ref 510) positioned above or below the plurality of digit lines (see Konevecki Fig 3 Ref 510), wherein
each of the matrix of TFTs is associated with a corresponding digit line of the plurality of digit lines (see Konevecki Fig 3 Ref 510).
As to claim 12, Konevecki and Nardi disclose discloses the memory device of claim 11, further comprising:
peripheral circuitry (see Konevecki Fig 3 Ref CMOS Substrate) formed under (see Konevecki Fig 3 Ref CMOS Substrate) the matrix of TFTs, the peripheral circuitry comprising one or more sense amplifiers (see Konevecki Paras [0044] and [0056], Fig 3 Ref GBL1, and Fig 4 Ref GBL) and decoding circuitry (see Konevecki Fig 3 Ref Row Select Gate Driver) associated with the plurality of word lines and the plurality of digit lines.
As to claim 13, Konevecki and Nardi disclose the memory device of claim 11, wherein
the matrix of TFTs is formed in a polysilicon layer (see Konevecki Para [0060]).
As to claim 14, Konevecki and Nardi disclose the memory device claim 10, further comprising:
a peripheral circuit layer (see Konevecki Fig 3 Ref CMOS Substrate) comprising one or more sense amplifiers (see Konevecki Paras [0044] and [0056], Fig 3 Ref GBL1, and Fig 4 Ref GBL) and decoding circuitry (see Konevecki Fig 3 Ref Row Select Gate Driver) positioned in a silicon substrate (see Konevecki Fig 3 Ref CMOS Substrate; CMOS without mentioning an exotic substrate is commonly understood to be a silicon substrate.).
As to claim 15, Konevecki and Nardi disclose the memory device of claim 10, wherein one or more TFTs associated with the plurality of selection transistors each comprises: an n-metal-oxide-semiconductor (NMOS) transistor with a drain region coupled to the respective digit line associated with the TFT (see Konevecki Fig 8 Ref 506 and Fig 3 Ref 510).
As to claim 16, Konevecki and Nardi disclose the memory device of claim 10, wherein
one or more TFTs associated with the plurality of selection transistors each comprises: two gate regions (see Konevecki Fig 7 Ref 507) in parallel (see Konevecki Fig 3 Ref 510) with a first gate oxide at a first side of a channel region and a second gate oxide at a second side of the channel region (see Konevecki Fig 7 Ref 505).
Claim(s) 9 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Konevecki, US 20160300885 A1 and Nardi, US 20190115391 A1, in view of Yamazaki, US 20210135010 A1.
As to claim 9, Konevecki and Nardi disclose the memory device of claim 2, comprising
a building block (see Konevecki Fig 15) comprising: a respective memory layer (see Konevecki Fig 15 Ref Storage Layer) with a respective plurality of word lines (see Konevecki Fig 15 Ref 536) configured orthogonally to a respective plurality of digit lines (see Konevecki Fig 15 Ref 571 and Fig 12j Ref 558), each digit line in the respective plurality of digit lines crossing at least a couple of word lines in the respective plurality of word lines (see Konevecki Fig 3), and a respective pillar selection layer with a respective plurality of thin film transistors (TFT) each TFT for selecting a corresponding digit line in the respective plurality of digit lines (see Konevecki Fig 15 Ref Pillar Select Layer).
Konevecki does not appear to explicitly disclose a stack of a plurality of building blocks.
Yamazaki discloses a stack of a plurality of building blocks (see Yamazaki Fig 50A Refs 400a and 400b).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a memory device, as disclosed by Konevecki and Nardi, may be stacked repetitively, as disclosed by Yamazaki. The inventions are well known variants of 3D memory structures, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is their Yamazaki’s attempt to reduce power consumption (see Yamazaki Para [0508]).
As to claim 17, Konevecki, Nardi, and Yamazaki disclose the memory device of claim 10, comprising:
a stack of building blocks (see Konevecki Fig 15 and see Yamazaki Fig 50A Refs 400a and 400b), each building block comprising: a respective memory layer (see Konevecki Fig 15 Ref Storage Layer) having a second plurality of word lines (see Konevecki Fig 3 Refs WL1 and WL2) orthogonal to a second plurality of digit lines (see Konevecki Fig 3 Ref LBL1 and LBL2), each digit line of the second plurality of digit lines crossing one or more word line of the second plurality of word lines (see Konevecki Fig 3), and a respective pillar selection layer (see Konevecki Fig 15 Ref Pillar Select Layer) having a respective plurality of TFTs (see Konevecki Fig 7 and Fig 3 Ref 510), each of the plurality of TFTs configured to select a corresponding digit line of the second plurality of digit lines (see Konevecki Fig 3 Ref 510).
Response to Arguments
Applicant's arguments filed 12/18/2025 have been fully considered but they are not persuasive.
New art has been provided which reads on the amended language.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICHARD ELMS can be reached at (517)272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 02/09/2026
Prosecution Insights